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Threads Starting Aug 2010
148550: 10/08/01: Giorgos Tzampanakis: Differences between Verilog versions
148561: 10/08/01: Jonathan Bromley: Re: Differences between Verilog versions
148802: 10/08/26: Ramesh: Re: Differences between Verilog versions
148598: 10/08/04: <sharp@cadence.com>: Re: Differences between Verilog versions
148563: 10/08/02: Rice: Modify UCF file generated with MIG
148564: 10/08/02: Gabor: Re: Modify UCF file generated with MIG
148569: 10/08/02: Rice: Re: Modify UCF file generated with MIG
148565: 10/08/02: Frank van Eijkelenburg: DMA operation to 64-bits PC platform (continued)
148567: 10/08/02: glen herrmannsfeldt: Re: DMA operation to 64-bits PC platform (continued)
148571: 10/08/03: Frank van Eijkelenburg: Re: DMA operation to 64-bits PC platform (continued)
148578: 10/08/03: alpha: Re: DMA operation to 64-bits PC platform (continued)
148606: 10/08/05: sreekanth: Re: DMA operation to 64-bits PC platform (continued)
148644: 10/08/11: Frank van Eijkelenburg: Re: DMA operation to 64-bits PC platform (continued)
148566: 10/08/02: Gladys: how to store data in i2c slave
148568: 10/08/02: Gabor: Re: how to store data in i2c slave
148572: 10/08/03: =?ISO-8859-1?Q?Jaime_Andr=E9s_Aranguren_Cardona?=: Accelogic is looking for a Senior FPGA Engineer
148573: 10/08/03: embedded: PIT interrupt in Xilinx
148574: 10/08/03: muhammad_umer: Xilinx EasyPath Pricing
148575: 10/08/03: Gabor: Re: Xilinx EasyPath Pricing
148577: 10/08/03: =?ISO-8859-1?Q?Jaime_Andr=E9s_Aranguren_Cardona?=: Re: Xilinx EasyPath Pricing
148583: 10/08/03: Kolja Sulimma: Re: Xilinx EasyPath Pricing
148599: 10/08/05: muhammad_umer: Re: Xilinx EasyPath Pricing
148604: 10/08/05: Jeff Cunningham: Re: Xilinx EasyPath Pricing
148576: 10/08/03: KJ: Re: Connecting "signed" to "std_logic_vector" ports.
148579: 10/08/03: Andy: Re: Connecting "signed" to "std_logic_vector" ports.
148580: 10/08/03: Tim Wescott: Xilinx ISE Webpack and Pipeline Optimization
148581: 10/08/03: Rob Gaddi: Re: Xilinx ISE Webpack and Pipeline Optimization
148582: 10/08/03: Manny: Re: Xilinx ISE Webpack and Pipeline Optimization
148584: 10/08/03: Steve Pope: Re: Xilinx ISE Webpack and Pipeline Optimization
148585: 10/08/03: Andy: Re: Xilinx ISE Webpack and Pipeline Optimization
148586: 10/08/03: emeb: Re: Xilinx ISE Webpack and Pipeline Optimization
148587: 10/08/03: Angela O: Vendor Tool Stability
148590: 10/08/04: Gabor: Re: Vendor Tool Stability
148591: 10/08/04: Rob Gaddi: Re: Vendor Tool Stability
148608: 10/08/05: Nico Coesel: Re: Vendor Tool Stability
148609: 10/08/05: Rob Gaddi: Re: Vendor Tool Stability
148610: 10/08/05: Tim Wescott: Re: Vendor Tool Stability
148612: 10/08/06: David Brown: Re: Vendor Tool Stability
148614: 10/08/06: Jason Thibodeau: Re: Vendor Tool Stability
148596: 10/08/04: KJ: Re: Vendor Tool Stability
148616: 10/08/06: John McCaskill: Re: Vendor Tool Stability
148588: 10/08/04: salimbaba: Logic implementation probelm
148589: 10/08/04: Gabor: Re: Logic implementation probelm
148601: 10/08/05: salimbaba: Re: Logic implementation probelm
148603: 10/08/05: Jeff Cunningham: Re: Logic implementation probelm
148602: 10/08/05: Gabor: Re: Logic implementation probelm
148592: 10/08/04: alessandro.strazzero@gmail.com: A question from a VHDL beginner
148593: 10/08/04: Jon Elson: Re: A question from a VHDL beginner
148594: 10/08/04: John Adair: Re: A question from a VHDL beginner
148615: 10/08/06: Mike Treseler: Re: A question from a VHDL beginner
148618: 10/08/07: Ammar2k: Re: A question from a VHDL beginner
148595: 10/08/04: Aragorc: Generic parameters in Actel Libero SmartDesign Components
148617: 10/08/06: Joan@Actel: Re: Generic parameters in Actel Libero SmartDesign Components
148597: 10/08/04: KJ: Re: Connecting "signed" to "std_logic_vector" ports.
148600: 10/08/05: siriokds: Spartan 3AN Starter Kit. Sell.
148607: 10/08/05: rafayhasan: Verification of the SEU estimates
148611: 10/08/06: chinnathurai: xilinx usb cable
148613: 10/08/06: Socrates: Re: xilinx usb cable
148619: 10/08/07: lastminutepanic: VHDL newbie- stuck just weeks before project submission :(..please
148620: 10/08/09: Thomas Stanka: Re: VHDL newbie- stuck just weeks before project submission
148621: 10/08/09: Kolja Sulimma: Re: VHDL newbie- stuck just weeks before project submission
148622: 10/08/09: KJ: Re: VHDL newbie- stuck just weeks before project submission
148626: 10/08/10: Thomas Stanka: Re: VHDL newbie- stuck just weeks before project submission
148639: 10/08/10: Andy: Re: VHDL newbie- stuck just weeks before project submission
148623: 10/08/09: ColdStart: Signal value clears for no reason [VHDL, ISE 10.1]
148624: 10/08/09: KJ: Re: Signal value clears for no reason [VHDL, ISE 10.1]
148625: 10/08/09: Ed McGettigan: Re: Signal value clears for no reason [VHDL, ISE 10.1]
148634: 10/08/10: Gabor: Re: Signal value clears for no reason [VHDL, ISE 10.1]
148637: 10/08/10: KJ: Re: Signal value clears for no reason [VHDL, ISE 10.1]
148627: 10/08/10: Neill Arnell: Multiple builds with different top-level generic
148628: 10/08/10: Benjamin Krill: Re: Multiple builds with different top-level generic
148633: 10/08/10: KJ: Re: Multiple builds with different top-level generic
148629: 10/08/10: Fredxx: Instantiating non-global clock buffers (Xilinx ISE)
148630: 10/08/10: Benjamin Krill: Re: Instantiating non-global clock buffers (Xilinx ISE)
148631: 10/08/10: Fredxx: Re: Instantiating non-global clock buffers (Xilinx ISE)
148638: 10/08/10: Fredxx: Re: Instantiating non-global clock buffers (Xilinx ISE)
148635: 10/08/10: Chris Maryan: Re: Instantiating non-global clock buffers (Xilinx ISE)
148636: 10/08/10: Gabor: Re: Instantiating non-global clock buffers (Xilinx ISE)
148646: 10/08/11: Chris Maryan: Re: Instantiating non-global clock buffers (Xilinx ISE)
148632: 10/08/10: Benjamin Krill: Re: Instantiating non-global clock buffers (Xilinx ISE)
148642: 10/08/11: Philip Pemberton: Spartan3a: improving DCM performance and "To achieve optimal
148643: 10/08/10: John McCaskill: Re: Spartan3a: improving DCM performance and "To achieve optimal
148649: 10/08/12: maxascent: Re: Spartan3a: improving DCM performance and
148660: 10/08/13: John_H: Re: Spartan3a: improving DCM performance and
148648: 10/08/12: Philip Pemberton: Re: Spartan3a: improving DCM performance and "To achieve optimal
148650: 10/08/12: Philip Pemberton: Re: Spartan3a: improving DCM performance and
148691: 10/08/17: Andy Peters: Re: Spartan3a: improving DCM performance and "To achieve optimal
148652: 10/08/12: FPGA: XC5VTX240T-2FF1759I4177
148653: 10/08/12: MM: Re: XC5VTX240T-2FF1759I4177
148654: 10/08/12: Ed McGettigan: Re: XC5VTX240T-2FF1759I4177
148655: 10/08/13: aaron123: How to use VIO and core inserter at the same time.
148659: 10/08/13: self: Re: How to use VIO and core inserter at the same time.
148661: 10/08/14: Ed McGettigan: Re: How to use VIO and core inserter at the same time.
148664: 10/08/16: aaron123: Re: How to use VIO and core inserter at the same time.
148662: 10/08/15: Antti: Re: How to use VIO and core inserter at the same time.
148663: 10/08/15: Ed McGettigan: Re: How to use VIO and core inserter at the same time.
148665: 10/08/16: Antti: Re: How to use VIO and core inserter at the same time.
148666: 10/08/16: John McCaskill: Re: How to use VIO and core inserter at the same time.
148671: 10/08/17: aaron123: Re: How to use VIO and core inserter at the same time.
148695: 10/08/17: aaron123: Re: How to use VIO and core inserter at the same time.
148672: 10/08/17: John McCaskill: Re: How to use VIO and core inserter at the same time.
148657: 10/08/13: Robert Miles: Re: SPAM Re: Fueling your car with natural gas from home
148658: 10/08/13: self: CoreTimer programming in Actel SoftConsole
148667: 10/08/16: hvo: VDHL initializing
148668: 10/08/16: Mike Treseler: Re: VDHL initializing
148669: 10/08/17: Mark McDougall: Re: VDHL initializing
148670: 10/08/17: Jonathan Bromley: Re: VDHL initializing
148681: 10/08/17: hvo: Re: VDHL initializing
148686: 10/08/17: Jonathan Bromley: Re: VDHL initializing
148693: 10/08/17: hvo: Re: VDHL initializing
148698: 10/08/18: RCIngham: Re: VDHL initializing
148716: 10/08/18: hvo: Re: VDHL initializing
148717: 10/08/18: hvo: Re: VDHL initializing
148730: 10/08/18: hvo: Re: VDHL initializing
148718: 10/08/18: Mike Treseler: Re: VDHL initializing
148724: 10/08/18: KJ: Re: VDHL initializing
148736: 10/08/18: KJ: Re: VDHL initializing
148673: 10/08/17: somayeh2010: I have problem in writing testbench
148674: 10/08/17: Jonathan Bromley: Re: I have problem in writing testbench
148675: 10/08/17: stevem1: CPLD development board with 8-bit wide Flash/EEProm
148676: 10/08/17: Rob Gaddi: Re: CPLD development board with 8-bit wide Flash/EEProm
148679: 10/08/17: stevem1: Re: CPLD development board with 8-bit wide Flash/EEProm
148734: 10/08/18: -jg: Re: CPLD development board with 8-bit wide Flash/EEProm
148779: 10/08/20: John Adair: Re: CPLD development board with 8-bit wide Flash/EEProm
148677: 10/08/17: Rice: SDK example from Xilinx do not compile
148690: 10/08/17: Gabor: Re: SDK example from Xilinx do not compile
148692: 10/08/17: Rice: Re: SDK example from Xilinx do not compile
148720: 10/08/18: Anssi Saari: Re: SDK example from Xilinx do not compile
148723: 10/08/18: Brian Drummond: Re: SDK example from Xilinx do not compile
148712: 10/08/18: Gabor: Re: SDK example from Xilinx do not compile
148773: 10/08/20: Rice: Re: SDK example from Xilinx do not compile
148678: 10/08/17: rupertlssmith@googlemail.com: Getting started with FPGA
148680: 10/08/17: glen herrmannsfeldt: Re: Getting started with FPGA
148682: 10/08/17: Tim Wescott: Re: Getting started with FPGA
148684: 10/08/17: Andrew Feldhaus: Re: Getting started with FPGA
148685: 10/08/17: Jonathan Bromley: Re: Getting started with FPGA
148687: 10/08/17: Tim Wescott: Re: Getting started with FPGA
148688: 10/08/17: Tim Wescott: Re: Getting started with FPGA
148701: 10/08/18: Nial Stewart: Re: Getting started with FPGA
148702: 10/08/18: Nial Stewart: Re: Getting started with FPGA
148705: 10/08/18: Nial Stewart: Re: Getting started with FPGA
148714: 10/08/18: Michael Kellett: Re: Getting started with FPGA
148726: 10/08/18: glen herrmannsfeldt: Re: Getting started with FPGA
148707: 10/08/18: Nial Stewart: Re: Getting started with FPGA
148722: 10/08/18: Tim Wescott: Re: Getting started with FPGA
148735: 10/08/19: Symon: Re: Getting started with FPGA
148743: 10/08/19: Symon: Re: Getting started with FPGA
148745: 10/08/19: Nial Stewart: Re: Getting started with FPGA
148750: 10/08/19: Symon: Re: Getting started with FPGA
148689: 10/08/17: Mike Treseler: Re: Getting started with FPGA
148694: 10/08/17: Chris Abele: Re: Getting started with FPGA
148719: 10/08/18: Anssi Saari: Re: Getting started with FPGA
148696: 10/08/18: rupertlssmith@googlemail.com: Re: Getting started with FPGA
148697: 10/08/18: Oscar Almer: Re: Getting started with FPGA
148699: 10/08/18: =?ISO-8859-1?B?RGlu52F5IEFr5/ZyZW4=?=: Re: Getting started with FPGA
148700: 10/08/18: =?ISO-8859-1?B?RGlu52F5IEFr5/ZyZW4=?=: Re: Getting started with FPGA
148703: 10/08/18: rupertlssmith@googlemail.com: Re: Getting started with FPGA
148704: 10/08/18: rupertlssmith@googlemail.com: Re: Getting started with FPGA
148709: 10/08/18: vanepp: Re: Getting started with FPGA
148710: 10/08/18: rupertlssmith@googlemail.com: Re: Getting started with FPGA
148711: 10/08/18: Gabor: Re: Getting started with FPGA
148713: 10/08/18: rupertlssmith@googlemail.com: Re: Getting started with FPGA
148731: 10/08/18: John Adair: Re: Getting started with FPGA
148738: 10/08/19: Andrew Feldhaus: Re: Getting started with FPGA
148739: 10/08/19: rupertlssmith@googlemail.com: Re: Getting started with FPGA
148740: 10/08/19: rupertlssmith@googlemail.com: Re: Getting started with FPGA
148746: 10/08/19: Bryan: Re: Getting started with FPGA
148706: 10/08/18: CP: vMAGIC 0.3.9 released
148708: 10/08/18: Sink0: FPGA PCI BOARD .. Few Questions
148725: 10/08/18: Brian Drummond: Re: FPGA PCI BOARD .. Few Questions
148728: 10/08/18: Bryan: Re: FPGA PCI BOARD .. Few Questions
148732: 10/08/18: glen herrmannsfeldt: Re: FPGA PCI BOARD .. Few Questions
148733: 10/08/18: Sink0: Re: FPGA PCI BOARD .. Few Questions
148742: 10/08/19: RCIngham: Re: FPGA PCI BOARD .. Few Questions
148744: 10/08/19: Sink0: Re: FPGA PCI BOARD .. Few Questions
148758: 10/08/19: Frank Buss: Re: FPGA PCI BOARD .. Few Questions
148759: 10/08/19: Sink0: Re: FPGA PCI BOARD .. Few Questions
148768: 10/08/19: Sink0: Re: FPGA PCI BOARD .. Few Questions
148769: 10/08/19: Sink0: Re: FPGA PCI BOARD .. Few Questions
148775: 10/08/20: Sink0: Re: FPGA PCI BOARD .. Few Questions
148729: 10/08/18: Nico Coesel: Re: FPGA PCI BOARD .. Few Questions
148741: 10/08/19: John Adair: Re: FPGA PCI BOARD .. Few Questions
148761: 10/08/19: John Adair: Re: FPGA PCI BOARD .. Few Questions
148774: 10/08/20: John Adair: Re: FPGA PCI BOARD .. Few Questions
148715: 10/08/18: Fredxx: CE compliance testing
148721: 10/08/18: General Schvantzkoph: Re: CE compliance testing
148747: 10/08/19: Fredxx: Re: CE compliance testing
148764: 10/08/19: Mike Harrison: Re: CE compliance testing
148763: 10/08/19: Mike Harrison: Re: CE compliance testing
148727: 10/08/18: Nico Coesel: Re: CE compliance testing
148737: 10/08/19: Michael Kellett: Re: CE compliance testing
148749: 10/08/19: Fredxx: Re: CE compliance testing
148765: 10/08/19: Mike Harrison: Re: CE compliance testing
148762: 10/08/19: Mike Harrison: Re: CE compliance testing
148748: 10/08/19: Fredxx: Re: CE compliance testing
148752: 10/08/19: Morten Leikvoll: Re: CE compliance testing
148756: 10/08/19: Fredxx: Re: CE compliance testing
148766: 10/08/19: Mike Harrison: Re: CE compliance testing
148770: 10/08/20: Morten Leikvoll: Re: CE compliance testing
148771: 10/08/20: Stef: Re: CE compliance testing
148776: 10/08/20: Nico Coesel: Re: CE compliance testing
148780: 10/08/21: Stef: Re: CE compliance testing
148760: 10/08/19: Nico Coesel: Re: CE compliance testing
148767: 10/08/19: Mike Harrison: Re: CE compliance testing
148751: 10/08/19: Symon: Re: CE compliance testing
148755: 10/08/19: Fredxx: Re: CE compliance testing
148778: 10/08/20: Leon: Re: CE compliance testing
148782: 10/08/22: Michael Schwingen: Re: CE compliance testing
148753: 10/08/19: Morten Leikvoll: Altera blasters missing ESD protection
148754: 10/08/19: Symon: Re: Altera blasters missing ESD protection
148757: 10/08/19: Thomas Entner: Re: Altera blasters missing ESD protection
148772: 10/08/20: maverick: Analog Video Processing module
148777: 10/08/20: Mike Santarini: Xilinx Xcell Journal Issue 72 Now available
148786: 10/08/24: RCIngham: Re: Xilinx Xcell Journal Issue 72 Now available
148781: 10/08/20: micro: TCP Client using lwIP API
148783: 10/08/23: Marc Jet: Re: TCP Client using lwIP API
148784: 10/08/24: kude: Text compression Huffman Encoder and Decoder
148787: 10/08/24: David Brown: Re: Text compression Huffman Encoder and Decoder
148791: 10/08/24: kude: Re: Text compression Huffman Encoder and Decoder
148792: 10/08/24: Tim Wescott: Re: Text compression Huffman Encoder and Decoder
148790: 10/08/24: RCIngham: Re: Text compression Huffman Encoder and Decoder
148793: 10/08/24: glen herrmannsfeldt: Re: Text compression Huffman Encoder and Decoder
148879: 10/09/06: kude: Re: Text compression Huffman Encoder and Decoder
148883: 10/09/07: Stef: Re: Text compression Huffman Encoder and Decoder
148932: 10/09/12: kude: Re: Text compression Huffman Encoder and Decoder
148933: 10/09/12: kude: Re: Text compression Huffman Encoder and Decoder
148880: 10/09/06: kude: Re: Text compression Huffman Encoder and Decoder
148785: 10/08/24: farhanakram: problem with using DCM of virtex 4
148788: 10/08/24: Jonathan Bromley: Looking to buy some obsolete FPGAs
148789: 10/08/24: Benjamin Couillard: Mismatch between Xilinx FIR interpolation filter
148795: 10/08/25: wicore: Re: Mismatch between Xilinx FIR interpolation filter
148794: 10/08/25: Bert_Paris: New Application Note: Multiple configurations for Altera FPGAs
148796: 10/08/26: Nial Stewart: Re: New Application Note: Multiple configurations for Altera FPGAs
148797: 10/08/26: Nial Stewart: Re: New Application Note: Multiple configurations for Altera FPGAs
148798: 10/08/26: Nial Stewart: Re: New Application Note: Multiple configurations for Altera FPGAs
148799: 10/08/26: Bert_Paris: Re: New Application Note: Multiple configurations for Altera FPGAs
148800: 10/08/26: Gabor: Re: New Application Note: Multiple configurations for Altera FPGAs
148801: 10/08/26: Me: about (low-level) jtag
148807: 10/08/27: jt_eaton: Re: about (low-level) jtag
148803: 10/08/26: =?windows-1252?Q?GaLaKtIkUs=99?=: Spartan-6 - What is the IODRP2_MCB??
148805: 10/08/27: Gabor: Re: Spartan-6 - What is the IODRP2_MCB??
148804: 10/08/27: micro: Checking whether the client is connected to the Server
148808: 10/08/27: Pete Fraser: Plotting sampled data in Matlab
148809: 10/08/27: Randy Yates: Re: Plotting sampled data in Matlab
148810: 10/08/27: Pete Fraser: Re: Plotting sampled data in Matlab
148811: 10/08/28: kadhiem_ayob: Re: Plotting sampled data in Matlab
148819: 10/08/28: Pete Fraser: Re: Plotting sampled data in Matlab
148816: 10/08/28: Fred Marshall: Re: Plotting sampled data in Matlab
148818: 10/08/28: Pete Fraser: Re: Plotting sampled data in Matlab
148817: 10/08/28: Manny: Re: Plotting sampled data in Matlab
148820: 10/08/28: Pete Fraser: Re: Plotting sampled data in Matlab
148823: 10/08/29: kadhiem_ayob: Re: Plotting sampled data in Matlab
148821: 10/08/28: Manny: Re: Plotting sampled data in Matlab
148822: 10/08/28: Manny: Re: Plotting sampled data in Matlab
148812: 10/08/28: kadhiem_ayob: Stratix iv PLLs ref clock
148813: 10/08/28: Frank Buss: Re: Stratix iv PLLs ref clock
148814: 10/08/28: kadhiem_ayob: Re: Stratix iv PLLs ref clock
148815: 10/08/28: Michael S: Re: Stratix iv PLLs ref clock
148824: 10/08/29: Sharath Raju: FPGA DAC Interface
148825: 10/08/29: John_H: Re: FPGA DAC Interface
148826: 10/08/30: Brian Drummond: Re: FPGA DAC Interface
148827: 10/08/30: MM: Re: FPGA DAC Interface
148828: 10/08/31: Symon: Re: FPGA DAC Interface
148829: 10/08/31: Plutonium: BRAM initialization in EDK 12.2
148831: 10/08/31: Shakes: dct verilog
148832: 10/09/01: glen herrmannsfeldt: Re: dct verilog
148833: 10/08/31: KJ: Re: dct verilog
148847: 10/09/02: d_s_klein: Re: dct verilog
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Compare FPGA features and resources
Threads starting:
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