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On Aug 3, 8:47=A0am, "muhammad_umer" <muhammad_umer@n_o_s_p_a_m.comsats.edu.pk> wrote: > Hi, i am working on a project where i am developing my architecture on > Virtex-4 FPGA. My ultimate goal is to port my design to Xilinx EasyPath > FPGA. But i dont have any idea, how xilinx charges for implementing desig= n > on EasyPath. there is no guide wither they charge against gate count, or > FPGA family. what ever criteria they use, i want some general quotation > which can give me idea about pricing. Hoping for quick response. thanks! > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com You'll get a quicker response if you contact your Xilinx sales rep.Article: 148576
On Jul 31, 1:50=A0pm, Andy <jonesa...@comcast.net> wrote: > It would break existing code that used signed/unsigned like SLV, and > needed the tri-state, multi-driver logic. Also, elements of unsigned > would not be SL, with the same problem. > Actually, I intended my question more along the lines of if signed/ unsigned were changed to be collections of std_ulogic rather than std_logic, how many would really notice/care? I understand that those who use signed/unsigned with multiple drivers would be affected...but how many of those cases are actually out there? So, do *you* use multiple drivers on signed/unsigned signals? Is that actually important to you? KJArticle: 148577
On 3 Aug., 15:28, Gabor <ga...@alacron.com> wrote: > On Aug 3, 8:47=A0am, "muhammad_umer" > > <muhammad_umer@n_o_s_p_a_m.comsats.edu.pk> wrote: > > Hi, i am working on a project where i am developing my architecture on > > Virtex-4 FPGA. My ultimate goal is to port my design to Xilinx EasyPath > > FPGA. But i dont have any idea, how xilinx charges for implementing des= ign > > on EasyPath. there is no guide wither they charge against gate count, o= r > > FPGA family. what ever criteria they use, i want some general quotation > > which can give me idea about pricing. Hoping for quick response. thanks= ! > > > --------------------------------------- =A0 =A0 =A0 =A0 > > Posted throughhttp://www.FPGARelated.com > > You'll get a quicker response if you contact your Xilinx sales rep. Probably asking for some 100K... Still, less than ASIC.Article: 148578
On Aug 3, 3:26 am, Frank van Eijkelenburg <fei.technolut...@gmail.com> wrote: > On Aug 2, 5:28 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > > > > > Frank van Eijkelenburg <fei.technolut...@gmail.com> wrote: > > > > I have a custom made PCIe board with a Virtex 5 FPGA on which I > > > implemented a DMA unit which uses the PCIe endpoint block plus v1.14. > > > I also implemented simple read/write operations from the PC to the > > > board (the board responds with completion TLPs). The read/write > > > operations are working, DMA is not working (transferring data from > > > FPGA to PC). > > > (snip) > > > > When I start a DMA operation by writing a register in the FPGA, I can > > > see in chipscope the correct physical addresses in the TLP header (of > > > the memory write requests). However, I do not see the correct values > > > in the allocated memory at the PC. What can I do to check where it is > > > going wrong? > > > Not having tried to do DMA through PCI before, is data being > > written, but the wrong data? > > That is what I do not know. Yes the correct data is send to the PC, > but if I readout the memory the values are unchanged. > > > > > I would try writing all zeros or all ones and see if those come > > through fine. It could be timing between the FPGA and PCI such > > that the wrong data is being latched. > > > Then try slightly less predictable data and see what gets through. > > > -- glen > > If it was timing, I expect the other way around also problems (which I > don't have). Also single memory read/write requests send from the PC > are working correctly. Does CPU caches get snooped when DMA wrote into host memory? If not, then you may not see right data by normal read.Article: 148579
On Aug 3, 8:40=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > On Jul 31, 1:50=A0pm, Andy <jonesa...@comcast.net> wrote: > > > It would break existing code that used signed/unsigned like SLV, and > > needed the tri-state, multi-driver logic. Also, elements of unsigned > > would not be SL, with the same problem. > > Actually, I intended my question more along the lines of if signed/ > unsigned were changed to be collections of std_ulogic rather than > std_logic, how many would really notice/care? =A0I understand that those > who use signed/unsigned with multiple drivers would be affected...but > how many of those cases are actually out there? =A0So, do *you* use > multiple drivers on signed/unsigned signals? =A0Is that actually > important to you? > > KJ Mostly in places where I have an inout port (or procedure argument) of a record type, and I need resolution functions to manage in and out elements more often than I actually use a bidirectional element. My test benches tend to have lots of procedures like read/write(bus, address, data) I have also used unsigned on tri-stated primary IOs of FPGAs (it is easy enough to convert them back to SLV if I need to use the gate level models). Internally, I have used them with a tri-state bus description, knowing full-well that the synthesis tool would convert them to muxes for me. The added benefit is that the synthesis tool can assume that the tri- state enables are mutually exclusive, which allows it to optimize the muxes. Sometimes it is just easier to describe an interface with a bus, than to create the mux and the plumbing for it. I don't usually do truly bi-directional busses, but sometimes... So, yes, I have used them in several areas. IMHO, changes to the language or standard packages must be backwards compatible (even though in rare cases in the past they have not been so), so that they don't break anyone's code, regardless of how common (or even "useful") a given usage is. The "prime directive" WRT changes to the standards should be "do no harm". If we need a different numeric_std-like package, so be it. AndyArticle: 148580
Here's a naive question, from a sometime FPGA user: A long time ago, a friend of mine who does _real_ digital design work was telling me how cool the (then new) Mentor tools were, because you could do a whole bunch of natural-looking combinational Verilog code in a module, then at the very end you could put in a bunch of register delays, and the tools would figure out how to distribute the delays in your combinational code to get a nicely pipelined bit of logic. Has this nifty technology migrated into Xilinx tools? Or if I need pipelining, do I need to figure it out myself? -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 148581
On 8/3/2010 10:25 AM, Tim Wescott wrote: > Here's a naive question, from a sometime FPGA user: > > A long time ago, a friend of mine who does _real_ digital design work > was telling me how cool the (then new) Mentor tools were, because you > could do a whole bunch of natural-looking combinational Verilog code in > a module, then at the very end you could put in a bunch of register > delays, and the tools would figure out how to distribute the delays in > your combinational code to get a nicely pipelined bit of logic. > > Has this nifty technology migrated into Xilinx tools? Or if I need > pipelining, do I need to figure it out myself? > Theoretically yes, practically I've had great difficulty getting the tools to distribute any more than one level of pipeline delay. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 148582
On Aug 3, 6:25=A0pm, Tim Wescott <t...@seemywebsite.com> wrote: > Here's a naive question, from a sometime FPGA user: > > A long time ago, a friend of mine who does _real_ digital design work > was telling me how cool the (then new) Mentor tools were, because you > could do a whole bunch of natural-looking combinational Verilog code in > a module, then at the very end you could put in a bunch of register > delays, and the tools would figure out how to distribute the delays in > your combinational code to get a nicely pipelined bit of logic. > > Has this nifty technology migrated into Xilinx tools? =A0Or if I need > pipelining, do I need to figure it out myself? You have to always be cautious of what the tools can or can not do for you. My experience tells me that cheap tools are better off fed the design with a spoon. Then comes a host of other problems to do with bugs everywhere, e.g. a design with a MACC has to be broken into separate multiply and accumulate blocks and then retimed. Pure joy! -MomoArticle: 148583
>From a Xilinx press release: "For example, list price for a Spartan-3 EasyPath XCE3S1500 is $12.95* U.S. with $75,000 NRE and 50,000 unit minimum order quantities in second half calendar year 2005." KoljaArticle: 148584
On Aug 3, 6:25 pm, Tim Wescott <t...@seemywebsite.com> wrote: > Here's a naive question, from a sometime FPGA user: > > A long time ago, a friend of mine who does _real_ digital design work > was telling me how cool the (then new) Mentor tools were, because you > could do a whole bunch of natural-looking combinational Verilog code in > a module, then at the very end you could put in a bunch of register > delays, and the tools would figure out how to distribute the delays in > your combinational code to get a nicely pipelined bit of logic. > > Has this nifty technology migrated into Xilinx tools? Or if I need > pipelining, do I need to figure it out myself? Register retiming. All the synthesizers do this. SteveArticle: 148585
But how many re-time over more than one clock cycle? Many can only move logic +/- 1 clock cycle, and some don't do it unless the original design won't meet timing. AndyArticle: 148586
On Aug 3, 1:40=A0pm, spop...@speedymail.org (Steve Pope) wrote: > On Aug 3, 6:25=A0pm, Tim Wescott <t...@seemywebsite.com> wrote: > > > Here's a naive question, from a sometime FPGA user: > > > A long time ago, a friend of mine who does _real_ digital design work > > was telling me how cool the (then new) Mentor tools were, because you > > could do a whole bunch of natural-looking combinational Verilog code in > > a module, then at the very end you could put in a bunch of register > > delays, and the tools would figure out how to distribute the delays in > > your combinational code to get a nicely pipelined bit of logic. > > > Has this nifty technology migrated into Xilinx tools? =A0Or if I need > > pipelining, do I need to figure it out myself? > > Register retiming. =A0All the synthesizers do this. My favorite tool for this was something Synopsys sold years ago called 'Module Compiler'. Apparently they bought another company that actually made this, but my first exposure was at Synopsys. It used a 'Verilog-like' language to specify the logical & mathematical operations without any pipelining. The only registers you'd put in explicitly were those required for state (like accumulators, state machines, etc). It used the target library capabilities to do all the pipelining for you, as well as optimizing the logic & math - sort of a precursor to what became Physical Synthesis. It would spit out a gate- level netlist for the P/R tools and behavioral Verilog for verification. Amazing stuff. Apparently most of Module Compiler was rolled into Design Compiler a while back. Don't know what became of it beyond that. EricArticle: 148587
A project I am considering undertaking would require that an FPGA's implementation flow (synthesis through bitgen) be routinely run in a scripted form at customer locations by the end customer, likely a non- engineer. The RTL input can be assumed to be good. All aspects of the vendor tools would be hidden from the end user via scripts or GUI. The stability of the vendor tools are the biggest concern in this project. I am not tied to any vendor. The performance specs are such that almost any current or last generation FPGA could handle the load. I would appreciate hearing your thoughts on which vendor to consider for this application. Unpredictable errors and crashes are something that must be avoided. Thank you in advance. AngieArticle: 148588
Hey i am using ise 9.1i for synthesizing my designs for spartan 3 fpgas. I am facing a very wierd problem. My system comprises of 1 xcs400 fpga and an ARM 7 processor. My RTL design is very modular. Here is the problem. I have a microcontroller interface in my rtl design to communicate with arm. other portions of my rtl design are related to some other logic implementations.now what happens is that when i change some line of code or logic in the other modules WHICH ARE IN NO WAY CONNECTED TO CONTROLLER INTERFACE, the bit file that is generated causes my processor to crash and go into abort conditions. this happens primarily because of contention on the data bus of the processor. However, i cannot tell why this is happening that a change in logic is some very remote part of the design causes the controller interface to misbehave. Keep in view that my controller interface is perfected and is running perfectly on a couple of other systems.the only difference between a working bit file and a non working bit file is a small change in some other part of the design and it is so small that it may include only a size change of a register. i have pulled down all unused ios and all other setups are exactly the same Regards --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148589
On Aug 4, 9:23=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hey i am using ise 9.1i for synthesizing my designs for spartan 3 fpgas. = I > am facing a very wierd problem. > My system comprises of 1 xcs400 fpga and an ARM 7 processor. My RTL desig= n > is very modular. Here is the problem. > > I have a microcontroller interface in my rtl design to communicate with > arm. other portions of my rtl design are related to some other logic > implementations.now what happens is that when i change some line of code = or > logic in the other modules WHICH ARE IN NO WAY CONNECTED TO CONTROLLER > INTERFACE, the bit file that is generated causes my processor to crash an= d > go into abort conditions. this happens primarily because of contention on > the data bus of the processor. > However, i cannot tell why this is happening that a change in logic is so= me > very remote part of the design causes the controller interface to > misbehave. Keep in view that my controller interface is perfected and is > running perfectly on a couple of other systems.the only difference betwee= n > a working bit file and a non working bit file is a small change in some > other part of the design and it is so small that it may include only a si= ze > change of a register. > > i have pulled down all unused ios and all other setups are exactly the > same > > Regards =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com It's very likely that you are having timing problems. If your design is not properly constrained, the timing can vary significantly from run to run, even for parts of the design that don't change. I assume you at least have PERIOD constraints on any clocks in the design. In addition you should constrain inputs and outputs for setup/hold and clock to out. Alternately turn on the switch in the tools that says to push all of your I/O flip-flops into the IOB's. This will cause the timing at the pin interface to be constant from run to run. There may be cases where you I/O logic cannot be pushed into the IOB's however, so you need to check for these and make sure that you have constrained the timing for them appropriately. A good source of information is your post place&route timing report. Make sure you tell the report generator to add the data sheet section. This gives you a view into the setup/hold and clock to out timing of your design as built. See if there are significant differences between the versions that work and those that don't. Finally another cause of build-to-build design instability is also caused by timing differences but not in a way that lends itself to being constrained. If you have any signals that come in asynchronously or cross clock domains be sure that for each clock they are only registered in one flip-flop. Any further logic in that clock domain should use the output of the same initial synchronizing flip-flop. If the same async input goes through multiple flip-flops, those flip-flops can see the signal change on different clock cycles, and which one sees the signal first can change from build to build based on the relative routing delays from the source to the flip-flop D input. HTH, GaborArticle: 148590
On Aug 3, 11:23=A0pm, Angela O <angieoak...@gmail.com> wrote: > A project I am considering undertaking would require that an FPGA's > implementation flow (synthesis through bitgen) be routinely run in a > scripted form at customer locations by the end customer, likely a non- > engineer. =A0The RTL input can be assumed to be good. =A0All aspects of > the vendor tools would be hidden from the end user via scripts or GUI. > > The stability of the vendor tools are the biggest concern in this > project. =A0I am not tied to any vendor. =A0The performance specs are suc= h > that almost any current or last generation FPGA could handle the > load. > > I would appreciate hearing your thoughts on which vendor to consider > for this application. =A0Unpredictable errors and crashes are something > that must be avoided. > > Thank you in advance. > Angie Having worked with Xilinx tools and devices for many years, I would say that it is possible to have very stable results as long as you know what to avoid. Generally speaking, a design with one system clock and no special feature usage almost never has any issues through the tool chain. Start adding too many clock resources or other special features and you can run into issues where the tools need to be guided to complete the design. I don't know enough about your application to say whether Xilinx tools are stable enough for your purposes. Whichever chip vendor you pick, you will have some things you need to avoid. Only the synthesis portion of the tool chain can be de-coupled from the chip vendor. It would really help if you had extensive experience working with your vendor of choice before going into your own tool implementation. Most of the annoying bugs from Xilinx are not in the actual synthesis / place / route / build, but in the GUI wrapper. Regards, GaborArticle: 148591
On 8/4/2010 6:43 AM, Gabor wrote: > On Aug 3, 11:23 pm, Angela O<angieoak...@gmail.com> wrote: >> A project I am considering undertaking would require that an FPGA's >> implementation flow (synthesis through bitgen) be routinely run in a >> scripted form at customer locations by the end customer, likely a non- >> engineer. The RTL input can be assumed to be good. All aspects of >> the vendor tools would be hidden from the end user via scripts or GUI. >> >> The stability of the vendor tools are the biggest concern in this >> project. I am not tied to any vendor. The performance specs are such >> that almost any current or last generation FPGA could handle the >> load. >> >> I would appreciate hearing your thoughts on which vendor to consider >> for this application. Unpredictable errors and crashes are something >> that must be avoided. >> >> Thank you in advance. >> Angie > > Having worked with Xilinx tools and devices for many years, I would > say that it is possible to have very stable results as long as you > know what to avoid. Generally speaking, a design with one system > clock and no special feature usage almost never has any issues > through the tool chain. Start adding too many clock resources > or other special features and you can run into issues where the > tools need to be guided to complete the design. I don't know > enough about your application to say whether Xilinx tools are > stable enough for your purposes. Whichever chip vendor you > pick, you will have some things you need to avoid. Only the > synthesis portion of the tool chain can be de-coupled from the > chip vendor. It would really help if you had extensive experience > working with your vendor of choice before going into your own > tool implementation. Most of the annoying bugs from Xilinx > are not in the actual synthesis / place / route / build, but in the > GUI wrapper. > > Regards, > Gabor I've had nothing but problems with stability of Xilinx designs, actually. Routinely in going from one version of the toolchain to the next, command line options are changed or deprecated, forcing me to tweak the settings in my Makefile. Right now I'm in the process of opening a Webcase because a design which, under 12.1, was willing to respect IOB=FORCE to push some input flip-flops into the ILOGIC cells for timing reasons, it no longer will under 12.2. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 148592
Dear everybody, I'm a beginner in using the VHDL and I'm experiencing some problems during the testing phase. I have developped a small VHDL model based on an Altera Cyclone FPGA and, using ModelSim, I have tested it in simulation mode. The results from simulation were goods, so I decided to synthesize the model and test it on the FPGA. With my surprise, the model doesn't work well as in ModelSim and I don't understand the reasons. Without to deeply face the problem by analysing the code, based on your skill, could you suggest me some guidelines where to search for the problems ? Maybe I have not applied some important "good rules" to synthesize the model, or whatelse an expert hardware man can imagine ... I have synthesized the model using the latest version of Quartus II and the message window did not report some critical warnings during the compilation. Best Regards /AlessandroArticle: 148593
alessandro.strazzero@gmail.com wrote: > Dear everybody, > > I'm a beginner in using the VHDL and I'm experiencing some problems > during the testing > phase. I have developped a small VHDL model based on an Altera Cyclone > FPGA and, > using ModelSim, I have tested it in simulation mode. The results from > simulation were goods, so I decided to synthesize the model and test > it on the FPGA. > > With my surprise, the model doesn't work well as in ModelSim and I > don't understand the > reasons. Without to deeply face the problem by analysing the code, > based on your skill, > could you suggest me some guidelines where to search for the > problems ? Maybe I have > not applied some important "good rules" to synthesize the model, or > whatelse an expert > hardware man can imagine ... The simulation cannot have timing violations or the analog behavior of signals. The real world implementation is subject to these effects. You may have electrical noise issues either on the power supply, clocks or I/O signals, or a timing violation on inputs coming into the logic. If you have inputs that are not synchronized with the internal FPGA clock, it can have disastrous results on the stability of state machines and similar bus control logic. You do this by specifying a register on the raw input signal, then the internal logic only uses the output of that register, never the raw I/O signal. If the timing between the external device and the FPGA is completely asynchronous, it is best to use TWO sets of synchronizers to avoid metastability conditions where the input changes just as the FF is sampling. JonArticle: 148594
First thing to check is that you have set some basic timing, and pin location, constraints in quartus.You can do this under the Assignments menu in Quartus. Second thing to check is that you have not relyed on sensitivity list gating. Simulators tend to follow the standard in this. Synthesisers usually ignore sensitivity lists. Third if you have more than one clock domain in your design check that your data/signal passing is done in a way to guarantee operation. Lots of posts on clock domain crossing in this news group. John Adair Enterpoint Ltd.- Home of Drigmorn4. The Spartan-6 Embedded Processor Board. On 4 Aug, 19:10, "alessandro.strazz...@gmail.com" <alessandro.strazz...@gmail.com> wrote: > Dear everybody, > > I'm a beginner in using the VHDL and I'm experiencing some problems > during the testing > phase. I have developped a small VHDL model based on an Altera Cyclone > FPGA and, > using ModelSim, I have tested it in simulation mode. The results from > simulation were goods, so I decided to synthesize the model and test > it on the FPGA. > > With my surprise, the model doesn't work well as in ModelSim and I > don't understand the > reasons. Without to deeply face the problem by analysing the code, > based on your skill, > could you suggest me some guidelines where to search for the > problems ? Maybe I have > not applied some important "good rules" to synthesize the model, or > whatelse an expert > hardware man can imagine ... > > I have synthesized the model using the latest version of Quartus II > and the message > window did not report some critical warnings during the compilation. > > Best Regards > > /AlessandroArticle: 148595
Hello I need some help for using Actel Libero IDE. The SmartDesign fonctionnality enable me to design my code as a block diagramm. This is a very convenient way to keep global view of my programm. But I don't know how to set generic parameters with components. I know this is really easy to do with Altera Active HDL, but I can't find the way with Libero. Does anyone knows how to use generics with components? I hope my question is understable. Thank you for your help. +++ --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148596
On Aug 3, 11:23=A0pm, Angela O <angieoak...@gmail.com> wrote: > The stability of the vendor tools are the biggest concern in this > project. =A0I am not tied to any vendor. =A0 Fewer people here complain about brand A tools than brand X...the two companies are the two largest in the FPGA world. Maybe that's because there are more users of brand X tools, or maybe it's because the brand A tools are better. Take both out for a spin and see for yourself. The other way to keep tools stable is simply to not let them change. Lock it down to a specific tool revision and you'll minimize the tool migration issues. > > I would appreciate hearing your thoughts on which vendor to consider > for this application. =A0 Brand A =3D Altera Brand X =3D Xilinx Brand L =3D Lattice which uses brand S synthesis tools Brand S =3D Synplify which can target many different vendors KJArticle: 148597
On Aug 3, 12:04=A0pm, Andy <jonesa...@comcast.net> wrote: > On Aug 3, 8:40=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > IMHO, changes to the language or standard packages must be backwards > compatible (even though in rare cases in the past they have not been > so), Backwards compatibility should not be a 'must have'...although I certainly agree that it is something worth working for to get if you can. Examples of changes that are definitely more onerous to 'used to be working just fine' code were the changes to type 'FILE' and 'shared variables'. > so that they don't break anyone's code, regardless of how common > (or even "useful") a given usage is. I think the cost/benefit should be weighed although just how well one can weigh this with actual users is a bit of a question. > The "prime directive" WRT changes > to the standards should be "do no harm". 'Do no harm' applies to doctors, not engineering standards. If something needs to be improved and is 'worth it' to the users then it should be improved. The definition of whether something is 'worth it' or not is subjective. > If we need a different > numeric_std-like package, so be it. > Maybe just use the fixed point package. The documentation says it uses std_logic as the base, but the actual code says std_ulogic. Thanks for your input on how you use/need multi-driver signed/unsigned Kevin JenningsArticle: 148598
Regarding Jonathan's comment about new keywords added in later revisions of the language: that is one thing that is actually well- documented for each version. The specification of the `begin_keywords directive lists the keywords that were reserved in each revision.Article: 148599
>Hi, i am working on a project where i am developing my architecture on >Virtex-4 FPGA. My ultimate goal is to port my design to Xilinx EasyPath >FPGA. But i dont have any idea, how xilinx charges for implementing design >on EasyPath. there is no guide wither they charge against gate count, or >FPGA family. what ever criteria they use, i want some general quotation >which can give me idea about pricing. Hoping for quick response. thanks! > > > >--------------------------------------- >Posted through http://www.FPGARelated.com > OK,i get some idea of pricing from Xilinx Cost Analyzer. But this is abstract and comparing EasyPath price with competitors ASIC. There is a cell in this calculator which asks to input Easypath unit cost. Can you tell me where i get this unit cost from? As unit costs for FPGA's from xilinx are clearly mentioned, i am unable to get unit cost for EaspyPath FPGA's clearly. One more thing, i google internet and found some articles, mentioning EasythPath saves 80% of FPGA cost. so this mean that, for instance, if FPGA cost $100 then its EasyPath partner will cost $20. Am i correct in my understanding? Please provide me complete pricing detail for all easypath FPGA's families. Thanks in advance. --------------------------------------- Posted through http://www.FPGARelated.com
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