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Pete Fraser pisze: > I'm going to be travelling soon, and will continue to > do FPGA design from the road. I'll need to get a > new laptop for this. > > Any thoughts? > I think something based on the Core i7-620M might > be fast enough and low power, but they seem rare. > Looks like I'll probably end up with something with > a Core i7-720QM or a Core i7-820QM. > Anybody here have any experience with on of these > machines? Is there another processor I should be looking at? > > The obvious OS with a new machine would be Windows 7, > 64-bit, but I'm not sure my software will run on that. > I'm running ISE Foundation 10.1 (and don't plan on > upgrading quite yet). I also use Modelsim XE, but will > be upgrading to Modelsim PE or Aldec. > > It's not clear what software runs on what OS. It seems > that I might be safer with 32-bit XP for the Modelsim > and the Xilinx software. Windows 7 Professional > seems to have a downgrade option to XP. Does that > mean I choose to install one or the other OS, or can > I install both and switch between them? 7 Pro seems > to have some sort of XP mode. Will that work for these > tools? Is there a performance penalty over a real XP > installation? Can I emulate XP 32-bit under W7 64-bit? > > Thanks for your thoughts and suggestions. > > Pete > > Use Remote desktop or similar . You can have really powerful PC for fpga compilation this way. If you have inet connection of course. AdamArticle: 146026
On Mar 2, 12:15=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > Nicely put, but that way lies stagnation and the > ultimate death of our industry. I wasn't suggesting that it is completely impossible to outrun the steamroller, but if you want a much better chance of doing it, you should try running in a different direction than the steamroller is going. If you are only slightly off the path of the steamroller, maybe it will shift its path a bit to follow you, and maybe not. If your path is significantly different from that of the steamroller, there's a better chance that it will ignore you. Other than AMD, the companies that have any success selling x86 processors are targeting niches that Intel didn't focus much effort on, rather than trying to compete with Intel's mainstream parts. Most of them are targetting embedded and low power designs, where Intel's offerings were traditionally weak, though Intel seems to have become much more interested in those in the last few years. Many of those companies, including the one my friend worked at, started their x86 designs with the intent of competing at the high end, and ultimately realized that they couldn't. If you're going to compete with big FPGA vendors, there had better be something that your FPGA is *significantly* (not just slightly) better at than their parts. Whether Tabula's stuff is sufficiently better remains to be seen. > there's no point in creating something that's 10 times as good as > the competition, when something 1.5 times as good > will make you rich. If you're one of the big players, 1.5 times better might be good enough to gain you a bit of market share, but it rarely is sufficient for a startup to gain traction against the big guys. And startups that plan on being 10x better are often not even 1.5x better by the time they ship product. Successful startups usually have something that is *many* times better than the existing products, on some axis almost entirely orthogonal to the prior metrics. EricArticle: 146027
Hi folks, I would like to ask you for recomandation of the ethernet development kit with FPGA (much preferably Xilinx's one). Our requirements are the low power, as big FPGA as possible and at least 3 ethernet ports at 1Gbps. I am not sure it there is currently such kit being distributed, because I was not able to find it by google. Please, could you send information about kits, that could meet the requirements? (or are close to them?) Thank you very much JanArticle: 146028
On Mar 3, 4:19=A0pm, "Pete Fraser" <pfra...@covad.net> wrote: > "Jason Thibodeau" <jason.p.thibod...@gmail.com> wrote in message > > news:hmmfsq$gvr$1@news.eternal-september.org... > > > On 03/03/2010 11:20 AM, emeb wrote: > >> What size of designs are you working on? FWIW, I've had good luck > >> doing smaller stuff in WinXP running from the Bootcamp partition on a > >> MacBook using VMware. I've also gotten stuff built on an EEE901A with > >> WebPack 10.1 under EEEbuntu. > > > I think it is important to note the size of your designs. I actually us= e > > an HP mini 210HD for a lot of my designs. I run Fedora 12, and ISE 11.1= . > > Sure its not as speedy as can be, but it gets the job done. > > It varies. > My current design is very small (XC3S250E). > Mostly I design with XC5VSX50T, but I'm a consultant, so it's whatever th= e > client wants. > Typically the SX50T is a nice sweet spot for price / performance for vide= o > processing. > My current project is audio, hence the tiny part. > > Pete Some things to consider: http://www.xilinx.com/ise/ossupport/index.htm http://www.xilinx.com/ise/products/memory.htm Note the memory requirements for the larger devices.Article: 146029
On 3 Mrz., 14:02, "Pete Fraser" <pfra...@covad.net> wrote: > Any thoughts as to the relative merits of Modelsim PE and > Active-HDL (PE) for FPGA simulation? What about Systemverilog support? To my last evaluation Aldec still lags considerably behind Mentor and thus wasn't a option to me.Article: 146030
>What about Systemverilog support? > That might be true, does anyone know what the level of SystemVerilog support is in Active-HDL. Back in 2005 was using Modelsim-PE with SystemVerilog fine, support all features I used then, class, interface, etc. BOMK it has been expanded since then. You can get 30 day eval of both (pretty sure). Might be worth trying out unless there is a show stopper like SystemVerilog or multi-language support, Active-HDL supports Verilog/VHDL without an extra license (i think). --------------------------------------- Posted through http://www.FPGARelated.comArticle: 146031
On Mar 4, 5:31=A0am, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > >www.1pin-interface.com > > I've been emailed to say that some people are having problems with this. > > This is based on a Tiddlywiki, a quick google shows that the Skype plug-i= n > breaks some wiki-sites. It's in the Skype bug list to be fixed. > > If you do have any problems try disabling Skype to view it. > > Hardly an auspicious start. :-( > > Nial Looks interesting. A few administrative observations: * I get '404' pages for the target VHDL and Schematics on the Download pages. * the links in your prior messages are missing the 'http://' so they need to be cut/pasted into the browser rather than just clicking to follow. Conceptually attractive - I like the idea of an inexpensive USB interface for internal access to FPGAs. Something along the lines of Chipscope. I don't much care for the need to use Excel as the front- end. For those of us who don't use Excel or have access to VBA is there any possibility of a document that describes the protocol so that other languages & apps can be used to access it, or is that level of detail proprietary? EricArticle: 146032
On Mar 4, 8:07=A0am, "cfelton" <cfelton@n_o_s_p_a_m.ieee.org> wrote: > =A0BOMK it has been expanded since then. > BOMK?Article: 146033
> Looks interesting. A few administrative observations: > * I get '404' pages for the target VHDL and Schematics on the Download > pages. This should be mostly fixed, I don't seem to be able to link to a *.vhd file for some reason but have changed it to *.txt. Just change the file ending and it should work. I'll try it fix it properly later. > * the links in your prior messages are missing the 'http://' so they > need to be cut/pasted into the browser rather than just clicking to > follow. It looks like this is a Google problem, other newsreaders pick up the URLs properly, but thanks again. > Conceptually attractive - I like the idea of an inexpensive USB > interface for internal access to FPGAs. Something along the lines of > Chipscope. Yes, but at a slightly higher functional level. Chipscope/Signal Tap are for monitoring individual lines/groups (AFAIK). The 1 Pin Interface is more targeted towards reading or driving status or control registers. The idea is to have a convenient/compact interface that replaces an RS232 type debug interface and removes the need for external power supplies for level convertors etc. And only uses one pin. > I don't much care for the need to use Excel as the front- > end. I started using C++ builder but switched to Excel because it's almost universal. BTW, if you have access to Excel the VBA editor is integrated, just hit Alt-F11. It's obviously not universal enough! > For those of us who don't use Excel or have access to VBA is > there any possibility of a document that describes the protocol so > that other languages & apps can be used to access it, or is that level > of detail proprietary? Yes no problem, I want to to be as open as possible, as long as you don't expect support for strange languages. I'll probably publish the code for the 1 pin module if there's any demand. I'll add a page to the Web site lising the text of the Excel module tonight. This is probably the simplest way of explaining what's happening. Thanks for the feedback. NialArticle: 146034
>I've finally decided to buy a better simulator >(I've been making do with Modelsim XE so far). > >Any thoughts as to the relative merits of Modelsim PE and >Active-HDL (PE) for FPGA simulation? > >Thanks > >Pete > > I have been using both Modelsim PE and Active HDL since last six years. over the years , I have seen noticeable speed advantage of 2-3 times in Active HDL-PE compared to Modelsim-PE. I also use lot of scripts to simulate my designs and link files to AHDL without making local copies in AHDL project.Well there is definite cost advantage with active HDL-PE. -Nick --------------------------------------- Posted through http://www.FPGARelated.comArticle: 146035
On Feb 8, 12:46=A0am, Mike Hore <mike_hore...@OVE.invalid.aapt.net.au> wrote: > (see below) wrote: > > On 05/02/2010 18:19, in article > > badc12c3-cb2b-4ce9-9543-237d60fc2...@o8g2000vbm.googlegroups.com, "Eric > > Chomko" <pne.cho...@comcast.net> wrote: > > >> Has anyone created a copy machine of an old system using an FPGA? I > >> was wondering if it would be possible to take an entire SWTPC 6800 and > >> compile the schematics and have it run on an FPGA board.? Wouldn't > >> even have to be the latest Xylinx product, I suspect. > > > I think such a project would valuable, and perhaps even more valuable i= f it > > aimed to recreate a machine of the "heroic" era -- a 7094, an Atlas, or= a > > KDF9, say. Perhaps even a Stretch. > > A KDF9, maybe, but Stretch? =A0You'd have to be seriously masochistic, or > downright insane =A0:-) I keep hoping for an FPGA that would be suitable for replicating the internal logic of an IBM 360/195, as an example, so that if I did build a replica of a computer, I could have a reasonably efficient implementation which would give performance at least roughly in the ballpark of a Pentium - at least an early one. I'm working on refining the ISA for my own example computer design - based on the parsimonious use of opcode space made possible by the old SEL 32 trick used in Aligned Operand Mode, I think I can indeed abandon the multitudinous alternative instruction modes, and not only have just one - but have one with the property that a minimal number of logic gates are required to determine the number of 16-bit halfwords which constitute any given instruction.Article: 146036
On Mar 3, 7:06=A0pm, Greg Menke <guse...@comcast.net> wrote: > Peter Flass <Peter_Fl...@Yahoo.com> writes: > > Michael Wojcik wrote: > >> Peter Flass wrote: > >>> Hey! =A0C's finally caught up to PL/I. =A0Only took them 50 years, an= d then > >>> of course all the features are just tacked-on in true C fashion, inst= ead > >>> of thought-through. > > >> Well, that's rather insulting to the members of WG14, who spent a > >> decade designing those features. Fortunately, they published the > >> Rationale showing that, in fact, they were thought through.[1] And a > >> great deal of documentation describing the process is available in the > >> archives.[2] > > >> If you'd care to show why you think otherwise, perhaps there would be > >> some grounds for debate. > > > "The flexible array must be last"? > > > "sizeof applied to the structure ignores the array but counts any > > padding before it"? > > > C is a collection of ad-hoc ideas. =A0WG14 may have put a great deal of > > thought into how to extend it without breaking the existing mosh, but > > that's my point, it's still a mosh. > > iostream formatting operators, because we really need more operator > overloading and no enhancements are too bizarre in service of making > everything, (for particular values of everything), specialized? > > Oh but wait, you can compile, install and dig your way through Boost so > as to avoid the fun & games of vanilla iostream. > > Thank goodness printf and friends are still around. More generally when speaking about C++, than goodness C is still around. > > Which I suppose isn't an argument that the feature wasn't designed, but > is perhaps in support of the "ad-hoc" argument. =A0One more wacky idea > thrown on the pile for the amusement of the programmer. > > GregmArticle: 146037
Jan, You may want to consider the XUP V5 pcb (university program ML505, with a xc5vlx110t). It has one ethernet port, and one MGT to sma connectors. It also has a bank of uncommitted IO pins brought out to a header. You might be able to get a multiple port ethernet hardware interface on another small pcb, and connect the two through the uncommitted IO. Something to think about. Also look at the new Virtex 6 pcbs, ML605, etc. and check out their features, and the use of the new extension connector, and what sort of extension boards are available. http://www.xilinx.com/products/devkits/EK-V6-ML605-G.htm http://www.xilinx.com/products/devkits/HW-FMC-XM104-G.htm AustinArticle: 146038
On Mar 4, 5:04=A0am, Kastil Jan <ikas...@stud.fit.vutbr.cz> wrote: > Hi folks, > I would like to ask you for recomandation of the ethernet development kit > with FPGA (much preferably Xilinx's one). Our requirements are the low > power, as big FPGA as possible and at least 3 ethernet ports at 1Gbps. > > I am not sure it there is currently such kit being distributed, because I > was not able to find it by google. > > Please, could you send information about kits, that could meet the > requirements? (or are close to them?) > > Thank you very much > > Jan The Xilinx ML50x <http://www.xilinx.com/support/documentation/ ml506.htm> has one GigE, one SGMII, and 3 other banks that would be trivial to wire as SGMII. Found with a 30-second Google search. RKArticle: 146039
On Mar 4, 10:06=A0am, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > Looks interesting. A few administrative observations: > > * I get '404' pages for the target VHDL and Schematics on the Download > > pages. > > This should be mostly fixed, I don't seem to be able to link to a *.vhd > file for some reason but have changed it to *.txt. Just change the file > ending and it should work. Yep - I'm now able to get both of those items. > > Conceptually attractive - I like the idea of an inexpensive USB > > interface for internal access to FPGAs. Something along the lines of > > Chipscope. > > Yes, but at a slightly higher functional level. > > Chipscope/Signal Tap are for monitoring individual lines/groups (AFAIK). Yes, now that I've seen the way the target works it appears to be a 4k bank of 16-bit read/write registers. Chipscope gives a more fine- grained access than that, although one can build similar structures in the GUI. Any other debugging function (bit access, logic analyzers, etc) could be easily layered on top of the register structure so it's functionally complete. As I've mentioned elsewhere, one of my gripes with Chipscope is that all access to the Virtual I/O and Internal Logic Analyzers is mediated by their WinXX GUI app, and that can't be scripted or controlled by anything except user mouse clicks. They have a rudimentary TCL interface, but it doesn't know how to access the VIOs and ILAs - it just gives access to the JTAG TAP controller. Having algorithmic access to the FPGA guts would be a big help, and right now I have to do that via other means (extra logic on the board that's controlled by the PC, etc). > > there any possibility of a document that describes the protocol so > > that other languages & apps can be used to access it, or is that level > > of detail proprietary? > > Yes no problem, I want to to be as open as possible, as long as you > don't expect support for strange languages. I'll probably publish the > code for the 1 pin module if there's any demand. > > I'll add a page to the Web site lising the text of the Excel module > tonight. This is probably the simplest way of explaining what's happening= . Sounds good. Thanks for making this available. EricArticle: 146040
On Mar 2, 4:17=A0pm, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > I've just noticed and read the thread you started just before Christmas > about your Fifo problem. > > You said... > > > problem fixed! > > solution and explanation in the next Brain issue > > (I will post short post also after the issue release) > > Any sign of the new Brain? > > BTW, was the read indicated by a single clock width pulse that was always > de-asserted after each read, or could this have been active for a number > of 62.5mhz cycles? > > I'd have changed the design so the internal read flag was inverted at > each read, then the number of reads couldn't have been mistaken by the > higher speed clock domain. > > Looking forward to the solution.. > > Nial sign :)! just returned from embedded still needing some breathe time FIFO proble solution: this was SO STUPID, the reason was that the engineer who made the "read enable" signal from the PPC user logic for some mystical reason did move this read enable from the PPC clock domain to the MGT clock domain that was in sync with the master clock on the master board, so in the slave board all was fine, except fifo read enable was in the clock domain of the master (syncronised to the MGT recovered clock) this also explains why the problem was not visible in chipscope: chipscope did latch the signal in 1 F/F and no bad disaster happened, what I also witnessed, but in the FIFO itself the clock enable was controlling multiple F/F that occasionally did then go nuts what I also witnessed. so there was no clock issue, no FIFO issue, but.. well things happen. I was not the only person who did look at the code, but nobody did see any issue, well we all mostly looked at the problems with the FIFO and CLOCK signals... AnttiArticle: 146041
as Xilinx has dropped hard processor IP in the latest families it makes ACTEL the only FPGA vendor whos latest product family does have hard processor IP. Smart fusion includes Cortex-M3, and yes its available now, I did have the kits in my hand at embedded AnttiArticle: 146042
On Mar 5, 6:06=A0am, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > I don't much care for the need to use Excel as the front- > > end. > > I started using C++ builder but switched to Excel because it's > almost universal. BTW, if you have access to Excel the VBA editor > is integrated, just hit Alt-F11. > > It's obviously not universal enough! So, does it work with OpenOffice ? > Yes no problem, I want to to be as open as possible, as long as you > don't expect support for strange languages. I'll probably publish the > code for the 1 pin module if there's any demand. I could not see an example timing/protocol diagram ? The other uses that spring to mind are * Use with a Microcontroller, in which case a SW-pin version on the target would be needed. Might be as simple as a slow enough clock ? * Use with CPLDs, in this case, minimal-logic is the requirement. -jgArticle: 146043
Eric Chomko <pne.chomko@comcast.net> writes: >More generally when speaking about C++, than goodness C is still >around. One can actually write very maintainable and quite performant applications in C++ by restricting the subset of C++ the version 2.1 flavor (no STL, no Templates, no Exceptions, no run-time typing). Basically C with classes. One can still use printf, snprintf, setjmp/longjmp etc, while reaping the data hiding and inheritance/interface benefits of C++. I've worked on three different operating systems or hypervisors written in such a restricted dialect. And yes, I think the iostream stuff is a useless abominable hack. scottArticle: 146044
On Mar 5, 7:56=A0am, Antti <antti.luk...@googlemail.com> wrote: > as Xilinx has dropped hard processor IP in the latest families it > makes ACTEL the only FPGA vendor whos latest product family does have > hard processor IP. > > Smart fusion includes Cortex-M3, and yes its available now, I did have > the kits in my hand at embedded > > Antti Did they mention a price for the A2F060 ? The A2F200 hits that old 'all things to all users' conundrum : Price! (and package..) eg you can buy the 'right sized' uC for these sort of prices, and add the 'right sized' ProASIC from another selection list ? [STM32 Value Line $0.85 : 10K : 16Kbyte 48-pin LQFP48 $1.44 : 10K : 64Kbyte 64-pin LQFP64 ] Cypress has the PSoC3 in open samples, and supposedly the PSoC5 in more stealth samples ? -jgArticle: 146045
On Mar 2, 8:14=A0am, Bob Smith <bsm...@linuxtoys.org> wrote: > JuNNi wrote: > > Hi, I am a beginner at FPGA. I had a query that which platform is used = for > > professional digital designs. Is it linux or windows?? > > Linux of course. =A0 And, if I might add, using vi and make. > > OK, the "of course" applies only to me, but I didn't want > to switch to Windows to do FPGA development so I took the > time to figure out what ISE was doing under the covers and > found that all the real work is done by programs that can > be invoked at the command line. =A0Eventually I was able to > even build a makefile for my project. > > I wrote an article for Nuts & Volts magazine describing how > to use command line tools and makefiles for FPGA development. > The article is at > =A0 =A0http://www.demandperipherals.com/docs/CmdLineFPGA.pdf > > I had a little trouble getting the proprietary JTAG drivers > to work under Linux, so when I designed my board (Baseboard4) > I made it so you could download the FPGA code to a USB-serial > port using just a 'cat' command. > > It turns out that the command line approach works as well > under Windows as it does under Linux, if that is of any use > to you. > > thanks > Bob Smith Bob, XST supports having the 'run' command in a script file, so the echo- >pipe technique is not needed. $.02, RKArticle: 146046
On Mar 3, 3:42=A0pm, d_s_klein <d_s_kl...@yahoo.com> wrote: > On Mar 3, 5:02=A0am, "Pete Fraser" <pfra...@covad.net> wrote: > > > I've finally decided to buy a better simulator > > (I've been making do with Modelsim XE so far). > > > Any thoughts as to the relative merits of Modelsim PE and > > Active-HDL (PE) for FPGA simulation? > > > Thanks > > > Pete > > One complaint I have about Active-HDL is that it insists on making a > copy of the sources and hiding them in a not so easy to find > location. =A0It will then simulate these, and only these copies. =A0If yo= u > change a file while simulating, you have to remember to copy it out. > If you change something between simulations, you have to re-import it. > > This "feature" makes the simulator mostly useful only *after* all the > bugs are fixed. =A0(argh) As Rick says, when you choose "Add New File," there is a check-box for "Make Local Copy," which if de-selected seems to get grayed out so you can never select it again. However when this is deselect the project does not copy the file and instead references it from wherever it lives. I find Aldec's forced directory structure to be rather stupid, and it's really difficult to put it reasonably into a source-code control system. It wants to put all of the scripts and configuration files into its src directory, which of course breaks the cardinal rule "don't put synthesizable sources and configuration files in the same directory!" and it's got too many configuration files. ModelSim has one project file (the .mpf) which is plain text and easily edited by hand. I think it's whole notion of workspaces is pretty useless, too. It has a potential to be useful, in that you can put multiple designs in it. Consider, for instance, a design which has a top-level source and three lower-level sources. Of course you want some kind of test bench for each lower-level source, and it would seem that creating a "Design" for each in the workspace would work. But it doesn't. One reason is that each design has a library associated with it (and the default name is NOT work, but rather the design name). You cannot have a library that is shared among all of the designs in a workspace. Also, you can't call the work library for each design "work" -- they have to have different names. This all matters if you are lazy like me and you use direct instantiation of lower-level entities: u_lower : entity work.lower port map (foo =3D> foo, bar =3D> bar); I suppose the "right" thing to do in that case is to create a library for each entity, analyze each into this library and instantiate from it. This all assumes that your synthesis tool can support this. Finally, I really like ModelSim's concept of "simulation configurations." They're very easy -- you create a configuration, tell it the top-level entity, set all of the generics and various other things, and it's done. Click on the simulation configuration and off you go. Sure, these things are nothing more than wrappers around the vsim command but they're very handy. Active-HDL doesn't have this feature, so the workaround is to create tcl scripts which call asim with the proper command line. So, yeah, Active-HDL is fine but if you are used to ModelSim's features it can be confusing. I've spoken to Aldec's support folks about the really fscking stupid forced directory structure, the overabundance of configuration files and the lack of simulation configurations. I don't know whether they will, or even can, change some of this stuff without breaking existing projects, but as a paying customer I guess I'm allowed to make suggestions. -aArticle: 146047
On Mar 4, 5:04=A0am, Kastil Jan <ikas...@stud.fit.vutbr.cz> wrote:
> Hi folks,
> I would like to ask you for recomandation of the ethernet development kit
> with FPGA (much preferably Xilinx's one). Our requirements are the low
> power, as big FPGA as possible and at least 3 ethernet ports at 1Gbps.
>
> I am not sure it there is currently such kit being distributed, because I
> was not able to find it by google.
>
> Please, could you send information about kits, that could meet the
> requirements? (or are close to them?)
>
> Thank you very much
>
> Jan
The Digilent NetFPGA may suit your needs. It has 4 GigE Phys.
Note the host interface is only PCI and thus can't get all (or even 1)
gig ports in to the host but should be able to between ports if thats
all you need to do and it is an old FPGA (Virtex 2)
http://www.digilentinc.com/Products/Detail.cfm?NavPath=3D2,400,521&Prod=3DN=
ETFPGA
Note an alternatve to the phys are sfp slots (which some of the
Xilinx boards have) are an option with copper sfps (or fibre if thats
what you need). I'd be interested in anything else you find because
I'm after a board with at least 2 gig phys and a PCIX or PCIe host bus
that can get 2 gigs in to the host for packet capture (and haven't
found one yet).
Peter Van Epp
Article: 146048On Mar 4, 10:05=A0am, d_s_klein <d_s_kl...@yahoo.com> wrote: > On Mar 4, 8:07=A0am, "cfelton" <cfelton@n_o_s_p_a_m.ieee.org> wrote: > > > =A0BOMK it has been expanded since then. > > BOMK? "best of my knowledge." -aArticle: 146049
On Mar 4, 11:56=A0am, Antti <antti.luk...@googlemail.com> wrote: > as Xilinx has dropped hard processor IP in the latest families it > makes ACTEL the only FPGA vendor whos latest product family does have > hard processor IP. Putting a processor inside an FPGA has proven to us to be a bigger PITA than it's worth. Consider than instead of V4FX, you can use an S3AN and a standalone PPC and you'll pay a whole lot less. Plus the various Freescale PPCs have DDR memory and Ethernet and DMA controllers that don't suck, and you're not stuck with crappy tools. Embedding the processor in the FPGA is an interesting idea, but as long as Brand X seems to think that the only people who do are the types who want to run Linux on an FPGA, it's gonna suck for actual embedded use. -a
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