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> Is a development environment like Xilinx ISE or Altera Quartus > necessary? or are there standalone Verilog or VHDL compilers available > that can be used? I'm a bit unclear as to the process of going from > the source code to writing the design onto the chip. The development > boards generally have an FPGA chip that is removable, and one removes > it and inserts it into a 'programmer' to burn in the design? or is the > FPGA chip fixed onto the dev board and gets programmed in place? FPGA is fixed to board and programmed in place. FPGA can be programmed with either ISE or QUARTUS or another software provided from the boards manufacturer. There are programs you can simulate your HDL code. I don't know any program other than ISE or QUARTUS that generates the programming files for your FPGA.Article: 148701
> Is a development environment like Xilinx ISE or Altera Quartus > necessary? or are there standalone Verilog or VHDL compilers available > that can be used? I'm a bit unclear as to the process of going from > the source code to writing the design onto the chip. The development > boards generally have an FPGA chip that is removable, and one removes > it and inserts it into a 'programmer' to burn in the design? or is the > FPGA chip fixed onto the dev board and gets programmed in place? There are two main processes involved with non trivial FPGA design. 1) Write HDL (VHDL if you've any sense :-) ) and functionally simulate it. This is the only way you're going to get a design of any reasonable complexity to work. It involves writing a testbench 'wrapper' of HDL round the module or complete design you've written, this drives inputs, can check outputs etc. For a simple small module you might just check the outputs manually, for a complex design some form of self checking is a good idea. It's a good idea to thoroughly check all sub modules before plugging them together to form the top level design. You'll spend >>50% of your development time writing and testing modules/the design (in my experience). There is a subset of HDL that can be used when designing the FPGA itself, synthesiseable code. However when writing the testbench you can use all the constructs available so can read stimuli from text files, dump results etc, it's much more flexible. At a more system level Modelsim (one of the industry standards) has hooks to allow things to be driven from C etc. When you're convinced the design is functionally correct it's time for stage 2.... 2) Take the synthesiseable core that you've been testing and run it through the vendor tools to generate a programming file. This is a completely separate process to 1). When you're starting the GUI is a sensible way to drive things. You can use scripts eventually, but when you're searching for the syntax to apply an IO standard to a pin it's all there in the GUI. If I have a lot of similar pins I sometimes apply a constraint to 1 in the GUI then look at the generated constraint files and repeat this where necessary. Having said that Quartus has a pretty good Assignments editor where you can drag assignments from one pin to multiple pins (as you copy formulae in excel). Being a satisfied mostly Altera user and reading of recent ISE problems I'd recommend Altera tools to a beginner. I hope this helps, NialArticle: 148702
I forgot to say that to generate the programming files for your target device you will need the vendors tools. You can do your development in whatever text editing tool you want. I use textpad with syntax highlighting with tools defined to do a modelsim compile, grep a word in the current file and throw up a list of all signals, entities or ports. I also have a perl script written to generate testbench shells. Emacs has a VHDL (and probably verilog) mode which does all of this but I don't have enough knuckles to drive it. NialArticle: 148703
On Aug 18, 11:11=A0am, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > Emacs has a VHDL (and probably verilog) mode which does all of this > but I don't have enough knuckles to drive it. Thanks, this is good to know. I'm pretty comfortable in Emacs so I'll try that out. I also notice that ModelSim does a free cut down 'student' version, which sounds like it will make a very good starting point.Article: 148704
On Aug 18, 12:14=A0pm, "rupertlssm...@googlemail.com" <rupertlssm...@googlemail.com> wrote: > Thanks, this is good to know. I'm pretty comfortable in Emacs so I'll > try that out. I also notice that ModelSim does a free cut down > 'student' version, which sounds like it will make a very good starting > point. Looks like its for genuine higher education use only, and possibly only for windows. I'll try out the hardware vendors tools, and maybe come back to modelsim later.Article: 148705
> I also notice that ModelSim does a free cut down > 'student' version, which sounds like it will make a very good starting > point. Altera (and probably the rest) have a free OEM download version. This is speed crippled but is certainly good enough to get started with! Nial.Article: 148706
Hi folks! We are proud to announce version 0.3.9 of the vMAGIC libraries with a number of improvements. Most importantly, this will be the last alpha release as we want to keep the API stable from beta release 0.4.0 onwards. The current release particularly improves the handling of scopes, thus extending the code analysis features of vMAGIC. Also we have re-added the documentation to the binary release, and introduced a complete overhaul of the output framework. This last item is as yet transparent to the user, but it will be very important for the extension of the vMAGIC output options, i.e., the generation of XML code or Java code using vMAGIC (cf. http://vmagic.sf.net > Coming up next). Get it at SourceForge: http://vmagic.sf.net Looking forward to your feedback on http://sourceforge.net/projects/vmagic/forums/forum/880445 Ralf and christopherArticle: 148707
> Looks like its for genuine higher education use only, and possibly > only for windows. I'll try out the hardware vendors tools, and maybe > come back to modelsim later. You'll need it to test your designs! As above(/below) most of the vendors include an OEM version with their downloadable tools. Nial.Article: 148708
I am designing myself a FPGA board to interact with a PCI Bus and i have couple questions. First, Is it mandatory to have 2 power layers (GND + VCC)? Second, i just got a quote from a PCB manufactury and it should cost me $250 to make a board. Is it possible to find a cheaper board? The cheapest i found was Dragon Board from Knjn with a price of $300. Once i heared about a Insight Eletronics Board but i could not find it ... Any sugestions? Thats all for now!! Thank you! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148709
>Hi,
>
>I'm interested in learning more about FPGAs in a hands on way. Can
>anyone recommend an inexpensive set of tools to get started with? My
>wishlist is: I'd like to develop on Linux, I'd like to spend no more
>than a few hundred $ on a starter kit, I'd like to learn using the
>tools and up-to-date skills that are relevant to the more high end set
>ups available. Which is better to start with, Xilinx or Altera or
>something else? Is there a choice between Verilog and VHDL to be made,
>or can both be tried out just as easily?
>
>At the moment I am not too bothered about specific applications, just
>if I can get some hands on experience, whatever i/o ports are
>available on whatever board I use, I will think of some little project
>to try out using them.
>
>Thanks for your recommendations.
>
>Rupert
>
Since you've seen the expert's replies, I'll weigh in from a similar
place to you (i.e. a newbie :-)). I bought a Xylinx Spartan3 starter kit:
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,799&Prod=S3BOARD
(although I spent the $50 to upgrade to the bigger FPGA so it was $159
instead o $109 plus a download cable) and a copy of Dr Chu's book (another
$100 :-)) based on the reviews here:
http://www.fpgarelated.com/books/30.php
I have the VHDL one but there is one for verilog as well. Of especial note
is
that he includes a couple of simple test bench examples (and references to
more information on test benches) which is very helpful. The examples in
the book use the starter kit board for a variety of projects to teach hands
on and as a bonus there is a on the web (google will likely find it, the
url isn't to hand at the moment but I can dig it up if needed) a project
that turns the starter kit in to a 32 channel 100 meg logic analyser so I
expect it to have life after I've finished the book (one can never have too
many logic analysers in my view :-)). As far as I can see the book covers
all of the common pitfalls that get pointed out in comp.arch.fpga as well.
There are other boards available from Digilent too and you may want to
have a look at
http://www.fpga4fun.com boards and good tutorial information
http://www.fpga-faq.com/FPGA_Boards.shtml a listing of many many dev
boards
http://www.enterpoint.co.uk boards, and the only inexpensive Ethernet
PHYs
that I'm aware of (only 10/100 but not $500 US either!)
if you are interested in host busses such as PCI or PCI-E (which you may
not
be) that may influence what you buy. As well there are lots of open source
FPGA projects available on www.opencores.org. Hope this helps!
Peter Van Epp
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 148710What about books? Can anyone recommend a good book to get started with? I like books that are not too dry and start simple then build up the complexity of the subject in a hands on tutorial way. There are lots of books on Amazon, but not many of them have reviews, which makes it hard to choose. I guess the readership of these books is not so huge that lots of reviews get written.Article: 148711
On Aug 18, 8:07=A0am, "rupertlssm...@googlemail.com" <rupertlssm...@googlemail.com> wrote: > What about books? Can anyone recommend a good book to get started > with? I like books that are not too dry and start simple then build up > the complexity of the subject in a hands on tutorial way. There are > lots of books on Amazon, but not many of them have reviews, which > makes it hard to choose. I guess the readership of these books is not > so huge that lots of reviews get written. I wish I could. I have found that there are books on Verilog and VHDL that don't clearly delineate what can be synthesized and what can't. Having started from a hardware background in the pencil and paper design days and starting with programmable devices using PALASM, I already had an idea about hardware design methodology and just bought the books for language reference. However if you are going to get started without hardware and using a simulator as your primary design entry platform, you need to understand the difference between sythesizable and non-synthesizable code, or you will have a big shock the first time you decide to try your design out in hardware. As for development boards, if you don't need too much I/O to start with you might look at the XP2 Brevia kit from Lattice. You can download the free ispLever starter software from Lattice and a branded version of Aldec's simulation environment. I think more people are used to Modelsim for simulation, though. Regards, GaborArticle: 148712
On Aug 17, 6:12=A0pm, "Rice" <albertopv@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com> wrote: > My makefile is the following: > > #########################################################################= ####### > # Automatically-generated file. Do not edit! > #########################################################################= ####### > > -include ../makefile.init > > RM :=3D rm -rf > > # All of the sources participating in the build are defined here > -include sources.mk > -include subdir.mk > -include objects.mk > > ifneq ($(MAKECMDGOALS),clean) > ifneq ($(strip $(C_DEPS)),) > -include $(C_DEPS) > endif > ifneq ($(strip $(S_UPPER_DEPS)),) > -include $(S_UPPER_DEPS) > endif > endif > > -include ../makefile.defs > > # Add inputs and outputs from these tool invocations to the build variabl= es > > ELFSIZE +=3D \ > LEDs.elf.size \ > > ELFCHECK +=3D \ > LEDs.elf.elfcheck \ > > # All Target > all: LEDs.elf secondary-outputs > > # Tool invocations > LEDs.elf: $(OBJS) $(USER_OBJS) > =A0 =A0 =A0 =A0 @echo 'Building target: $@' > =A0 =A0 =A0 =A0 @echo 'Invoking: MicroBlaze gcc linker' > =A0 =A0 =A0 =A0 mb-gcc > -L"C:\Xilinx\12.1\ISE_DS\EDK\gnu\microblaze\nt\microblaze-xilinx-elf\incl= ude" > -Wl,-T -Wl,../src/lscript.ld > -L../../empty_application_bsp_0/microblaze_0/lib -mxl-pattern-compare > -mcpu=3Dv7.30.a -mno-xl-soft-mul -o"LEDs.elf" $(OBJS) $(USER_OBJS) $(LIBS= ) > =A0 =A0 =A0 =A0 @echo 'Finished building target: $@' > =A0 =A0 =A0 =A0 @echo ' ' > > LEDs.elf.size: LEDs.elf > =A0 =A0 =A0 =A0 @echo 'Invoking: MicroBlaze Print Size' > =A0 =A0 =A0 =A0 mb-size LEDs.elf =A0|tee "LEDs.elf.size" > =A0 =A0 =A0 =A0 @echo 'Finished building: $@' > =A0 =A0 =A0 =A0 @echo ' ' > > LEDs.elf.elfcheck: LEDs.elf > =A0 =A0 =A0 =A0 @echo 'Invoking: Xilinx ELF Check' > =A0 =A0 =A0 =A0 elfcheck LEDs.elf -hw ../../ledd/system.xml -pe microblaz= e_0 =A0|tee > "LEDs.elf.elfcheck" > =A0 =A0 =A0 =A0 @echo 'Finished building: $@' > =A0 =A0 =A0 =A0 @echo ' ' > > # Other Targets > clean: > =A0 =A0 =A0 =A0 -$(RM) $(OBJS)$(C_DEPS)$(EXECUTABLES)$(ELFSIZE)$(ELFCHECK= )$(S_UPPER_DEPS) > LEDs.elf > =A0 =A0 =A0 =A0 -@echo ' ' > > secondary-outputs: $(ELFSIZE) $(ELFCHECK) > > .PHONY: all clean dependents > .SECONDARY: > > -include ../makefile.targets > > There is not anything like -lstdio.h > > Is there any way of searching a word inside the whole project in order to > locate the error? =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com If the problem isn't in the make file, then it's possible the error message is just messed up and the real issue is that it can't find stdio.h Near the top of the code in your original post you have: #include "stdio.h" This implies the header file should be located in the project directory. Normally system libraries are included as: #include <stdio.h> which indicates the header file is in the system libraries directory. Are there any other projects you could look at to see if this might be the normal way to include stdio.h? Regards, GaborArticle: 148713
On Aug 18, 2:56=A0pm, Gabor <ga...@alacron.com> wrote: > However if you are going > to get started without hardware and using a simulator as your primary > design entry platform, you need to understand the difference between > sythesizable and non-synthesizable code, or you will have a big > shock the first time you decide to try your design out in hardware. Ok, thanks for pointing that out. I guess that's why its important to have a hands on approach. These books seems to get a lot of god reviews: http://www.amazon.com/FPGA-Prototyping-VHDL-Examples-Spartan-3/dp/047018531= 7/ref=3Dsr_1_1?ie=3DUTF8&s=3Dbooks&qid=3D1282133861&sr=3D8-1 http://www.amazon.com/FPGA-Prototyping-Verilog-Examples-Spartan-3/dp/047018= 5325/ref=3Dsr_1_8?ie=3DUTF8&s=3Dbooks&qid=3D1282133861&sr=3D8-8 > As for development boards, if you don't need too much I/O to > start with you might look at the XP2 Brevia kit from Lattice. Only $29!Article: 148714
<rupertlssmith@googlemail.com> wrote in message news:2557f9e5-e8ed-451a-b716-1e7954f56f39@x21g2000yqa.googlegroups.com... On Aug 18, 2:56 pm, Gabor <ga...@alacron.com> wrote: > However if you are going > to get started without hardware and using a simulator as your primary > design entry platform, you need to understand the difference between > sythesizable and non-synthesizable code, or you will have a big > shock the first time you decide to try your design out in hardware. Ok, thanks for pointing that out. I guess that's why its important to have a hands on approach. These books seems to get a lot of god reviews: http://www.amazon.com/FPGA-Prototyping-VHDL-Examples-Spartan-3/dp/0470185317/ref=sr_1_1?ie=UTF8&s=books&qid=1282133861&sr=8-1 http://www.amazon.com/FPGA-Prototyping-Verilog-Examples-Spartan-3/dp/0470185325/ref=sr_1_8?ie=UTF8&s=books&qid=1282133861&sr=8-8 > As for development boards, if you don't need too much I/O to > start with you might look at the XP2 Brevia kit from Lattice. Only $29! My experience with Lattice and their tools has been good. They now bundle the Aldec simulator which I must like since I have the paid for version (many $k). The Brevia kit looks very good value to start but the JTAG adaptor needs your PC to have a real parallel port. I've always used Windows for FPGA development so I can't comment on how well Lattice tools will work with Linux. Michael KellettArticle: 148715
I have a small electronic unit which needs some CE compliance testing. Cost is a major issue and was wondering if anyone here can offer advice on an affordable solution.Article: 148716
> >Few use port default values. I tend to avoid these for code that I intend >to synthesize, but it is a useful feature for testbench models. > That's exactly why I started using default values in the first place. Besides being useful for testbench models, I get the sense that most people don't use default values too much. Is it just a pain in the butt for most people? or could it lead to unintended results if one is not careful? I find default values some-what useful because I can leave a signal open, i.e.Article: 148717
>> >>Few use port default values. I tend to avoid these for code that I intend >>to synthesize, but it is a useful feature for testbench models. >> > >That's exactly why I started using default values in the first place. >Besides being useful for testbench models, I get the sense that most people >don't use default values too much. Is it just a pain in the butt for most >people? or could it lead to unintended results if one is not careful? > >I find default values some-what useful because I can leave a signal open, >i.e. > > mysignal(0) => someothersignal, mysignal(3 downto 1) => open, --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148718
On 8/18/2010 9:19 AM, hvo wrote:
>> Few use port default values. I tend to avoid these for code that I intend
>> to synthesize, but it is a useful feature for testbench models.
> That's exactly why I started using default values in the first place.
> Besides being useful for testbench models, I get the sense that most people
> don't use default values too much. Is it just a pain in the butt for most
> people? or could it lead to unintended results if one is not careful?
Default values for ports and signals
are irrelevant and possible harmful in synthesis code.
Default values are ignored for synthesis, but may mask
an initialization problem when such synthesis code is tested.
> I find default values some-what useful because I can leave a signal open,
I sometimes find default signal values convenient for testbench
stimulus signals.
-- Mike Treseler
Article: 148719Dinçay Akçören <dincay@gmail.com> writes: > terasIC's MAX boards have CPLD, not FPGA. Good point. In fact, there seems to be a shortage of Cyclone III boards in the market, at least cheap ones with some devices on board. Terasic's DE0 seems to be the only one? Then there is Arrow's Bemicro which is certainly cheap (at least in the US), but all it has are a few LEDs. Good thing is that there's an 80-pin edge connector on the board, but again very little to plug into it.Article: 148720
"Rice" <albertopv@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com> writes: > There is not anything like -lstdio.h Maybe it's in the included makefile.init then? Or somewhere in the project settings? > Is there any way of searching a word inside the whole project in order to > locate the error? Surely that's normal computer usage?Article: 148721
On Wed, 18 Aug 2010 17:11:21 +0100, Fredxx wrote: > I have a small electronic unit which needs some CE compliance testing. > > Cost is a major issue and was wondering if anyone here can offer advice > on an affordable solution. You should contact a certification lab in your area. CE and UL are mostly a lot of paperwork with a small amount of actual testing. They are designed to be fee generators, and in CEs case trade barriers, do there isn't going to be a cheap way to do it. FCC is easier because it's based on physics not on the whims of bureaucrats, you can do FCC certification in a few hours because it's just a matter of measuring the emissions of the system, you are either within bounds or not.Article: 148722
On 08/18/2010 01:38 AM, rupertlssmith@googlemail.com wrote: > On Aug 17, 8:43 pm, Jonathan Bromley<s...@oxfordbromley.plus.com> > wrote: >> On Tue, 17 Aug 2010 10:07:45 -0700 (PDT), >> >> rupertlssm...@googlemail.com wrote: >>> I'm interested in learning more about FPGAs >> >> Wow. I think this thread reminds me why it's still >> kinda nice to hang out on comp.arch.fpga (and >> comp.lang.vhdl, .verilog). >> >> You get three seriously expert people, with distinctly >> different viewpoints and distinctly different positions, >> each giving a clearly expressed and nuanced take on >> a bunch of issues (X vs A, Verilog vs VHDL) that >> could so easily degenerate into a schoolyard scrap. >> >> And the OP gets spot-on advice too. >> >> Hard to beat. Thanks to all the contributors for >> their time and their generously shared expertise. >> -- >> Jonathan Bromley > > Yes, some excellent advice, thanks very much. > > I hadn't really appreciated that I can download Xilinx ISE or Altera > Quartus web editions for free and that both run on Linux. Also that I > can run simulations of designs without having a chip to program them > onto, so it looks like I can at least have a play around with the > basics at no cost at all. > > Is a development environment like Xilinx ISE or Altera Quartus > necessary? or are there standalone Verilog or VHDL compilers available > that can be used? As mentioned, the ISE environment is a shell for the command-line tools. One thing I like about it is that with a bit of digging you can find the command line used to invoke the tool, which means that you can use ISE to help you write your makefile when you get serious about production code. The term 'compiler' means something different in HDL than in a programming language. With HDL you either simulate or synthesize. They are different and essential steps. Simulation is just that -- there's a tool that runs the HDL or that compiles it to a runnable program, that simulates the design on your workstation. Simulation isn't just a cool geeky thing -- it's an essential step to making sure your design is working. There are open-source simulators out there, but the FPGA companies are pretty tight with their synthesis algorithms (and even the mapping between the bit files and the FPGA functions), so you won't find any open-source synthesizers. Synthesis takes the HDL that it can understand and do something with -- and that isn't all of the HDL -- and makes a design that will do what the HDL specifies. It usually needs an additional "constraint file" that lets it know about timing constraints, what signal goes to what pin, etc. In software build terms the constraint file is sorta kinda maybe a linker script, only different. Synthesis takes a _long_ time, and the result is a file that goes onto the FPGA where many informative signals are obscured -- hence the usefulness of the simulation step. > I'm a bit unclear as to the process of going from > the source code to writing the design onto the chip. The development > boards generally have an FPGA chip that is removable, and one removes > it and inserts it into a 'programmer' to burn in the design? or is the > FPGA chip fixed onto the dev board and gets programmed in place? The FPGA is soldered down to the board. During early development you fire things up and write bit files directly to the chip (at least in the Xilinx workflow) with a JTAG programmer. FPGA chips (at least those that don't have on-board PROM) are capable of loading configurations from EEPROM, and most development boards will have a suitable EEPROM that you can load your bit file onto so the board will come up by itself. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 148723
On Tue, 17 Aug 2010 17:12:08 -0500, "Rice" <albertopv@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com> wrote: >My makefile is the following: > ># Tool invocations >LEDs.elf: $(OBJS) $(USER_OBJS) > @echo 'Building target: $@' > @echo 'Invoking: MicroBlaze gcc linker' > mb-gcc >-L"C:\Xilinx\12.1\ISE_DS\EDK\gnu\microblaze\nt\microblaze-xilinx-elf\include" >-Wl,-T -Wl,../src/lscript.ld >There is not anything like -lstdio.h Look for an error in that "script.ld" which sounds like a linker script. Any mention of "stdio" there is suspicious Possibly rename/remove it and use the "generate linker script" tool to make a new one. - BrianArticle: 148724
On Aug 18, 12:32=A0pm, "hvo" <hai.vo@n_o_s_p_a_m.n_o_s_p_a_m.synrad.com> wrote: > >I find default values some-what useful because I can leave a signal open= , > >i.e. > > mysignal(0) =3D> someothersignal, > mysignal(3 downto 1) =3D> open, > Actually that example is illegal. You can't have a vector that is partially assigned and partially opened. I opened a feature suggestion to the VHDL standards group several years back to have that changed. KJ
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