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Hi guys, I'm (still) trying to chase down an issue with the SDRAM on an Enterpoint Drigmorn2 development board. Basically, the SDRAM is acting like the mythical Write Only Memory -- I can write stuff to it, but as soon as the address goes over 0x800, the readback is stuffed. Does anyone have either a known-working SDRAM IP core (ideally with a WISHBONE interface), or an SDRAM tester, which I can borrow to do some testing? I just need it to work with a 2M*32bit*4bank (the ISSI part on the Drigmorn2) and a 1M*16bit*4bank (the Powerchip part on the Altera/ Terasic DE1) chip. If it works with one, the other or neither, I'm open to tweaking it to work (should be a simple enough case of modifying the addressing logic). At this point I've more or less ruled out SI issues (clock rate is only 25MHz, slew rate is set to SLOW, tracks are very short...), which just leaves: 1) XST/ISE isn't synthesizing my logic properly. Can't prove this without a different synthesizer -- if I put a zip file with the ISE project somewhere, could someone possibly synthesize it with a different tool for me and send the bit-file back? 2) Duff SDRAM chip or bad connections/soldering. It's a BGA, BGAs always make me suspicious... :-/ 3) My logic is doing something wrong which the ISSI chip doesn't like, but which doesn't cause problems with the Powerchip chip on the Altera DE1 board. The board is currently hooked up to a logic analyser (HP 16500B+16555D Deep Memory analyser blade), but I'm not seeing anything out-and-out wrong. Refresh timing is right on (15.625us between each AUTO REFRESH), read/write latency seems to be set right, init looks good and matches the datasheet... Thanks, -- Phil. usenet10@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "10" with the last two digits of the current yearArticle: 148351
On Jul 13, 8:28=A0am, Philip Pemberton <usene...@philpem.me.uk> wrote: > Hi guys, > > I'm (still) trying to chase down an issue with the SDRAM on an Enterpoint > Drigmorn2 development board. Basically, the SDRAM is acting like the > mythical Write Only Memory -- I can write stuff to it, but as soon as the > address goes over 0x800, the readback is stuffed. > > Does anyone have either a known-working SDRAM IP core (ideally with a > WISHBONE interface), or an SDRAM tester, which I can borrow to do some > testing? I just need it to work with a 2M*32bit*4bank (the ISSI part on > the Drigmorn2) and a 1M*16bit*4bank (the Powerchip part on the Altera/ > Terasic DE1) chip. If it works with one, the other or neither, I'm open > to tweaking it to work (should be a simple enough case of modifying the > addressing logic). > > At this point I've more or less ruled out SI issues (clock rate is only > 25MHz, slew rate is set to SLOW, tracks are very short...), which just > leaves: > =A0 1) XST/ISE isn't synthesizing my logic properly. Can't prove this > without a different synthesizer -- if I put a zip file with the ISE > project somewhere, could someone possibly synthesize it with a different > tool for me and send the bit-file back? > > =A0 2) Duff SDRAM chip or bad connections/soldering. It's a BGA, BGAs > always make me suspicious... :-/ > > =A0 3) My logic is doing something wrong which the ISSI chip doesn't like= , > but which doesn't cause problems with the Powerchip chip on the Altera > DE1 board. > > The board is currently hooked up to a logic analyser (HP 16500B+16555D > Deep Memory analyser blade), but I'm not seeing anything out-and-out > wrong. Refresh timing is right on (15.625us between each AUTO REFRESH), > read/write latency seems to be set right, init looks good and matches the > datasheet... > > Thanks, > -- > Phil. > usene...@philpem.me.ukhttp://www.philpem.me.uk/ > If mail bounces, replace "10" with the last two digits of the current yea= r Just a guess, but if you're address is mapped such that going over 0x800 activates column address 10, then maybe you're not handling the auto- precharge properly? SDRAM chips with more than 1K columns skip column address 10 and go to column address line 11 because the A10 pin doubles as the auto-precharge select during CAS cycles. I remember early Xilinx MIG versions wouldn't even allow the use of row address 10 because they didn't handle this correctly and just tied A10 low instead of fixing it. I have to admit I've only worked with Micron parts, but it's hard to imagine ISSI parts behaving much differently given they all presumably meet the same JEDEC specifications. Are these single-data rate parts? Can you cross it to a Micron part number and get the Verilog model from their website? The Micron models are pretty good at showing you what is going on. Regards, GaborArticle: 148352
On Tue, 13 Jul 2010 06:05:49 -0700, Gabor wrote:
> Just a guess, but if you're address is mapped such that going over 0x800
> activates column address 10, then maybe you're not handling the auto-
> precharge properly?
That might be a possibility... though an unlikely one. I'll look into it.
The address generator is a little messy (out of necessity; it handles RAMs
with between 8 and 16 column address bits, programmable at runtime
believe it or not).
The chip I'm using has 512 columns (9bit column address), 4096 rows
(12bit row address) and four banks, so a column address should never
overflow into bit 10.
Hard coding the address decoder logic to this:
// columns: 9 bits
assign col_adr = linear_adr[8:0];
// rows: 12 bits, with A10 unused
assign row_adr = { linear_adr[20:19], 1'b0, linear_adr[18:9]};
assign bank = linear_adr[22:21];
gets me:
ADR0 Read Failure after writing to linear address 0x207
Expected 0x9BAB55AA, got 0xFF75EF7F.
Write to 0x207 went OK, but the value at 0x000 was found to have changed
---
ADR+N Readback Failure at linear address 0x240
Expected 0x6454AA55, got 0x00000000.
Wrote to 0x240 OK, but value read back was different.
It doesn't look like a CA / RA issue to me... Removing the "1'b0" from
the row_adr concatenation gets me the same result.
If I change it to this:
// rows: 12 bits, with A10 unused
assign row_adr = { linear_adr[11:10], 1'b0, linear_adr[9:0]};
// columns: 9 bits
assign col_adr = linear_adr[20:12];
assign bank = linear_adr[22:21];
I get an "ADR+N" error ("I put a book in the box, looked again and it
contained a fish!") at 0x100 instead:
ADR+N Readback Failure at linear address 0x100
Expected 0x6454AA55, got 0x00000000.
Wrote to 0x100 OK, but value read back was different.
> I have to admit I've only worked with Micron parts, but it's hard to
> imagine ISSI parts behaving much differently given they all presumably
> meet the same JEDEC specifications.
"Presumably" being the operative word here. While Micron seem to make a
big deal about JEDEC standards compliance and testing, ISSI stay
remarkably quiet about the subject.
> Are these single-data rate parts?
Yes.
> Can you cross it to a Micron part number and get the Verilog model from
> their website? The Micron models are pretty good at showing you what is
> going on.
The equivalent Micron part appears to be the MT48LC8M32B2 (which is
obsolete; it seems Micron have canned all their 256Mb x32 SDRAM parts --
the largest current x32 part is 4Mbit although 256Mb and 128Mb parts are
available in x16). This is a 2Meg, 32bit, 4bank part with the same
4096x512x32 bank size and addressing scheme:
A0-A8 = Column Address, with A10 as precharge
A0-A11 = Row Address
I've already done that and run the Testbench over the driver core using
Icarus Verilog. It works fine... :-/
--
Phil.
usenet10@philpem.me.uk
http://www.philpem.me.uk/
If mail bounces, replace "10" with the last two digits of the current year
Article: 148353
On Jul 13, 8:30=A0am, Philip Pemberton <usene...@philpem.me.uk> wrote:
> On Tue, 13 Jul 2010 06:05:49 -0700, Gabor wrote:
> > Just a guess, but if you're address is mapped such that going over 0x80=
0
> > activates column address 10, then maybe you're not handling the auto-
> > precharge properly?
>
> That might be a possibility... though an unlikely one. I'll look into it.
> The address generator is a little messy (out of necessity; it handles RAM=
s
> with between 8 and 16 column address bits, programmable at runtime
> believe it or not).
>
> The chip I'm using has 512 columns (9bit column address), 4096 rows
> (12bit row address) and four banks, so a column address should never
> overflow into bit 10.
>
> Hard coding the address decoder logic to this:
> =A0 =A0 =A0 =A0 // columns: 9 bits
> =A0 =A0 =A0 =A0 assign col_adr =3D linear_adr[8:0];
> =A0 =A0 =A0 =A0 // rows: 12 bits, with A10 unused
> =A0 =A0 =A0 =A0 assign row_adr =3D { linear_adr[20:19], 1'b0, linear_adr[=
18:9]};
> =A0 =A0 =A0 =A0 assign bank =3D linear_adr[22:21];
>
> gets me:
> =A0 ADR0 Read Failure after writing to linear address 0x207
> =A0 Expected 0x9BAB55AA, got 0xFF75EF7F.
> =A0 Write to 0x207 went OK, but the value at 0x000 was found to have chan=
ged
> =A0 ---
> =A0 ADR+N Readback Failure at linear address 0x240
> =A0 Expected 0x6454AA55, got 0x00000000.
> =A0 Wrote to 0x240 OK, but value read back was different.
>
> It doesn't look like a CA / RA issue to me... Removing the "1'b0" from
> the row_adr concatenation gets me the same result.
>
> If I change it to this:
> =A0 =A0 =A0 =A0 // rows: 12 bits, with A10 unused
> =A0 =A0 =A0 =A0 assign row_adr =3D { linear_adr[11:10], 1'b0, linear_adr[=
9:0]};
> =A0 =A0 =A0 =A0 // columns: 9 bits
> =A0 =A0 =A0 =A0 assign col_adr =3D linear_adr[20:12];
> =A0 =A0 =A0 =A0 assign bank =3D linear_adr[22:21];
>
> I get an "ADR+N" error ("I put a book in the box, looked again and it
> contained a fish!") at 0x100 instead:
> =A0 ADR+N Readback Failure at linear address 0x100
> =A0 Expected 0x6454AA55, got 0x00000000.
> =A0 Wrote to 0x100 OK, but value read back was different.
>
> > I have to admit I've only worked with Micron parts, but it's hard to
> > imagine ISSI parts behaving much differently given they all presumably
> > meet the same JEDEC specifications.
>
> "Presumably" being the operative word here. While Micron seem to make a
> big deal about JEDEC standards compliance and testing, ISSI stay
> remarkably quiet about the subject.
>
> > Are these single-data rate parts?
>
> Yes.
>
> > Can you cross it to a Micron part number and get the Verilog model from
> > their website? =A0The Micron models are pretty good at showing you what=
is
> > going on.
>
> The equivalent Micron part appears to be the MT48LC8M32B2 (which is
> obsolete; it seems Micron have canned all their 256Mb x32 SDRAM parts --
> the largest current x32 part is 4Mbit although 256Mb and 128Mb parts are
> available in x16). This is a 2Meg, 32bit, 4bank part with the same
> 4096x512x32 bank size and addressing scheme:
> =A0 A0-A8 =A0=3D Column Address, with A10 as precharge
> =A0 A0-A11 =3D Row Address
>
> I've already done that and run the Testbench over the driver core using
> Icarus Verilog. It works fine... :-/
>
> --
> Phil.
> usene...@philpem.me.ukhttp://www.philpem.me.uk/
> If mail bounces, replace "10" with the last two digits of the current yea=
r
I believe I can supply the Micron chip. If you are interested in
crosses I will check it out and let you know. All parts are new in
original factory packaging. Please let me know if you have an interest
and how many you need.
Thank you ,
Jon E. Hansen
(949)864-7745
Article: 148354
I was under the impression that in Verilog nonblocking
assignments are evaluated in an arbitrary order. However, in
Quartus, I have noticed that if you use something like this:
always @(posedge clock) begin
a <= 1;
if (condition) a <= 0;
end
Then, if "condition" is true "a" will always be assigned the
value 0. Is this the way Verilog is described in the standard
or is it just an Altera convention?
Which bring us to my next question: Can I block multiple non-
blocking assignments together like so:
always @(posedge clock) begin
begin
a <= 1;
b <= 2;
end
begin
c <= a;
d <= b;
end
end
So that "c" will end up with value 1 and "d" will end up with
value 2? I know that if I had only "a" and "c" I could use
blocking assignments, but with two groups of variables it
wouldn't be possible. So does the above snippet work reliably?
Article: 148355Hello! I am using xcf16p EEPROM, and 2 xc3s4000 FPGAs connected in a daisy chain on a custom board. The problem is when i program my FPGAs through JTAG interface, FPGA 1 always gets programmed and verified and always shows output whereas FPGA 2 always gets programmed and verified and sometimes it shows the output and sometimes it doesnt. I have failed to understand the reason for this behavior :s Kindly help me .. thanks --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148356
Hello I've been trying to download these 2.9GB for 3 days with numerous retries (thanks to the download manager, the 'resume' resulted in a restart from 0) and when I finally managed to get the full file it was corrupted. Now I want to order a DVD and when I click on the appropriate link on the web site I get redirected to the home page. Who at Xilinx wants to prevent people from using their products ? NicoArticle: 148357
On Thu, 15 Jul 2010 01:08:51 -0700 (PDT), Nicolas Matringe <nic_o_mat@msn.com> wrote: >Hello >I've been trying to download these 2.9GB for 3 days with numerous >retries (thanks to the download manager, the 'resume' resulted in a >restart from 0) and when I finally managed to get the full file it was >corrupted. >Now I want to order a DVD and when I click on the appropriate link on >the web site I get redirected to the home page. > >Who at Xilinx wants to prevent people from using their products ? Maybe the same people that >1 year leadtimes are acceptable.Article: 148358
hi all, I want to implement a DDR2 SDRAM controller, as Xilinx provides MIG software tool to create IP core for the memory interface, however I have some questions about the port configuration. I want to store up to 9 frames(3000H x 2748V) of image data into 1GB DDR2 SDRAM(MT47H64M16), the frame size is resolution x bits/pixel = 10 megapixels(3664H x 2748V) x 12bits/pixel = 15MB. In the prototyping, the address bits = 14, data bits=16, bank address=3bits, I need asynchronous write and read from SDRAM: 1- How to choose Port Configuration among the 5 configurations? For example:2 32bits Bidir + 4 32bits Unidir, 4 32bits Bidir, 2 64bits Bidir, etc. 2- How to choos the fruequency, in the datasheet, the max frequency could be 333MHz, actually the master clock of FPGA is set to 25MHz, what frequency for the SDRAM should be fine? 3- Since each pixel has 12bits, the data bus is 16bits, How should the storage perform, the extra 4 bits will be a waste, is it? 4- how are the frames stored? line by line, frame by frame, how to seperate each line or each frame? Thanks for your help! GladysArticle: 148359
I cant understand what was wrong with the old way of doing things i.e. just use your own download manager to get a zip file. Since they introduced the new method I have never managed to get it to work. Every time I pause the download it throws up an error when I try to resume it. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148360
On Jul 15, 2:20=A0am, Giorgos Tzampanakis <g...@hw.ac.uk> wrote: > So does the above snippet work reliably? Yes, but not in the way you described :-) > I was under the impression that in Verilog nonblocking > assignments are evaluated in an arbitrary order. You're not alone, but it's a delusion. > However, in > Quartus, I have noticed that if you use something like this: > > always @(posedge clock) begin > =A0 =A0 =A0 =A0 a <=3D 1; > =A0 =A0 =A0 =A0 if (condition) a <=3D 0; > end > > Then, if "condition" is true "a" will always be assigned the > value 0. Is this the way Verilog is described in the standard Yes. The standard says that if you have multiple nonblocking assignments (NBAs) to a variable, all maturing at the same time, then they will take effect in the same order in which they were executed procedurally. Given that your begin...end is a procedural block, it's clear that the second a<=3D0 will be executed later than the a<=3D1 assignment, and so it will also take effect (update its target variable) later. This is a fine, reasonable and useful coding style: make a default assignment, and then possibly change your mind about it later in the same procedural block. > Which bring us to my next question: Can I block multiple non- > blocking assignments together like so: > > always @(posedge clock) begin > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 a <=3D 1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 b <=3D 2; > =A0 =A0 =A0 =A0 end > > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 c <=3D a; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 d <=3D b; > =A0 =A0 =A0 =A0 end > end > > So that "c" will end up with value 1 and "d" will end up with > value 2? No. There will be a one-clock delay between the update on a and the update on c, and similarly for d and b. The inner begin...ends are completely irrelevant and superfluous; begin...end is simply bracketing to make a string of procedural statements act syntactically like a single procedural statement. Within the begin...end the statements are executed sequentially, and each begin...end block is executed in sequence as if it were a single more complex procedural statement. Here's what happens: 1.On the first clock edge, all four assignments are executed sequentially as you would expect. However, at the point when c<=3Da is executed, the earlier NBA a<=3D1 has not yet taken effect, so the assignment is effectively c<=3D1'bx (assuming a was initially 1'bx). 2.At the time of that same clock edge, various other code in your design will also execute as the result of @(posedge clock) controls. All these code blocks will execute as far as their next @() or other delay control. 3.When all code that was triggered by the clock has done executing and has stalled at some delay control, Verilog moves on to the NBA region of its scheduling model. The NBAs that were executed in steps 1 and 2 now mature, and drop their assigned values on to their target variables. 4.As a result of those variables being updated, it's quite likely that other always or continuous-assign code may be triggered for execution. But you can be sure that the clocked always blocks are not among them, because (I hope!) none of the NBAs updated the clock. 5.Then everything goes quiet until the next active clock edge, and we're back to step 1 again. The net result of all of this is that when you write a conventional synthesisable clocked always block, you have some guarantees about the behaviour of variables that were written by NBA... - when you READ the value of such a variable, either in a test condition or in an expression on the RHS of some assignment, you are reliably getting the variable's value as it was immediately BEFORE the clock edge; - when you ASSIGN to a variable using NBA, you are not yet updating the variable; rather, you are specifying the value that variable will take immediately AFTER the clock edge. And you can rewrite that specification as often as you please, by making successive NBAs to the same variable. > I know that if I had only "a" and "c" I could use > blocking assignments, but with two groups of variables it > wouldn't be possible I really don't know what you mean by that. Standard advice: take a look at Cliff Cummings's well-known paper on blocking and nonblocking assignments (Google for "Cummings coding styles that kill nonblocking"), which is a thorough and generally reliable overview of the situation. But please keep your critical faculties engaged; there are some unjustified "rules" in his paper that simply don't make sense. I and others have ranted at length about that here, many times. -- Jonathan BromleyArticle: 148361
HI all, I would like to write a decoder for 1-wire but I am stuck about the search algorithm. My question is: is it possible for a third party, without knowing the 1-Wire master and "slave" status, to correctly decode the whole execution of the command? I mean, the sequence of bits exhanged on the bus could give a clue of when is going to end or the exact informations are inside the master and you should wait the next reset because you cannot tell when it is going to end. It is not clear what happens if the master has already a list of devices, would it be possible to understand what is going on? BTW, which is the relation between 1-Wire commands and reset sequence? Is it true that every command must start with a reset or it could be used also to end a command ? Thanks in advance, Giuseppe Marullo giuseppe.marullo@iname.comArticle: 148362
Jonathan Bromley <spam@oxfordbromley.plus.com> wrote in
news:9250a4ef-19e7-41af-9e91-4970608bc6bb@j13g2000yqj.googlegro
ups.com:
> Yes. The standard says that if you have multiple
> nonblocking assignments (NBAs) to a variable, all maturing
> at the same time, then they will take effect in the same
> order in which they were executed procedurally.
>
> (snip)
>
> No. There will be a one-clock delay between the update on a
> and the update on c, and similarly for d and b. The
>
So, if we have assignments to the same variable we are
guaranteed that the assignments will take place in the order
they are written in the code. But with assignments to different
variables the situtation is still unclear. Compare the
following two snippets:
//Snippet 1
always @(posedge clock) begin
a <= 1;
if (condition) b <= a;
end
//Snippet 2
always @(posedge clock) begin
a <= 1;
b <= a;
end
if "condition" is true, do they behave exactly the same?
Article: 148363>On Thu, 15 Jul 2010 01:08:51 -0700 (PDT), Nicolas Matringe <nic_o_mat@msn.com> wrote: > >>Hello >>I've been trying to download these 2.9GB for 3 days with numerous >>retries (thanks to the download manager, the 'resume' resulted in a >>restart from 0) and when I finally managed to get the full file it was >>corrupted. >>Now I want to order a DVD and when I click on the appropriate link on >>the web site I get redirected to the home page. >> >>Who at Xilinx wants to prevent people from using their products ? > >Maybe the same people that >1 year leadtimes are acceptable. > It sounds like, for serious product developers, that using Xilinx's latest and greatest (devices and software) is not a great idea. The options are either stick with the older devices and software (11.3 been working ok for me). Or move to another FPGA manufacture that seems to be more consistent. Others have posted that Lattice seems to deliver better results but is a (perceived) generation behind. I say perceived because if you can't get the latest and greatest parts from X are they really ahead? Also, since X dropped NuHo it has been harder for me to get parts. NuHo distributes Lattice so we are strongly considering Lattice for our next design. There must be something to the quick / unstable latest and greatest releases. Because we all keep using their parts and some how putting up with the issues. Other than ISE we haven't had any huge issues with Xilinx (until they dropped NuHo). We don't upgrade our ISE to the latest, we try desperately not to get the latest ISE. Many have been interested in getting the latest X 7 series but then the frustration mounted because no parts are actually available. I think the car companies do the same thing? Generating hype, if it is good or bad hype? If you are using an older device (non-spartan6) you might want to try ISE10.x version (can it still be downloaded?). chris --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148364
On Jul 15, 1:08=A0am, Nicolas Matringe <nic_o_...@msn.com> wrote: > Hello > I've been trying to download these 2.9GB for 3 days with numerous > retries (thanks to the download manager, the 'resume' resulted in a > restart from 0) and when I finally managed to get the full file it was > corrupted. I had the same problem. I can't remember which browser wasn't working (IExplorer or FireFox)..... But when I switched to the other browser, the download worked fine with the download manager. RichArticle: 148365
On 7/15/2010 1:08 AM, Nicolas Matringe wrote: > Hello > I've been trying to download these 2.9GB for 3 days with numerous > retries (thanks to the download manager, the 'resume' resulted in a > restart from 0) and when I finally managed to get the full file it was > corrupted. > Now I want to order a DVD and when I click on the appropriate link on > the web site I get redirected to the home page. > > Who at Xilinx wants to prevent people from using their products ? > > Nico Yeah, but at least it's down from 5.5GB to 3GB. That's nearly 40% fewer places for your download to break. More to the point, that much smaller of a package at least implies that Xilinx is finally starting to do some much needed housecleaning in their software. Maybe by 13 it'll start working the way it's supposed to. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 148366
On Thu, 15 Jul 2010 13:59:48 +0000 (UTC), Giorgos Tzampanakis wrote: >So, if we have assignments to the same variable we are >guaranteed that the assignments will take place in the order >they are written in the code. But with assignments to different >variables the situtation is still unclear. No, it isn't. > Compare the following two snippets: > >//Snippet 1 >always @(posedge clock) begin > a <= 1; > if (condition) b <= a; >end > >//Snippet 2 >always @(posedge clock) begin > a <= 1; > b <= a; >end > >if "condition" is true, do they behave exactly the same? Yes. And in both cases, b<=a will read the OLD value of a (not the new value '1' whose assignment is scheduled for the upcoming NBA region of the scheduler). I can't really understand what would make you think they would be different. -- Jonathan BromleyArticle: 148367
On Thu, 15 Jul 2010 13:59:48 +0000 (UTC), Giorgos Tzampanakis wrote: Sorry about the second response, but I just noticed.... >So, if we have assignments to the same variable we are >guaranteed that the assignments will take place in the order >they are written in the code. No, that's not the point at all. They will take place ** in the order they were executed **. In other words, scheduled updates go on to a particular timeslot's NBA queue in FIFO order. In a single sequential block, then of course that has the same effect as "the order they are written" (except in loops, which can divert the flow of execution backwards in the code). But in the presence of concurrent assignment to the same variable from multiple blocks, or of intra-assignment delays, the difference is critical. Fortunately for the present discussion, neither of those two situations is suitable for synthesisable design code. -- Jonathan BromleyArticle: 148368
"maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> writes: > I cant understand what was wrong with the old way of doing things i.e. just > use your own download manager to get a zip file. Likewise. Well, I once read some comments from some Linux distributor which indicated almost no one uses download managers that can resume, instead most people download files multiple times until they finally succeed. So it makes some sense to try to push people into using a download manager, even if it's primitive and easily avoided. But then you have no chance to resume. And to think resuming downloads was everyday stuff in the 1990's already... > Since they introduced the new method I have never managed to get it > to work. Every time I pause the download it throws up an error when > I try to resume it. It has often worked for me, if I deliberately stop a download to resume later. But if something actually goes wrong, then resuming is unlikely to work... Altera at least does actually provide a direct link to the file if the download manager doesn't start. Doesn't help with Xilinx, though.Article: 148369
On Jul 15, 3:11=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hello! > I am using xcf16p EEPROM, and 2 xc3s4000 FPGAs connected in a daisy chain > on a custom board. The problem is when i program my FPGAs through JTAG > interface, FPGA 1 always gets programmed and verified and always shows > output whereas FPGA 2 always gets programmed and verified and sometimes i= t > shows the output and sometimes it doesnt. > > I have failed to understand the reason for this behavior :s > > Kindly help me .. thanks =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Do you always program them in sequence after power-up? If you randomly reprogram the devices well after the initial program, you could be getting trouble from an open-drain configuration I/O pin connected in common between the two chips. To program chips in a chain independently after power up in the Xilinx chain I used a couple years back, assertion of the program pin causes the done pin to go low which confuses the other chip as an input.Article: 148370
On Jul 15, 2:10=A0pm, Giuseppe Marullo <giuseppe.marullonos...@iname.com> wrote: > HI all, > I would like to write a decoder for 1-wire but I am stuck about the > search algorithm. > > My question is: is it possible for a third party, without knowing the > 1-Wire master and "slave" status, to correctly decode the whole > execution of the command? > > I mean, the sequence of bits exhanged on the bus could give a clue of > when is going to end or the exact informations are inside the master and > you should wait the next reset because you cannot tell when it is going > to end. > > It is not clear what happens if the master has already a list of > devices, would it be possible to understand what is going on? > > BTW, which is the relation between 1-Wire commands and reset sequence? > Is it true that every command must start with a reset or it could be > used also to end a command ? > > Thanks in advance, > > Giuseppe Marullo > > giuseppe.maru...@iname.com if reset go tristate for all but master. on(clock) step through following if not tristate emit address and command process recieved command gated by address if command invalid go to reset if command required tristate switch then switch sender off if command required tristate switch then switch reciever on loop to on(clock)Article: 148371
On 15 juil, 17:21, "cfelton" <cfelton@n_o_s_p_a_m.n_o_s_p_a_m.ieee.org> wrote: > >On Thu, 15 Jul 2010 01:08:51 -0700 (PDT), Nicolas Matringe > <nic_o_...@msn.com> wrote: > > >>Hello > >>I've been trying to download these 2.9GB for 3 days with numerous > >>retries (thanks to the download manager, the 'resume' resulted in a > >>restart from 0) and when I finally managed to get the full file it was > >>corrupted. > >>Now I want to order a DVD and when I click on the appropriate link on > >>the web site I get redirected to the home page. > > >>Who at Xilinx wants to prevent people from using their products ? > > >Maybe the same people that >1 year leadtimes are acceptable. > > It sounds like, for serious product developers, that using Xilinx's lates= t > and greatest (devices and software) is not a great idea. =A0The options a= re > either stick with the older devices and software (11.3 been working ok fo= r > me). =A0Or move to another FPGA manufacture that seems to be more consist= ent. [...] Well since the intent of all this was to do a quick FPGA benchmark it seems that Xilinx earned a VERY bad mark there. Altera wasn't very good either but I managed to install the software once I got it. Lattice's software comes through a normal file transfer, it is perfectly handled by FireFox (I stopped the download yesterday night and just resumed it. I only hope that the file won't be corrupted) Actel's software went fine Are Austin and Peter still reading this newsgroup ? Can you do something about it ? Please ? NicoArticle: 148372
Yes i always program it in a sequence i.e. FPGA 1 and then FPGA 2. another point i missed in the last post is that while programming FPGA 1, i give it the bit file with DRIVE DONE = YES, and when i program FPGA 2 , i give it the bit file with DRIVE DONE = YES. When i give FPGA 1 the bit file with DRIVE DONE = NO, it doesn't get programmed and FPGA 2 shows the same random behavior as mentioned above. and when i reprogram FPGA 1 after FPGA 2 , FPGA 1 gets programmed. Now, there's something fishy going around with the DONE signal i guess, but i'm not sure about it so i need pointers, help, anything that would give a lead. Thanks John =) --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148373
On Jul 16, 5:18=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: <snip> > > there's something fishy going around with the DONE signal i guess, but i'= m > not sure about it so i need pointers, help, anything that would give a > lead. > > Thanks John =3D) =A0 =A0 Read up on the DONE signal and its effect as an *input* to the FPGA. Note that it gets pulled down (regardless of drive=3Dyes or no, I believe) when the program bit is first asserted. One way to avoid this interaction is to break out the done separately from the two FPGAs so the open-drain pull-down of the DONE signal on one device doesn't affect the operation of the second; rather than one DONE connection to your programming device (assuming you're not programming via cable) you use two. Also look at whether DRIVE DONE =3D YES actively tries to assert the DONE pin even if the DONE from the other chip drives the same line with a typically-stronger pull down. Typical use is to have the DONE pulled up with a resistor and leave the rising edge for when all devices are programmed. The DRIVE DONE =3D YES would be for non-ganged DONE pins such as a single FPGA or separately pinned out DONE signals for the individual FPGAs so you don't have to add the pull-up to the single driver.Article: 148374
Hello everyone, I have a (maybe) simple problem I don't know exactly how to face up. I am given a design (which is made by a third person) that realizes simple bus peripherals upon a Altera CPLD. The design is quite simple: the address bus along with the data bus and the READ signals are brought as inputs of the CPLD (outputs are not considered). There is a combinatorial network which, starting from the adresses bus and the READ signal, derives some internal Chip Select signals used to drive the Clock of internal FFD registries. Now, I am asked to perform timing analysis to such design to verify if it is feasible (I have the timing specs of the bus). How can I perform such kind of *asynchronous* analysis? I am used to analyze pure synchronous circuits, but this situation is totally different! Theoretically, I should verify that the propagation delay of the combinatorial decoding network is compatible with the timings of the FFDs, but actually I do not know exactly the timings of the FFD (I suppose they are not a fixed value but depend on the decisions of the place and route) Paradoxically, I would be able to verify timings if the FFDs were realized as physical chips OFF the CPLD (verifying that the pin-to-pin combinatorial delay is feasible according to the external FFD chips timings). How should I model such constrains when everything is modeled inside a CPLD design? I am currently using Quartus II tools. Thank you in advance, Primiano Tucci -- Primiano Tucci http://www.primianotucci.com --------------------------------------- Posted through http://www.FPGARelated.com
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