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On 21 Juli, 16:26, Jason <cincy...@gmail.com> wrote: > On Jul 21, 3:27=A0am, Markus Lavin <markusl.se78pleasenos...@gmail.com> > wrote: > > > Hi all, > > > This is a post to announce the existence of the AjarDSP project, an > > attempt to design and implement an open source VLIW DSP with an open > > source tool chain (assembler, simulator/debugger and C compiler). > > > Check out the details at:http://code.google.com/p/ajardsp/ > > > regards > > Markus > > Looks like a pretty ambitious project; good luck. Thanks! > It looks to me that > your design was heavily influenced by TI's C55x family? That is possible, but not really intentional. I would say that given that certain design parameters are fixed (like 16-bit dual-mac, 64-bit VLIW bundles, etc) then once you start to consider instruction encoding you aren't left with that much freedom. At least not if one wants to go for the more obvious solutions. > It does appear > to have a number of enhancements above any of those devices though > (more registers, more parallelism). > > Jason MarkusArticle: 148426
John_H schrieb:
> On Jul 21, 3:23 pm, Thomas Heller <thel...@python.net> wrote:
>> I'm trying to create a LVPECL_25 differential output on a Spartan 3
>> (XC3S200 device in PQ208 package). I did this by selecting 'LVPECL_25'
>> in the I/O Standard column in PACE (assign package pins).
>>
>> However, in 'Implement Design' I get the following error:
>>
>> Process "Translate" completed successfully
>> Using target part "3s200pq208-5".
>> Mapping design into LUTs...
>> Running directed packing...
>> ERROR:Pack:946 - The I/O component "q" has an illegal IOSTANDARD value.
>> Components of type IOB do not support IOSTANDARD LVPECL_25. Please correct
>> the IOSTANDARD property value.
>>
>> What am I doing wrong? I'm still using ISE 9.1.03i.
>>
>> Thanks,
>> Thomas
>
> Type IOB? Do you mean Type IOBUF? If it's the latter, the
> differential version might be IOBUFDS.
>
> I took a look at Table 10-3: Spartan-3 Generation I/O Components on
> page 321 of UG331 (v1.6) Spartan-3 Generation
> FPGA User Guide - http://www.xilinx.com/support/documentation/user_guides/ug331.pdf
> - where some of the implementation details might be less murky.
Well, the problem was that I have to instantiate an OBUFDS explicitely;
then I could set the IOSTANDARD attribute:
OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "LVPECL_25")
port map (
O => o, -- Diff_p output (connect directly to top-level port)
OB => o_not, -- Diff_n output (connect directly to top-level port)
I => count(3) -- Buffer input
);
Thanks,
Thomas
Article: 148427On 19 juil, 17:08, Gabor <ga...@alacron.com> wrote: > The chip you mentioned, MT47H64M16, is 1 gigabit, not 1 gigabyte. You > need 8 of these chips for 1 gigabyte of memory. I don't think you'll > be able > to drive 8 chips with the Spartan 6 MIG controller. Check carefully > in the > customization screens for MIG to see what you can do. Yes you are right, it's 1Gigabit and there's only 1 memory chip in my implementation. Actually now I just need to store maximum 3 frames of images in the DDR2, so there will be enough memory space for 3664 x 2748 x 12 x 3 = 362472192. > So sticking to me original idea of a 16-bit wide interface, even if > you > wasted the upper 4 bits you could store and retrieve 600 million > pixels per second at 300 MHz. I would consider running the > interface at a more comfortable 200 MHz which still gives you > a lot of extra bandwidth if all you need is a pixel buffer. Do the store and retrieve perform at the same frequency? Shall I slow down the rate of read in the read FIFO of MCB? > What is the speed grade of the MT47H64M16? That would need to > be -3 for the 300 MHz interface. a -5 part would be good enough > for 200 MHz. the speed grade of MT47H64M16 is -3. I just need to write and read about 30 million pixel once, so is 200MHz good enough for the design? > If your pixels are 12 bits and you want to store them in 16-bit wide > memory, concatenate 4 of them to make 48 bits of pixel data > which fit into three 16-bit words. How to implement this? If I choose the 128bit R/W port configuration, Should I pack 12bits pixel at the host side for the 128bits write data FIFO? Also now since I just need to store 3 frames, so I can waste the upper 4 bits, However, I don't understand how does the internal 128bits signal at host side transfered to 16bits signal at the DDR2 side, is the 128bits a set of 8 16 bits? > I'm still not convinced you do have memory to waste, but the basic > idea is > to start a new image line on say a 4096-word boundary even though the > actual line width is only 3664. This makes line addressing simpler. > Do > something similar by starting a new frame buffer at a 4096-line > boundary > even though the frame is only 2748 lines. This will mean that > addressing > within a frame buffer is a simpler function of pixel and line > position. Can I store the 3 images in different bank, for example, frame 1 in bank 1and 2, frame 2 in bank 3 and 4, and so forth. Sorry about my stupid questions, thank you again for your anwsers.Article: 148428
Hi, I' m new to Plan Ahead 12.1 and I' ve some values of I/O Ports in red color. It concerns DDR3 pins and values in red are Drive Strength (12*) and Slew Type (SLOW*). What could be the signification? ThanksArticle: 148429
On 7/22/2010 00:12, Tim Wescott wrote: > Anyone got one? Anyone close to Oregon City, Oregon got one? I'm > willing to pay a fair price, particularly if it's within driving distance. I hear there's compatible ones from Digilent - no experience though. http://shop.trenz-electronic.de/catalog/product_info.php?products_id=591 - Philip -- I will always be puzzled by the human predilection for piloting vehicles at unsafe velocities. (Lieutenant Commander Data)Article: 148430
Dear everybody,
in the following piece of code ...
if sRxOld /= iRx then
if vHIGH >= T_500ns then
sBit <= 'U';
elsif vLOW >= T_500ns then
sBit <= 'U';
elsif vLH = '1' then
sBit <= '0';
else
sBit <= '1';
end if;
else
sBit <= 'X';
end if;
... I assign the sBit signal of type std_ulogic to 'U', '0', '1' and
'X'. Then, anywhere in the code, I have a sequential
statement like this: if sBit /= 'X' then ...
My question is: when the VHDL is synthesized how the 'X' state is
represented ? Is the FPGA able to
distinguish between the 'X' state and '0' or '1' state ?
Best Regards
/Alessandro
Article: 148431On Jul 22, 1:12=A0am, Tim Wescott <t...@seemywebsite.com> wrote: > According to Avnet, Xilinx is out of their USB JTAG cables for weeks. > > I need one (see post about Linux, Cables, woe, etc.). > > Anyone got one? =A0Anyone close to Oregon City, Oregon got one? =A0I'm > willing to pay a fair price, particularly if it's within driving distance= . > > -- > > Tim Wescott > Wescott Design Serviceshttp://www.wescottdesign.com > > Do you need to implement control loops in software? > "Applied Control Theory for Embedded Systems" was written for you. > See details athttp://www.wescottdesign.com/actfes/actfes.html You could also check eBay.Article: 148432
On 22 July, 10:14, "alessandro.strazz...@gmail.com" <alessandro.strazz...@gmail.com> wrote: > Dear everybody, > > in the following piece of code ... > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if sRxOld /=3D iRx then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if vHIGH >=3D T_500ns= then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sBit <=3D 'U'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif vLOW >=3D T_500= ns then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sBit <=3D 'U'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif vLH =3D '1' the= n > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sBit <=3D '0'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sBit =A0<=3D '1'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sBit <=3D 'X'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > > ... I assign the sBit signal of type std_ulogic to 'U', '0', '1' and > 'X'. Then, anywhere in the code, I have a sequential > statement like this: if sBit /=3D 'X' then ... > > My question is: when the VHDL is synthesized how the 'X' state is > represented ? Is the FPGA able to > distinguish between the 'X' state and '0' or '1' state ? > > Best Regards > > /Alessandro Any input can only see a "1" or a "0". Although if the input is near the voltage where it has to decide then it will take a random amount of time to make up its mind and noise could make it change its mind. I wonder why we don't get this sort of thing as often as we used to? ColinArticle: 148433
DDR memory uses SSTL I/O and doesnt allow you to specify the drive strength. It seems to me that the I/O is setup wrong. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148434
On 7/22/2010 6:20 AM, colin wrote:
> On 22 July, 10:14, "alessandro.strazz...@gmail.com"
> <alessandro.strazz...@gmail.com> wrote:
>> Dear everybody,
>>
>> in the following piece of code ...
>>
>> if sRxOld /= iRx then
>> if vHIGH>= T_500ns then
>> sBit<= 'U';
>> elsif vLOW>= T_500ns then
>> sBit<= 'U';
>> elsif vLH = '1' then
>> sBit<= '0';
>> else
>> sBit<= '1';
>> end if;
>> else
>> sBit<= 'X';
>> end if;
>>
>> ... I assign the sBit signal of type std_ulogic to 'U', '0', '1' and
>> 'X'. Then, anywhere in the code, I have a sequential
>> statement like this: if sBit /= 'X' then ...
>>
>> My question is: when the VHDL is synthesized how the 'X' state is
>> represented ? Is the FPGA able to
>> distinguish between the 'X' state and '0' or '1' state ?
>>
>> Best Regards
>>
>> /Alessandro
>
> Any input can only see a "1" or a "0". Although if the input is near
> the voltage where it has to decide then it will take a random amount
> of time to make up its mind and noise could make it change its mind.
>
> I wonder why we don't get this sort of thing as often as we used to?
>
> Colin
Although this brings up a (fairly tool dependent) question that I've
had. If I assign a don't care output '-' (or an X or a U for that
matter) what happens? For instance, I just used in a project:
-- Start by setting up the address
C_addr <= (others => '-');
case TO_INTEGER(FCTL_I.ADDR) is
when REG_FIRST_COEF to REG_LAST_COEF =>
C_addr(7) <= '0';
C_addr(6 downto 5) <= UNSIGNED(fcsel_channel);
C_addr(4) <= fcsel_rt;
C_addr(3 downto 0) <= FCTL_I.ADDR(3 downto 0);
when REG_FIRST_CAL to REG_LAST_CAL =>
C_addr(7) <= '1';
C_addr(6 downto 5) <= UNSIGNED(fcsel_channel);
C_addr(0) <= FCTL_I.ADDR(0);
when others =>
C_we <= (others => false);
end case;
Now, I know what would happen if I were sitting around drawing Karnaugh
maps for these terms; C_addr(4) would always be equal to fcsel_rt,
regardless of FCTL_I.ADDR. What I don't know is whether or not XST is
smart enough to handle that don't care correctly, or whether all don't
care values get mapped to '0'. What about Quartus? What about
Synplicity? What about more complicated cases such as the following
inferred RAM, in which the bottom 7 bits of addr can always be used to
address the RAM?
if (addr < 128) then
dout <= RAM(addr);
else
dout <= (others => '-');
end if;
--
Rob Gaddi, Highland Technology
Email address is currently out of order
Article: 148435On 07/21/2010 04:10 PM, Brian Drummond wrote: > On Wed, 21 Jul 2010 15:10:37 -0700, Tim Wescott<tim@seemywebsite.com> wrote: > >> Is there any way to do this? >> >> Is there any way to do this without standing on my head? >> > > It doesn't quite involve standing on your head (at least in OpenSuse 11, I > haven't tried it in Ubuntu) but it does involve finding a "usb-driver" library > that also supports the parallel port. (The Xilinx-supported "libusb" is a > different beast) I had to tilt it over 45 degrees or so, though. I don't mind building my own software -- at least I know who to blame when things go bad -- but life can be a pain when the build process goes * Download from some website * type "make" * see a flood of errors... Fortunately in this case it was "type make, fiddle a very little bit, see impact work". > I got it from > http://rmdir.de/~michael/xilinx/ > > It uses the "ppdev" driver to communicate the parport, and only works at 200kHz > (Par Cable 3 compatibility mode) but once I got ot going I haven't had any > trouble with it. > > Better than the official Xilinx approach using Jungo Windriver, which won't even > build on any post-2008 kernel, as far as I can tell... Thank you, thank you for that link. The software limits the speed of the cable to that of the Parallel Cable III, but I'm just doing a small corner of a large design* so I'm not going to be impeded much by cable speed. And I'm happy that Xilinx made their tools Linux compatible, too. I know I'm swimming upstream to use Linux, but I just like it better than Windows for all sorts of reasons. * My corner is a motion controller to spin a motor synchronously with some other processes going on in the system. I'm really a control systems guy who writes decent software, but in a pinch I can write ugly HDL code that gets the job done. Since my customer is indeed in a pinch, that's what I'm doing. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 148436
On 07/21/2010 03:12 PM, Tim Wescott wrote: > According to Avnet, Xilinx is out of their USB JTAG cables for weeks. > > I need one (see post about Linux, Cables, woe, etc.). > > Anyone got one? Anyone close to Oregon City, Oregon got one? I'm willing > to pay a fair price, particularly if it's within driving distance. Never mind -- I solved my problem the 'right' way, so until I get a computer with no parallel port I'm good. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 148437
On Thu, 22 Jul 2010 10:58:35 -0700, Tim Wescott <tim@seemywebsite.com> wrote: >On 07/21/2010 04:10 PM, Brian Drummond wrote: >> On Wed, 21 Jul 2010 15:10:37 -0700, Tim Wescott<tim@seemywebsite.com> wrote: >>> Is there any way to do this without standing on my head? >but life can be a pain when the build process goes > > * Download from some website > * type "make" > * see a flood of errors... I hear you... >Fortunately in this case it was "type make, fiddle a very little bit, >see impact work". Glad to hear it. In my case it was more like "download half a dozen, get distracted for six months**, build them all, see flood of errors, until I found the one that worked... ** happens to me a lot, nowadays... >* My corner is a motion controller to spin a motor synchronously with >some other processes going on in the system. Cool. I may have to quiz you later on synchronous motor controllers. Not for the day job though... - BrianArticle: 148438
On Thu, 22 Jul 2010 09:50:33 -0700, Rob Gaddi <rgaddi@technologyhighland.com> wrote: >Although this brings up a (fairly tool dependent) question that I've >had. If I assign a don't care output '-' (or an X or a U for that >matter) what happens? For instance, I just used in a project: > > -- Start by setting up the address > C_addr <= (others => '-'); > > case TO_INTEGER(FCTL_I.ADDR) is > when REG_FIRST_COEF to REG_LAST_COEF => > C_addr(7) <= '0'; > C_addr(6 downto 5) <= UNSIGNED(fcsel_channel); > C_addr(4) <= fcsel_rt; > C_addr(3 downto 0) <= FCTL_I.ADDR(3 downto 0); > > when REG_FIRST_CAL to REG_LAST_CAL => > C_addr(7) <= '1'; > C_addr(6 downto 5) <= UNSIGNED(fcsel_channel); > C_addr(0) <= FCTL_I.ADDR(0); > > when others => > C_we <= (others => false); > > end case; > >Now, I know what would happen if I were sitting around drawing Karnaugh >maps for these terms; C_addr(4) would always be equal to fcsel_rt, >regardless of FCTL_I.ADDR. What I don't know is whether or not XST is >smart enough to handle that don't care correctly, or whether all don't >care values get mapped to '0'. What about Quartus? What about >Synplicity? I wouldn't necessarily trust even different versions of XST to do the same thing. As long as there is no extra cost in LUTs to either approach, the synth tool can do either. But I probably wouldn't care. If I did, I would code to more accurately reflect what I wanted : in this case, that would probably involve a separate case statement (or IF, or simple assignment for bits 4,5,6) for each bit group in the signal. - BrianArticle: 148439
On Jul 22, 3:14=A0pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Thu, 22 Jul 2010 09:50:33 -0700, Rob Gaddi <rga...@technologyhighland.= com> > wrote: > > > > >Although this brings up a (fairly tool dependent) question that I've > >had. =A0If I assign a don't care output '-' (or an X or a U for that > >matter) what happens? =A0For instance, I just used in a project: > > > =A0 =A0 -- Start by setting up the address > > =A0 =A0 C_addr =A0<=3D (others =3D> '-'); > > > =A0 =A0 case TO_INTEGER(FCTL_I.ADDR) is > > =A0 =A0 =A0 =A0 when REG_FIRST_COEF to REG_LAST_COEF =3D> > > =A0 =A0 =A0 =A0 =A0 =A0 C_addr(7) =A0 =A0 =A0 =A0 =A0 <=3D '0'; > > =A0 =A0 =A0 =A0 =A0 =A0 C_addr(6 downto 5) =A0<=3D UNSIGNED(fcsel_chann= el); > > =A0 =A0 =A0 =A0 =A0 =A0 C_addr(4) =A0 =A0 =A0 =A0 =A0 <=3D fcsel_rt; > > =A0 =A0 =A0 =A0 =A0 =A0 C_addr(3 downto 0) =A0<=3D FCTL_I.ADDR(3 downto= 0); > > > =A0 =A0 =A0 =A0 when REG_FIRST_CAL to REG_LAST_CAL =3D> > > =A0 =A0 =A0 =A0 =A0 =A0 C_addr(7) =A0 =A0 =A0 =A0 =A0 <=3D '1'; > > =A0 =A0 =A0 =A0 =A0 =A0 C_addr(6 downto 5) =A0<=3D UNSIGNED(fcsel_chann= el); > > =A0 =A0 =A0 =A0 =A0 =A0 C_addr(0) =A0 =A0 =A0 =A0 =A0 <=3D FCTL_I.ADDR(= 0); > > > =A0 =A0 =A0 =A0 when others =3D> > > =A0 =A0 =A0 =A0 =A0 =A0 C_we <=3D (others =3D> false); > > > =A0 =A0 end case; > > >Now, I know what would happen if I were sitting around drawing Karnaugh > >maps for these terms; C_addr(4) would always be equal to fcsel_rt, > >regardless of FCTL_I.ADDR. =A0What I don't know is whether or not XST is > >smart enough to handle that don't care correctly, or whether all don't > >care values get mapped to '0'. =A0What about Quartus? =A0What about > >Synplicity? =A0 > > I wouldn't necessarily trust even different versions of XST to do the sam= e > thing. As long as there is no extra cost in LUTs to either approach, the = synth > tool can do either. But I probably wouldn't care. > > If I did, I would code to more accurately reflect what I wanted : in this= case, > that would probably involve a separate case statement (or IF, or simple > assignment for bits 4,5,6) for each bit group in the signal. > > - Brian Actually I have found that XST is pretty good at minimizing logic when left with don't cares. It's not just a matter of LUT's. In this case any dependence on FCTL_I.ADDR would add connections to the LUT and reducing routing is another possibly more important optimization. In fact in this case you should end up with no LUT at all unless this logic gets flattened together with other code.Article: 148440
On Jul 22, 12:50=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > > Although this brings up a (fairly tool dependent) question that I've > had. =A0If I assign a don't care output '-' (or an X or a U for that > matter) what happens? =A0 This brings up the question of why are you asking what happens if you assign something as don't care? Sounds like you care...or perhaps you're just curious...and the way to satisfy curiousity is to try it out. But don't expect or get miffed if you happen to get different results from different tools for something you explicitly said you don't care about. <snip> > Now, I know what would happen if I were sitting around drawing Karnaugh > maps for these terms; C_addr(4) would always be equal to fcsel_rt, > regardless of FCTL_I.ADDR. =A0What I don't know is whether or not XST is > smart enough to handle that don't care correctly, or whether all don't > care values get mapped to '0'. =A0What about Quartus? =A0What about > Synplicity? =A0 Review the synthesis report more closely. > What about more complicated cases such as the following > inferred RAM, in which the bottom 7 bits of addr can always be used to > address the RAM? > > =A0 =A0 =A0if (addr < 128) then > =A0 =A0 =A0 =A0 =A0dout <=3D RAM(addr); > =A0 =A0 =A0else > =A0 =A0 =A0 =A0 =A0dout <=3D (others =3D> '-'); > =A0 =A0 =A0end if; > Again, try it and find out. If you're disappointed with the results, then you know you need to be more explicit. In this case, more explicit is also simpler. dout <=3D ram(addr mod 128); Kevin JenningsArticle: 148441
On Jul 22, 5:14=A0am, "alessandro.strazz...@gmail.com" <alessandro.strazz...@gmail.com> wrote: > Dear everybody, > > in the following piece of code ... > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if sRxOld /=3D iRx then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if vHIGH >=3D T_500ns= then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sBit <=3D 'U'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif vLOW >=3D T_500= ns then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sBit <=3D 'U'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif vLH =3D '1' the= n > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sBit <=3D '0'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sBit =A0<=3D '1'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sBit <=3D 'X'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > > ... I assign the sBit signal of type std_ulogic to 'U', '0', '1' and > 'X'. Then, anywhere in the code, I have a sequential > statement like this: if sBit /=3D 'X' then ... > > My question is: when the VHDL is synthesized how the 'X' state is > represented ? 'X' is not represented, the code you have listed is not synthesizable (1). If you run it through a synthesis tool, peruse the warnings that get generated looking for what it has to say about lines of code where you assign something the value of 'X' and where you compare some signal to 'X'. > Is the FPGA able to > distinguish between the 'X' state and '0' or '1' state ? Perhaps you review digital logic first. Kevin Jennings (1) The definition of 'synthesizable code' here being that any testbench that exercises the original code, produces the same result when exercising the synthesis output code. Exceptions for startup are allowed, but that's it. Specifically, the definition of synthesizable that I'm using is NOT simply that the synthesis tool produced an output file with no errors.Article: 148442
KJ <kkjennings@sbcglobal.net> writes: > Specifically, the definition of synthesizable that I'm using is NOT > simply that the synthesis tool produced an output file with no > errors. I like that :) I'll save that quote (attributed of course) if you don't mind? Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 148443
Hi all, I'm new in DDR2, I've read the MIG document UG388 but I don't quite understand, I'm wondering if anyones could explain me about the performance of the MCB's internal write/read FIFO datapath? the DDR2 is 16bits wide, and I need one 64bits write port and one 64bits read port for my implementation, the data to be stored into DDR2 is 48bits wide, how to implement this?Article: 148444
On Jul 23, 4:51=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > KJ <kkjenni...@sbcglobal.net> writes: > > Specifically, the definition of synthesizable that I'm using is NOT > > simply that the synthesis tool produced an output file with no > > errors. > > I like that :) I'll save that quote (attributed of course) if you don't m= ind? > > Martin > > -- Don't mind at all KJArticle: 148445
Le Wed, 21 Jul 2010 15:12:57 -0700, Tim Wescott a écrit : > According to Avnet, Xilinx is out of their USB JTAG cables for weeks. Hey Tim, why don't you use this one : XUP USB-JTAG from digilent. It works fine with my debian box. > > I need one (see post about Linux, Cables, woe, etc.). > > Anyone got one? Anyone close to Oregon City, Oregon got one? I'm > willing to pay a fair price, particularly if it's within driving > distance.Article: 148446
Tim Wescott wrote: > Is there any way to do this? > Is there any way to do this without standing on my head? I wanted to give a tutorial on how to use ISE on Linux but hah so many problems with JTAG that I gave up. Instead I designed an FPGA board that doesn't need JTAG for code download; it needs 'cat'. I eventually did give the tutorial and it went well. My board is here: http://www.demandperipherals.com and a HOWTO on using ISE with Makefiles under Linux is here: http://www.demandperipherals.com/docs.html#howto The BaseBoard is far from the only one that uses USB/serial for download but be careful as some boards use a proprietary USB driver even though it is just a serial port. HTH Bob SmithArticle: 148447
On Jul 22, 9:50=A0am, Rob Gaddi <rga...@technologyhighland.com> wrote:
> What about more complicated cases such as the following
> inferred RAM, in which the bottom 7 bits of addr can always be used to
> address the RAM?
>
> =A0 =A0 =A0if (addr < 128) then
> =A0 =A0 =A0 =A0 =A0dout <=3D RAM(addr);
> =A0 =A0 =A0else
> =A0 =A0 =A0 =A0 =A0dout <=3D (others =3D> '-');
> =A0 =A0 =A0end if;
Some hand-optimization might be good here:
dout <=3D RAM(addr);
After all, in this (likely contrived!) case, you don't care about the
assignment if the address is 128 or higher, so then not doing the
comparison at all and just doing the assignment anyway gives the best
result.
A smart synthesis tool should do that optimization.
-a
Article: 148448On Jul 19, 4:23=A0pm, Andy <jonesa...@comcast.net> wrote: > I recommend using integer for arithmetic if your data paths are less > than 32 bits. Mod has been well supported for quite a while (it was > then if you used decent FPGA tools), and is very handy for making sure > you don't have overflows (which do not go silently in the night in > simulation with integers). For example: > > signal count: natural range 0 to max_count - 1; > ... > count <=3D (count + 1 ) mod max_count; -- assume max_count =3D 2**n > > will roll over automatically for both increment and decrement. With modern (and by this I mean XST 10.1.3 supports!) the modulo need not be a power-of-two. -aArticle: 148449
"another one bytes the dust"... According to Processor Watch - July 22, 2010 (sorry, I have no URL, it was sent to me by email) ================================================ Tears for Tier Logic By Tom R. Halfhill, Senior Editor, MPR (7/19/2010) FPGA startup Tier Logic looks doomed after failing to raise enough money to move its first chips into production. A last-ditch attempt to save the privately held company fell through last week, said Paul Hollingworth, vice president for marketing and sales. Tier Logic, founded in Silicon Valley in March 2002, has spent about $20 million from its first-round investors and needs another $20 million to $30 million to bring its chips to market and reach breakeven, he said. Matrix Partners, the sole remaining investor, extended a bridge loan to keep Tier Logic alive for eight months during the search for additional funding, but that money is nearly gone, and the quest was unsuccessful. Another first-round investor, Walden International, pulled out last year. Hollingworth said the situation is frustrating, because Tier Logic has operational samples of its first programmable-logic chips and has already taken orders from early customers. The company had planned to begin production by the end of this quarter. ================================================ Now, $20 to develop silicon over almost 8 years, that sounds quite reasonable. So what did go wrong ? And what will happen now ? I think that now, the worse that could happen is that X & A buy all the patent portfolio and reinfoce their dominance in the market... yg -- http://ygdes.com / http://yasep.org
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