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100MHz has nothing to do with it - 12.5MHz in the authors orignal question = kind of does, but then this circuit isn't generally applicable to clock cro= ssings at higher speeds. Consider if the right FF is followed by combinator= ial logic before another FF. If that path has relatively little slack, then= a metastable event on the first slow FF will cause a timing violation on t= he second slow FF. Then the even may be double counted or missed. You can m= ake a assumption reasonably that this you'll never have this little slack a= t 12.5 MHz, but for the general case it's a problem. Also, metastability events can and do happen reasonably often. ChrisArticle: 150901
On 20 Feb., 06:09, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > I find the concept of trying to distill a complex state and time > dependent into a simple mathematical equation versus the HDL that > describes the system of questionable benefit. The HDL is a representation of the circuit that is extremely unsuitable for pretty much anything except for presenting the circuit to humans. I guess this is the reason why any tool chain (including ISE) gets rid of the HDL as quicky as possible to replace it by - netlists - state graphs - decision diagrams (ROBDDs for example) - boolean equations - function tables Whatever might suit the task that needs to be performed. (placement, logic optimization, retiming, equivalence checking, etc.) When analysing algorithms or proving properties of a circuits notations like that of the OP or mine are very commonly used and useful. For example in bounded model checking one iteratively builds a circuit derived from the original circuit and needs to no when this process reaches a functional fixed point. e.g. you want to know when Fn(x)=Fn+1(x). Try reasoning about such an algorithm without a formalism. By the way: Are there any plans by xilinx of making model checking available to the FPGA world for a price less then 120k$ per seat and year for the products by OneSpin? Regards, KoljaArticle: 150902
Hi All, I'm interested to know if anyone has successfully synthesised code using the fixed point data types 'sfixed' and 'ufixed' from the package (ieee_proposed.fixed_pkg_c) without any modifications... the library declarations in the top of my VHDL source are: library ieee; use ieee.std_logic_1164.all; library ieee_proposed; use ieee_proposed.fixed_pkg.all; This seems okay for the ISE simulator (ISim) however when I try to synthesise my code using XST I get the error: ERROR:HDLParsers:3317 - "D:/Workspace/LocalisationCore/ goertzel_dsp_core.vhd" Line 3. Library ieee_proposed cannot be found. ERROR:HDLParsers:3013 - "D:/Workspace/LocalisationCore/ goertzel_dsp_core.vhd" Line 4. Library ieee_proposed is not declared. Have I not declared something correctly, do I need to tell XST where its own libraries are? I know there are several compatibility packages around which attempt to make some of the features in VHDL2008, 1993 compliant. (http:// www.vhdl.org/fphdl/). But it seems that the 'fixed_pkg_c.vhd ' library/ package file is already in my VHDL source tree under IEEE proposed... So I guess my question is, what state are libraries that ship with ISE Design Suite 12.4 in, with regards to VHDL2008 support, and what is the best solution if I want/need to use the fixed point types ufixed and sfixed in synthesisable VHDL...Article: 150903
Can't believe no one has mentioned diligents CMOD yet!! http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,798&Prod=CMOD cost is $17, supports VHDL and Verilog (use the free WebPack design tool from xilinx, also comes with free simulator Isim) and has a standard DIP header perfect for connecting to breadboards. Although I believe an external clock is required, nothing a simple ASIC like 555 timer (5c?) couldn't provide tho... Cheers Mike.Article: 150904
Hi, i am using spartan 3 xc3s4000 in my design and i am working at 125Mhz clock. My design works fine in simulations but when i brought it on board, i am having issues with timing i guess. Xilinx does not report any timing failures but still im facing data loss. DataIn is not equal to DataOut, there is a great loss. Can anyone help me in achieving better timing closures.. thanks --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150905
On 21 Feb., 06:45, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hi, > i am using spartan 3 xc3s4000 in my design and i am working at 125Mhz > clock. My design works fine in simulations but when i brought it on board= , > i am having issues with timing i guess. Xilinx does not report any timing > failures but still im facing data loss. DataIn is not equal to DataOut, > there is a great loss. Can anyone help me in achieving better timing > closures.. > > thanks > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Hi, If the timing report gives you a result above 125 MHz, this is no question of timing closure. Inside the FPGA everything should be fine. But how do you make sure that valid data is captured at the inputs? And, how long are the Input delays. If not designed with care, these can ecceed the 8 ns period of the clock signal. Similar things apply for the output. Have a nice synthesis EilertArticle: 150906
"silvio.baccari" <silvio.baccari@gmail.com> wrote in message news:404f9d57-bb4d-4f3d-a4b0-186971ba71ae@x3g2000yqj.googlegroups.com... > Hi guys, > I'm searching for a general mathematical definition of an FPGA. > I propose this y=F(x,u) where y is a vector of output , u is a vector > of input and x is a vector of internal state and F is a certain > function of x,u. Have you some idea to generalize more this > definition? I guess a general [boring] mathematical definition could be: for all IO pins in i: IOpin(i)=F(all_other_IOpins,all_internal_memory_states,config_data) But for this to be valid, a "value" of "undriven/nothing" must be part of the valid return union.Article: 150907
>Hi, >If the timing report gives you a result above 125 MHz, this is no >question of timing closure. >Inside the FPGA everything should be fine. >But how do you make sure that valid data is captured at the inputs? >And, how long are the Input delays. If not designed with care, these >can ecceed the 8 ns period of the clock signal. >Similar things apply for the output. > >Have a nice synthesis > Eilert > timing report shows 127Mhz. And it is basically a gigabit mac and it has 2 interfaces, So, whatever comes on interface A,i can see it on chipscope and when to leaves at interface_B, i can see that too which is the same as coming in. But i dont know why, but this data doesn't come out on wire. I can monitor it till the last point but after that i dont know what's happening. Kindly help me out. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150908
>Hi guys, >I'm searching for a general mathematical definition of an FPGA. >I propose this y=F(x,u) where y is a vector of output , u is a vector >of input and x is a vector of internal state and F is a certain >function of x,u. Have you some idea to generalize more this >definition? >Thank you, >Silvio > What an incredibly daft idea! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150909
I finally was able to rewrite half of the code in a better way. now the syn= thesis report earn more than 6MHz speed. i am confident that maybe I can re= ach my aim of 80Mhz. But now i am wondering about OFFSET IN OUT constraints= . I have a 40MHz clock input then a DCM creates a 80MHz clock for the logic. = the problem is that I have an interface which works at 40MHz speed and the = interface state machine works at 80Mhz. So.. how can I set the right offset in out constraints? I can set only the = constraints relative to the 40 MHz clock even if the logic works at 80. in the same way I have also a ram interface which ges to 80Mhz. ho w can I = set the constraints relative to this interface if i have only the reference= clock that is the 40MHz input? this is the 40MHz interface, supposing a offset in of 10 ns: TIMEGRP "PLX_communication" OFFSET =3D IN 10 ns VALID 12.5 ns BEFORE "XCLK_= 40MHZ" RISING; which one is correct? TIMEGRP "PLX_communication" OFFSET =3D IN 10 ns VALID 25 ns BEFORE "XCLK_40= MHZ" RISING; from my state machine point of view, data are valid for 12.5 ns but the bus= keeps the valid for 25 'cos it works at 40MHz speed and if everything is re=F6lated to the 40MHz clock, and the derived constra= ints are automatically declared by SW, ho w can I set the constraints for t= he RAM interface at 80MHz?Article: 150910
Are you using SERDES and if so have you simulated to ensure you have it setup correctly? Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150911
>Are you using SERDES and if so have you simulated to ensure you have it >setup correctly? > >Jon > >--------------------------------------- >Posted through http://www.FPGARelated.com > No Jon, i am not using SERDES in my design. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150912
>>Are you using SERDES and if so have you simulated to ensure you have it >>setup correctly? >> >>Jon >> >>--------------------------------------- >>Posted through http://www.FPGARelated.com >> >No Jon, i am not using SERDES in my design. > >--------------------------------------- >Posted through http://www.FPGARelated.com > ok on further monitoring of signals i came across this weird thing, my state machines don't start from idle state when reset. few state machines reset to idle, whereas others reset to some other state. Can anyone help me out with this, and also tell me why is this happening ? thanks --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150913
On Feb 17, 4:40=A0pm, Leon <leon...@btinternet.com> wrote: > On Feb 17, 5:12=A0am, boB wrote: > > > > > On Wed, 16 Feb 2011 10:08:17 -0800 (PST), jack > > > <postbox4j...@gmail.com> wrote: > > >On Feb 16, 9:49 pm, Jay <jpt03...@engr.uconn.edu> wrote: > > >> Bryan <bryan.fletc...@avnet.com> wrote: > > >> >> You could use the $39 USB JTAG cable from Digilent, I'm thinking = of > > >> >> getting one. It isn't supported by Impact, but Digilent supplies = their > > >> >> own Adept software for it. > > > >> > The Digilent Cables can, in fact, support iMPACT, ChipScope, and S= DK > > >> > Debugging using a 3rd-party cable plug-in that Digilent provides. > > >> > There are a few extra steps involved to get it set up, but it does > > >> > work. Since the $39 cable is USB Full-speed, you might want to > > >> > consider the $47.95 High-Speed version. > > > >> > Also, it looks like Digilent has a Xilinx-authorized replica of th= e > > >> > Platform Cable USB-II since Digilent participates in the Xilinx > > >> > University Program. The non-Academic price is $129. > > > >> > Bryan > > > I tried to order the Digilent cable and they told me that since I > > wasn't a student, they could not sell me one. =A0Period. That was about > > a year ago. > > > I'm in the US if that makes any difference. > > > boB > > > >> I've been using the XUP cable for a few months now, and I have no > > >> complaints. A bit pricy, but I wanted a cable that works with impact= under > > >> Linux. I got the academic price, though. > > > >Thanks all for your suggestions. Am considering ordering one for > > >Digilent. > > I'd forgotten that I actually had one that I ordered some time ago > from Trenz, Digilent's German distributor, and stashed away. > > Unfortunately, I can't get it to work with my Digilent Spartan 3 > board, using both the Adept 2 software or Impact. I emailed Digillent > about the problem a couple of days ago, and haven't had a reply, > despite the acknowledgement =A0claiming that they respond in 24 hours. I > don't recommend that you order one. > > Leon It's a long time since I last used the Impact software, and I'd forgotten that I needed to create a project. When I did that the Digilent cable worked OK with the Spartan 3 board. LeonArticle: 150914
The cheap Platform Cable USB I'd bought on Ebay arrived this morning: http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&item=150560914094&ssPageName=STRK:MEWNX:IT Delivery via DHL was very quick. It works OK, also. LeonArticle: 150915
How are you coming out of reset? Ideally you should be coming out of reset = synchronously. Is the reset to your SMs synchronous? If it is, then this ba= sically leaves a logical error. Hopefully you are relying on a true reset, = not just the default state of the state FFs. ChrisArticle: 150916
>How are you coming out of reset? Ideally you should be coming out of reset = >synchronously. Is the reset to your SMs synchronous? If it is, then this ba= >sically leaves a logical error. Hopefully you are relying on a true reset, = >not just the default state of the state FFs. > >Chris > i have asynchronous reset in my design. And well i have a reset pin but i have tied it low (PULLDOWN) in UCF, and that reset is going everywhere in the design. Can you suggest any solution ? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150917
On Monday, February 21, 2011 1:34:23 PM UTC-5, salimbaba wrote: > >How are you coming out of reset? Ideally you should be coming out of reset > = > >synchronously. Is the reset to your SMs synchronous? If it is, then this > >basically leaves a logical error. Hopefully you are relying on a true reset, > >not just the default state of the state FFs. > > > >Chris > > > > i have asynchronous reset in my design. And well i have a reset pin but i > have tied it low (PULLDOWN) in UCF, and that reset is going everywhere in > the design. > Can you suggest any solution ? > > --------------------------------------- > Posted through http://www.FPGARelated.com So you really are relying on the initial conditions after configuration which is in essence an asynchronous release of reset after power-on. Generally a state machine can start up reliably with an asynchronous release of reset, but ONLY if the state it starts up in has no transition that will immediately become active upon release of reset. The simplest way to work around this is to generate a local reset signal for each state machine or module that releases synchronously one or two cycles after the release of the asynchronous reset and use that signal as a synchronous reset term for your state machines. Xilinx usually recommends a 4-stage shift register to create a reset from the GSR release. The actual number of stages required to reset cleanly will depend on the clock frequency and the size of the device, where the larger devices can have more skew in releasing GSR. My designs typically have no external reset signal and use the 4-stage S/R approach to an internal reset. I have had very good results with this approach, because the four stages give the tools ample opportunity to replicate the final S/R stage(s) to help meet timing. -- GaborArticle: 150918
Hello group, These days i'm back at A3P hacking and i fight against the tools and the elements, and probably against something i don't even know, so i'm asking the wise and experimented among you... Basically, a simple FIFO block (like 8b * 512) works. well, i use it just as a fast-to-slow circuit interface and i don't expect FULL status by design. I can even take advantage of word size conversion, i tried 16->8 (dropping the MSB) with some success. But when i want to do smaller sizes, like 16->1, it... doesn't work. output remains low, no sign of serialised signal. i see nothing about that in the datasheet and handbook. so where to turn when "it doesn't work" ? (except this group) ok so let's imagine i can still work with 8b->8b. i use the "EMPTY" flag to indicate that there is something available on the output. well, i don't know why but i see nothing on this signal :-/ it is normally registered on the (slow) read clock but i see nothing normal. Let's be clear : i don't do any high-speed stuff or crazy frequency domain crossing. it's in the 100KHz to 25MHz range, and I can look at the outputs with my faithful analog T'475. no problem with catching a 40ns pulse. So if anyone has any information about Actel ProASIC3's FIFO, concerning the extreme size conversions (16in, 1out) or/and the Empty flag, please step up ! If one of them is solved, i'm saved :-) yg -- http://ygdes.com / http://yasep.orgArticle: 150919
On Feb 21, 12:34=A0pm, Gabor <ga...@alacron.com> wrote: > On Monday, February 21, 2011 1:34:23 PM UTC-5, salimbaba wrote: > > >How are you coming out of reset? Ideally you should be coming out of r= eset > > =3D > > >synchronously. Is the reset to your SMs synchronous? If it is, then th= is > > >basically leaves a logical error. Hopefully you are relying on a true = reset, > > >not just the default state of the state FFs. > > > >Chris > > > i have asynchronous reset in my design. And well i have a reset pin but= i > > have tied it low (PULLDOWN) in UCF, and that reset is going everywhere = in > > the design. > > Can you suggest any solution ? =A0 =A0 =A0 =A0 > > > --------------------------------------- =A0 =A0 =A0 =A0 =A0 =A0 > > Posted throughhttp://www.FPGARelated.com > > So you really are relying on the initial conditions after > configuration which is in essence an asynchronous release > of reset after power-on. > > Generally a state machine can start up reliably with > an asynchronous release of reset, but ONLY if the > state it starts up in has no transition that will > immediately become active upon release of reset. > The simplest way to work around this is to generate > a local reset signal for each state machine or > module that releases synchronously one or two cycles > after the release of the asynchronous reset and > use that signal as a synchronous reset term for > your state machines. =A0Xilinx usually recommends > a 4-stage shift register to create a reset from > the GSR release. =A0The actual number of stages > required to reset cleanly will depend on the > clock frequency and the size of the device, > where the larger devices can have more skew in > releasing GSR. =A0My designs typically have no > external reset signal and use the 4-stage S/R > approach to an internal reset. =A0I have had > very good results with this approach, because > the four stages give the tools ample opportunity > to replicate the final S/R stage(s) to help > meet timing. > > -- Gabor Wow, nicely said! Anyone starting out in FSM design should take heed. I'll add one more thing: do you have any unconstrained timing paths in your design? Bob Perlman Cambrian Design WorksArticle: 150920
whygee wrote: > I can even take advantage of word size conversion, i tried > 16->8 (dropping the MSB) with some success. > But when i want to do smaller sizes, like 16->1, it... doesn't work. > output remains low, no sign of serialised signal. > i see nothing about that in the datasheet and handbook. > so where to turn when "it doesn't work" ? > (except this group) ok so width conversion from 18 to 9 bits wide is ok, I see the Empty status signal change but not with conversion to 4 bits or less. It seems that width conversion works with 2x wider or 2x smaller sizes, but not 4x or 8x or 18x No mention about it on the handbooks :-( Had i known this, I would have saved a day of work :-( yg -- http://ygdes.com / http://yasep.orgArticle: 150921
>On Monday, February 21, 2011 1:34:23 PM UTC-5, salimbaba wrote: >> >How are you coming out of reset? Ideally you should be coming out of reset >> = >> >synchronously. Is the reset to your SMs synchronous? If it is, then this >> >basically leaves a logical error. Hopefully you are relying on a true reset, >> >not just the default state of the state FFs. >> > >> >Chris >> > >> >> i have asynchronous reset in my design. And well i have a reset pin but i >> have tied it low (PULLDOWN) in UCF, and that reset is going everywhere in >> the design. >> Can you suggest any solution ? >> >> --------------------------------------- >> Posted through http://www.FPGARelated.com > >So you really are relying on the initial conditions after >configuration which is in essence an asynchronous release >of reset after power-on. > >Generally a state machine can start up reliably with >an asynchronous release of reset, but ONLY if the >state it starts up in has no transition that will >immediately become active upon release of reset. >The simplest way to work around this is to generate >a local reset signal for each state machine or >module that releases synchronously one or two cycles >after the release of the asynchronous reset and >use that signal as a synchronous reset term for >your state machines. Xilinx usually recommends >a 4-stage shift register to create a reset from >the GSR release. The actual number of stages >required to reset cleanly will depend on the >clock frequency and the size of the device, >where the larger devices can have more skew in >releasing GSR. My designs typically have no >external reset signal and use the 4-stage S/R >approach to an internal reset. I have had >very good results with this approach, because >the four stages give the tools ample opportunity >to replicate the final S/R stage(s) to help >meet timing. > >-- Gabor > Thanks a lot Gabor for the help. I tried 4 stage S/R approach but still the same problem. And there are no failing paths in my design, at least not reported in the timing report. Any other suggestions ? And also, i read this Cummings's paper on synchronous and asynchronous resets which stated the same solution, but i am still facing the same problem. In need of urgent help! Thanks --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150922
On Tue, 22 Feb 2011 01:28:15 -0600, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: >> >Thanks a lot Gabor for the help. I tried 4 stage S/R approach but still the >same problem. And there are no failing paths in my design, at least not >reported in the timing report. Any other suggestions ? And also, i read >this Cummings's paper on synchronous and asynchronous resets which stated >the same solution, but i am still facing the same problem. In need of >urgent help! I have several questions some of which may give you a clue (and hopefully not duplicative): * how many clocks do you have in the system? All of them constrained? Any of them coming from different sources (different oscillators, crystals, PHYs etc?) * did you check the "report unconstrained paths" option? did you read the resulting report? * do you have any latches (mainly combination feedback) in the design? * do you have any divided clocks in the design? * did you constrain all you IOs? did you check the datasheet/scope to verify that these timing values are correct? * do you have any multi-cycle constraints in your design? are you using the version of TRCE/PAR which has a bug with MC paths? (this is a trick question!) -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 150923
Am 21.02.2011 21:34, schrieb Gabor: > The simplest way to work around this is to generate > a local reset signal for each state machine or > module that releases synchronously one or two cycles > after the release of the asynchronous reset and > use that signal as a synchronous reset term for > your state machines. Xilinx usually recommends > a 4-stage shift register to create a reset from > the GSR release. The actual number of stages > required to reset cleanly will depend on the > clock frequency and the size of the device, > where the larger devices can have more skew in > releasing GSR. My designs typically have no > external reset signal and use the 4-stage S/R > approach to an internal reset. I have had > very good results with this approach, because > the four stages give the tools ample opportunity > to replicate the final S/R stage(s) to help > meet timing. Can you post some code (or pointers) demonstrating this reset signal generation? Thanks, ThomasArticle: 150924
On Feb 21, 11:28=A0am, "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >Hi guys, > >I'm searching for a general mathematical definition of an FPGA. > >I propose this y=3DF(x,u) where y is a vector of output , u is a vector > >of input and x is a vector of internal state and F is a certain > >function of x,u. Have you some idea to generalize more this > >definition? > >Thank you, > >Silvio > > What an incredibly daft idea! > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Your superficiality is disarming. Silvio
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