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On Feb 8, 9:48=A0am, Steven Hirsch <snhir...@gmail.com> wrote: > On 02/08/2011 09:23 AM, Bill Garber wrote: > > > > > "Steven Hirsch" <snhir...@gmail.com> wrote in message > >news:BrKdnZLU0fEjpczQnZ2dnUVZ_gednZ2d@giganews.com... > >> On 02/07/2011 08:41 PM, Bill Garber wrote: > > >>> Steven, already offered previously is this, with the reverse directio= n in > >>> the panel to the left of the page. > >>>http://www.mikroe.com/eng/products/view/182/5v-3-3v-voltage-translato.= .. > > >> At the risk of appearing naive, what is the difference between those t= wo > >> boards? Both have high and low voltage ports and both can be switched = in > >> direction. Isn't the overall functionality thus identical? > > > Ok, I will do ALL of the work for you, if I have to. 8^) > > I am just kidding, of course, you know me Steven. :o) > > Heh - I can take ribbing when it's due me.. > > > Yes, the manuals both say, at the bottom of page 2, that both boards ca= n be > > set up to operate in both directions. > > As I said, I looked them over and I feel that this fills your needs mos= t > > admirably. > > Yes, but since they went to so much trouble to design two different produ= cts, > I cannot help but be curious as to why two distinct designs were necessar= y. > There must be something I'm overlooking... =A0Inquiring minds want to kno= w. > > Shop around, Sir, you can get them cheaper. :o) > > I will do so - hopefully they have an importer. > > Steve Try this link: http://www.gadgetfactory.net/index.php?main_page=3Dindex&cPath=3D4 With some digilent cables and headers should be able to lash a setup together.Article: 150751
On 2/7/2011 7:49 PM, cfelton wrote:
> <snip>
>>
>> Thanks for that list Chris - would you be able to comment any more on
>> the MyHDL project? What's it (MyHDL) like as a design environment?
>>
>> Cheers,
>> Martin
>>
>>
>
> MyHDL is a Python module/library for Python. It adds RTL to the Python
> language. You can simulate your RTL design in Python, then convert to
> Verilog/VHDL for synthesis. You can co-simulate MyHDL (python) with the
> Verilog/VHDL.
>
> You would use the same tools (editors, debugger, etc) that you use with any
> Python development.
>
> I find MyHDL very useful in developing IP. You might have many flavors of
> a particular IP, Python can be useful for managing it all. Things like
> managing larger number of registers, in Python you can easily dump all the
> registers to CVS, HTML, etc. Without having to have an external tool to
> parse etc.
>
> For information see the Why MyHDL http://www.myhdl.org/doku.php/why.
I looked at MyHDL several years ago and gave up when I could
not prove that it worked using my standard modelsim/quartus vhdl flow.
Thanks to your review, I looked again, and it seems this has been fixed:
http://www.myhdl.org/doc/0.7/whatsnew/0.6.html#toVHDL
Maybe I will try to torture it again ;)
-- Mike Treseler
Article: 150752On 02/08/2011 04:38 PM, wjc wrote: > Try this link: > http://www.gadgetfactory.net/index.php?main_page=index&cPath=4 > > With some digilent cables and headers should be able to lash a setup > together. Brilliant! That's a much less expensive answer than the Mikroelecktronik gadgets. However, I'm a wee bit doubtful about their claim that a 3.3v output would "drive most 5V logic levels". One application I have in mind is talking to an IDE disk drive or a floppy drive. Would a device like this have enough moxie to do that?Article: 150753
On Feb 8, 2:27=A0pm, Steven Hirsch <snhir...@gmail.com> wrote: > On 02/08/2011 04:38 PM, wjc wrote: > > > Try this link: > >http://www.gadgetfactory.net/index.php?main_page=3Dindex&cPath=3D4 > > > With some digilent cables and headers should be able to lash a setup > > together. > > Brilliant! =A0That's a much less expensive answer than the Mikroelecktron= ik > gadgets. =A0However, I'm a wee bit doubtful about their claim that a 3.3v= output > would "drive most 5V logic levels". =A0One application I have in mind is = talking > to an IDE disk drive or a floppy drive. =A0Would a device like this have = enough > moxie to do that? I don't know. Depends on your device, however the data sheet list max at 120ma per pin which is decent. The schematic, data sheet, etc is all open source. Also you may want to email gadget factory, they are good to replying to emails and may be able to give you some insight.Article: 150754
> I'm also open to other suggestions, of course. Anyone have experience with > these low-cost development kits and chips? Are there any particular interfaces and peripherals you want to use? Unless you're very enthusiastic about designing PCBs and your time is worth nothing, spending more money on a development board that has everything you might possibly want to use in the future is a good investment. I've got an Atlys and it's almost perfect, but: - it doesn't use the standard Xilinx FMC connector, which might bother you if you wanted to add third-party interface boards - it doesn't have a PCI Express connector, which might bother you if you ever decide that you want PCI Express. - if you want to make your own interface board for it, the VHDCI connector is a little tricky to get hold of as Digilent doesn't currently sell it on its own, and the documentation is unclear about the correct gender. Other than that it's great! You get a lot more than the Xilinx SP601 and Avnet Spartan-6 LX16 board for a similar price. At the sub-$100 end of the price scale there are quite a few options, though these may be a bit more limited than what you were after. I've compiled a list at http://tristesse.org/CheapFPGADevelopmentBoards . JoelArticle: 150755
now I am rewriting the whole code in a more clear way as I learnt from xilinx's web seminars. just a tip: when I have a state machine and want to remain in a fixed state what is better to write in vhdl? this when current_state => if nBLAST = '0' then state_m_plx <= next_state; -- conclude the nREADY sequence else null; -- remain here until BLAST if; or this? when current_state => if nBLAST = '0' then state_m_plx <= next_state; -- conclude the nREADY sequence else state_m_plx <= current_state; -- remain here until BLAST if; I am complaining about what the synthesis tool implement when I write NULL; or state_m_plx <= current_state; does it matter??Article: 150756
> does it matter?? It depends on the code that you didn't post. My preferred (and working) way to write a semi complex state machine, is a big but lean combinatorial process. The external inputs are pre-processed in separate processes, as much as possible. For example, a memory interface can pre-process CS/RD and ADDR to produce a qualified "read area x" signal, which then is used by the state machine. At the top of the process, all combinatorial outputs are assigned either a default value or the previous value (from a register). After that, a big CASE statement follows, which handles the various states and their effect on the combinatorial outputs. A separate process registers the combinatorial output of the state machine (and honors reset to provide initial state). This approach is very simple, produces no latches and other pitfalls, and reduces the size of the "big process" to the very minimum necessary. It can be used for purely combinatorial outputs (like same- cycle ack) as well as for pipelined uses, and mixes thereof. It's all determined by the various pre-/postprocessing steps, not inside the state machine. You only have to look at the synthesis output to make sure there are no latches, and no "signal x is not on the sensitivity list" warnings. Those indicate that you made a mistake somewhere. Best regardsArticle: 150757
>now I am rewriting the whole code in a more clear way as I learnt from xilinx's web seminars. just a tip: > >when I have a state machine and want to remain in a fixed state what is better to write in vhdl? >this > >when current_state => > if nBLAST = '0' then > state_m_plx <= next_state; -- conclude the nREADY sequence > else > null; -- remain here until BLAST > if; > > >or this? > >when current_state => > if nBLAST = '0' then > state_m_plx <= next_state; -- conclude the nREADY sequence > else > state_m_plx <= current_state; -- remain here until BLAST > if; > > >I am complaining about what the synthesis tool implement when I write NULL; or state_m_plx <= current_state; > >does it matter?? > As per previous reply, it depends on the rest of your code, for instance, what your coding style is. 1/2/3-process FSM? BUT, the 'null' style is more likely to infer a latch. Latch inference is bad, and XST will issue warnings about them. If you get them, fix them! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150758
Hello everyone, We have got a new project in my company. It's about a controller based in a FPGA. For several reasons we have decided to use Actels FPGAs to implement it. For designing the PCB we use Altium Summer 09. Our doubt is now if using Altium to design the FPGA too or use Libero from Actel. We like Altium because of the synchronisation of pins and the possible integration in the PCB simulations, in addition it looks better as Libero to print planes, and in reality it makes use of the vendor tools (Synplify and Designer) in batch mode. In addition it allows easier portability to another devices. The problem is that we have found massive problems to compile some projects that made use of some special features of the FPGA, for example the integrated ADC. The program crashes when compiling or even when executing usual tasks. In addition there are some error in the libraries for our FPGA, ports names for example (it is fixed very easy). Simulations (post-synthesis, post-layout) are also easier with Libero. In Altium they have told us that in next version (AD10) the demo project that we have sent them doesn't make the program crash but we haven't test the synthesis, P&R... This version will be released next week when they fix some problem they are having. I would like to know your opinion about this. Do you have any experience with Altium? Would you use a non-vendor tool to design your FPGA? We think that maybe Altium looks very good (the idea, the results...) but maybe it isn't reliable enough to handle our big project. Thanks for your att, best regards, Miguel Cholbi --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150759
> I would like to know your opinion about this. Do you have any experience > with Altium? Would you use a non-vendor tool to design your FPGA? We think > that maybe Altium looks very good (the idea, the results...) but maybe it > isn't reliable enough to handle our big project. Miguel, I'm an Altium user but that is exclusively for PCB design. I learned FPGA design in a large teleco co and have contracted since in another large telco, both of which had strict guidelines for FPGA development and both of which I consider did it 'right'. Altium doesn't fit into either of their (very similar) design flows. I also can't understand the 'efficiency' of inteposing another tool between myself and the vendor tools. For a design of any complexity or speed at all you're going to have to learn to drive the vendor tools and trying to do this via a 3rd party just doesn't make sense. There's been some discussion on the Altium forums about this, it seems to help some people (beginners?) but many are sceptical about the approach. Nial.Article: 150760
On 9 Feb., 16:46, "mcholbi" <miguel.cholbicollados@n_o_s_p_a_m.aes- aero.com> wrote: > Our doubt is now if using Altium to design the FPGA too or use Libero from > Actel. We like Altium because of the synchronisation of pins and the > possible integration in the PCB simulations, in addition it looks better as > Libero to print planes, and in reality it makes use of the vendor tools > (Synplify and Designer) in batch mode. In addition it allows easier > portability to another devices. The problem is that we have found massive > problems to compile some projects that made use of some special features of > the FPGA, for example the integrated ADC. The program crashes when > compiling or even when executing usual tasks. In addition there are some > error in the libraries for our FPGA, ports names for example (it is fixed > very easy). Simulations (post-synthesis, post-layout) are also easier with > Libero. Libero is in fact just a framework that allows you to controll the underlying tools. You could as well use all these tools stand-alone without using libero or any similar above. Especially simulation can be handled quite good as Libero uses only Modelsim which is a well known stand alone simulator. I have no clue what Altium allows you to do or not to do. But in corner cases you need at least be able to use the Actel Designer in GUI mode (in my opinion) because you can't do everything in batchmode that can be done with Designer. The question is why using Altium when you want to avoid using Libero? What is provided by Altium that you miss and can't have when using the individual tools stand alone if Altium is only referring to designer in batch mode? bye ThomasArticle: 150761
> We have got a new project in my company. It's about a controller based in > a > FPGA. For several reasons we have decided to use Actels FPGAs to implement > it. For designing the PCB we use Altium Summer 09. ... > I would like to know your opinion about this. Do you have any experience > with Altium? Would you use a non-vendor tool to design your FPGA? We think > that maybe Altium looks very good (the idea, the results...) but maybe it > isn't reliable enough to handle our big project. Here's a data point for ya: We have Altium at my work place. I evaluated it for FPGA design using a Nanoboard Cyclone III. I love the idea of the top to bottom integrated design flow. They have some good ideas in FPGA and embedded SW design flow which is where I spent all my effort. Unfortunately the constant crashing made me decide to not use it for a real FPGA project that was soon to follow. I needed more reliability. Since then (about 2 years) I've been using Altera Quartus. I can't remember a single crash or hangup in Quartus. I don't regret my decision. I used Altium Designer over three revs during which time the crashing was never eliminated nor reduced. I personally wouldn't trust them when they say that the next version won't crash. JJSArticle: 150762
"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote: >> I would like to know your opinion about this. Do you have any experience >> with Altium? Would you use a non-vendor tool to design your FPGA? We think >> that maybe Altium looks very good (the idea, the results...) but maybe it >> isn't reliable enough to handle our big project. > >Miguel, > >I'm an Altium user but that is exclusively for PCB design. > >I learned FPGA design in a large teleco co and have contracted since in another >large telco, both of which had strict guidelines for FPGA development and >both of which I consider did it 'right'. Altium doesn't fit into either >of their (very similar) design flows. > >I also can't understand the 'efficiency' of inteposing another tool between >myself and the vendor tools. For a design of any complexity or speed at all >you're going to have to learn to drive the vendor tools and trying to do this >via a 3rd party just doesn't make sense. I don't know about the quality of current Altium versions (I used it for one or two projects a long time ago and I hated it). The problem with most vendor tools is that the IDE is not their core business so investments in getting it right are minimal. When developing software I like to use Eclipse because it offers a uniform user interface and workflow regardless of the (target) platform. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 150763
On Wed, 2 Feb 2011 00:56:32 -0800 (PST), Emanuele Carraro <emanuele83katamail@googlemail.com> wrote: >Hello everybody, >I got on Friday a new board, with brand new FPGAs soldered rightly (it seems). >Now I test my non-working FW and the 3 boards that I have behaves equally, so I have only two possibility: > >a_ the synthesis tool is failing, bu I tried the same FW on a different machine with a brand new copy of ISE 12.4 installed and it behaves the same in each and every board. Almost certainly not. >b_ my coding style is somehow wrong. I checked the Xilinx's seminar on the web at this address and I watched all the basic HDL and Spartan 3 FPGA specific seminars. Ok, my code is not perfectly written but not with huge errors (for example everything is synchronous the reset path is correctly done, but I use nested if and case that are not the right thing (this is what Xilinx says) >For example, the reset code pointed out by Mike here https://groups.google.com/d/msg/comp.arch.fpga/eQ5EeHECOQw/rO5YroyQhaUJ >is, in Xilinx's opinion, not the best choice. Unlikely - Mike Treseler's style is not quite my choice either, but it is definitely solid and acceptable to XST. >1_ since I have constrained the clock period and offset in and out, with only one clock domain in the entire FPGA( in other words everything is clocked by the same source) and all the constraints are met must I trust the clock report? Even if the design does not behave as expected? I mean, with the same code and constraints, only changing a synthesis parameters (from AUTO to one-hot encoding, for example) the constraints are always met and the timing report does not show any setup/hold violation, how is it possible that the FPGA behaves differently, if not for a synthesis error/mistake or an HW failure? Within its own limitations, the timing report is reliable. >2_ If this is normal: if, changing the code style, or the used resources, the behaviour changes even with all the constraints met, how am I supposed to use a debugger like CHIPSCOPE, which uses the internal FPGA resources? In other words, if introducing a CHIPSCOPE debugger the used resources change and subsequently is expected that the behaviour changes, how is possible to debug correctly? All this is pointing to something else - such as power problems or a noisy (or poorly terminated) clock signal, or some mistake on the I/O pin constraints. When you DO solve the problem and get it stable, you will find that minor changes to the code and settings (adding/removing Chipscope cores etc) will make no appreciable difference. One point that I haven't seen mentioned, is to check that your input and output registers are where you expect them - typically, in the IOBs (I/O blocks). To find out, look at the relevant section near the end of the MAP report (.mrp file). If you want decent predictable I/O signal timing, push the IO registers into the IOBs, and you will see IFF, OFF, ENBFF listed in this section. (There are constraints and design choices which can prevent this happening by default, and it can take some time to find out why and how to overcome them). - BrianArticle: 150764
>In my travels I have found that -- in the US at least -- HDL choice is >very strongly correlated to location: designers on the west coast tend >to use Verilog instead of VHDL, the obverse is the true of folks on the >east coast. > >Designers on each coast like to adopt a cosmopolitan air and claim to be >_completely agnostic_ about which language that they'd prefer to use -- >at least during the job interview. Then when it comes time to actually >write lines of code, most of them will kick and scream (or at least >quietly hyperventilate) if they don't get to use the language that >they're accustomed to. > >So -- where are you from, and what HDL do you use? Have you seen >patterns of language use in your area change in the last decade or so? > >I'm particularly interested in hearing from folks outside the US, and >from folks in the US but not on the coasts. Noting whether you're from >a military hardware background or purely civilian is of interest, too. > Location: England After a number of years doing ASIC/CPLD/FPGA/other design with proprietary netlists and schematics, my first HDL project was in 1999. Because it was military, it had to be VHDL. Since then I haven't done any significant level of Verilog. I have done civilian, military and "dual-use" projects since then. I like VHDL - the strong typing, the function/process overloading, the verbose syntax, the long_and_descriptive signal/process/etc. names. Because of the available frameworks, it looks like SystemVerilog would be good for testbenches - perhaps I'll get a chance to use in the next 15 years. HTH! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150765
Have a look at our Drigmorn3 board http://www.enterpoint.co.uk/drigmorn/dri= gmorn3.html. It's a nice board particularly for the embedded processor side with RTC, LCD, PS2, Ethernet, DDR3 memory, SPI Flash, memory card socket, accelerometer, 4 x 3 LEDs (traffic lights), USB and 40 5V tolerant I/O features. There is also the big brother Drigmorn4 http://www.enterpoint.co.uk/drigmor= n/drigmorn4.html but I think that might be out of your budget. The significantly enhanced Issue2 will be available within a few days including in limited quantities the XC6SLX45 and XC6SLX75 versions that are ISE Webpack compatible. The XC6SLX150 version will offer a new I/O interface with 40 Gbit/s capability that we will be using to support a number of interesting add-ons including a FMC interface adaptor. Discounts on both these products are available to students and other academic buyers. John Adair Enterpoint Ltd. On Feb 8, 11:14=A0am, "Caeliferum" <chatthak@n_o_s_p_a_m.uoguelph.ca> wrote: > I've been doing digital design for awhile now both in class and in my co-= op > terms. I work with FPGAs pretty regularly. However, I have some side > projects in my head that I want to work on, so I'd like a board for my > personal use. Projects that may require a bit more kick. DSP, embedded > processor design, maybe even ANN, etc. > > I don't really want to spend any more than, say, $500. So I've been looki= ng > at the following dev kits: > > DE2-115 (Cyclone IV)http://www.terasic.com.tw/cgi-bin/page/archive.pl?Lan= guage=3DEnglish&Ca... > > and > > Atlys (Spartan 6)http://digilentinc.com/Products/Detail.cfm?NavPath=3D2,4= 00,836&Prod=3DATLYS > > I admit I haven't used the Altera tool set, but at the end of the day its > the hardware and synthesis quality that matters. > > I'm also open to other suggestions, of course. Anyone have experience wit= h > these low-cost development kits and chips? > > Any and all help is greatly appreciated! :) > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comArticle: 150766
Power consumption will vary with the FPGA build and frequency of operation. By experience a XC3SD1800A might take between 0.25A and 4A on the core voltage of 1.2V. Similar variations are also possible on the Vcco input for bank voltages. To narrow this all down try using the Xilinx Xpower tool. Even if you don't have a finished FPGA design it can give some indication fo what you might need. John Adair Enterpoint Ltd. - Home of Hollybush2. The FPGA PC104 Board. On Feb 8, 11:14=A0am, "chethansharma" <chethan.sharma.p@n_o_s_p_a_m.gmail.com> wrote: > Hello, > =A0 =A0 =A0 =A0 =A0I wanted to know the power specification of Spartan-3A > (XC3SD1800A).In the data sheet it does not speak precisely of the power > consumption. How much is the power rating of the board? Also what,s the > maximum current the board needs or withstand -- is less than 4A sufficien= t > to drive the board safely? Please throw some light on the above queries. > > Cheers; > Chethan > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comArticle: 150767
On Feb 9, 5:31=A0am, Emanuele C <emanuele83katam...@googlemail.com> wrote: > now I am rewriting the whole code in a more clear way as I learnt from xi= linx's web seminars. just a tip: > > when I have a state machine and want to remain in a fixed state what is b= etter to write in vhdl? > this > > when current_state =3D> > =A0 =A0if nBLAST =3D '0' then > =A0 =A0 =A0 =A0 state_m_plx <=3D next_state; -- conclude the nREADY seque= nce > =A0 =A0else > =A0 =A0 =A0 =A0 null; -- remain here until BLAST > =A0 =A0if; > > or this? > > when current_state =3D> > =A0 =A0if nBLAST =3D '0' then > =A0 =A0 =A0 =A0 state_m_plx <=3D next_state; -- conclude the nREADY seque= nce > =A0 =A0else > =A0 =A0 =A0 =A0 state_m_plx <=3D current_state; -- remain here until BLAS= T > =A0 =A0if; > > I am complaining about what the synthesis tool implement when I write NUL= L; or state_m_plx <=3D current_state; > > does it matter?? I don't think all synthesis tools are the same in all regards. If your code is part of a clocked process, the assignment of the current state to the next state can either combine the current state in the logic for the next state, or it can generate a clock enable. The null assignment likely will generate a clock enable on the FF. I have never seen the null assignment generate logic combined with the logic for the next state. If the above code is in a combinatorial process, the null assignment will generate a latch if no other assignment is made to the next state signal. RickArticle: 150768
On Feb 8, 6:00=A0pm, Joel Williams <nospamwhydontyoublogabou...@nospamgmail.com> wrote: > I've got an Atlys and it's almost perfect, but: > > - it doesn't use the standard Xilinx FMC connector, which might bother > you if you wanted to add third-party interface boards > > - it doesn't have a PCI Express connector, which might bother you if you > ever decide that you want PCI Express. > > - if you want to make your own interface board for it, the VHDCI > connector is a little tricky to get hold of as Digilent doesn't > currently sell it on its own, and the documentation is unclear about the > correct gender. One other drawback to the Atlys is their use of a gigabit-Ethernet PHY that requires a signed NDA before the vendor (Marvell) will let you see the data sheet. That means no open source development can (legally) be conducted with this board, at least as far as Ethernet connectivity is concerned.* Why a company with Digilent's tradition of hacker-friendliness went with a vendor like Marvell, I can't begin to guess. It's a really nice development board otherwise. I was disappointed to see the Marvell part on there, and told them as much. *:Yes, a copy of the data sheet stamped with "Marvell Confidential" and someone else's NDA number can be downloaded from various sources. No, that's not a good substitute for a legally-unencumbered design. -- john, KE5FXArticle: 150769
On Feb 9, 12:05=A0pm, "John Speth" <johnsp...@yahoo.com> wrote: > > We have got a new project in my company. It's about a controller based = in > > a > > FPGA. For several reasons we have decided to use Actels FPGAs to implem= ent > > it. For designing the PCB we use Altium Summer 09. > > ... > > > I would like to know your opinion about this. Do you have any experienc= e > > with Altium? Would you use a non-vendor tool to design your FPGA? We th= ink > > that maybe Altium looks very good (the idea, the results...) but maybe = it > > isn't reliable enough to handle our big project. > > Here's a data point for ya: > > We have Altium at my work place. =A0I evaluated it for FPGA design using = a > Nanoboard Cyclone III. =A0I love the idea of the top to bottom integrated > design flow. =A0They have some good ideas in FPGA and embedded SW design = flow > which is where I spent all my effort. =A0Unfortunately the constant crash= ing > made me decide to not use it for a real FPGA project that was soon to > follow. =A0I needed more reliability. =A0Since then (about 2 years) I've = been > using Altera Quartus. =A0I can't remember a single crash or hangup in Qua= rtus. > I don't regret my decision. > > I used Altium Designer over three revs during which time the crashing was > never eliminated nor reduced. =A0I personally wouldn't trust them when th= ey > say that the next version won't crash. > > JJS This reminds me of my first experience with and HDL. I was starting a new job and they had just bought a new CAD system that supported schematic FPGA design. I went to their week long training class and the last day they taught VHDL. I was impressed with what I learned and decided to use VHDL for the project I was starting... at least it sounded like a good idea. As I worked on the project I found it hard to understand or even figure out what logic was being produced from my code. Support was pretty abysmal so I didn't get much relief. I was told silly things like the names of my signals had no correspondence with the nets in the synthesized design so I shouldn't expect to understand what signal names to look at for debug. The problems grew worse as the project proceeded with the tool crashing a lot and just not synthesizing properly. Work moved along at a snails pace until a month later I threw in the towel and said we would have to switch to the Xilinx tools or the project would never get done in time. After that the project moved along and I actually was able to complete it on schedule. One of the support incidents I had was to call in at 9 AM and not answered for 20 minutes. I thought support was busy and so not picking up. On answering the person let it slip that they simply had not bothered to answer the phones for that whole time and couldn't believe I had stayed on the line waiting all that time! It was within the year that Orcad dropped their synthesis product and started selling a third party product. I thought it was interesting that their product and their support was so bad that the product had to be scrapped. That alone is a pretty significant statement. Not that I'm drawing a parallel with Altium. I was just reminded of one of the engineering stories I remember. RickArticle: 150770
On the topic of gigabit ethernet PHY's, where can one obtain prototype quantities of them? I can't find any on Digikey. Which manufacturers and models are recommended? Allan On Feb 9, 11:25=A0pm, John Miles <jmi...@gmail.com> wrote: > One other drawback to the Atlys is their use of a gigabit-Ethernet PHY > that requires a signed NDA before the vendor (Marvell) will let you > see the data sheet. =A0That means no open source development can > (legally) be conducted with this board, at least as far as Ethernet > connectivity is concerned.* =A0Why a company with Digilent's tradition > of hacker-friendliness went with a vendor like Marvell, I can't begin > to guess. > > It's a really nice development board otherwise. =A0I was disappointed to > see the Marvell part on there, and told them as much. > > *:Yes, a copy of the data sheet stamped with "Marvell Confidential" > and someone else's NDA number can be downloaded from various sources. > No, that's not a good substitute for a legally-unencumbered design. > > -- john, KE5FXArticle: 150771
I didn't think about the generation of a clock enable. I would like to avoi= d it, as xilinx pointed out in its webseminar it is always a good choice to= use a pipeline when the clock enable is used, but in my case, beeing the c= ode implementing a synch state machine is maybe better that a one hot encod= ing recognize the "loop" condition. I mean, I think it is better to avoid c= lock enable when a state machine waits for another signal to switch to the = following state... so.. > when current_state =3D> > if nBLAST =3D '0' then > state_m_plx <=3D next_state; -- conclude the nREADY sequence > else > state_m_plx <=3D current_state; -- remain here until BLAST > if;Article: 150772
Look at DP83865DVH available in Digikey. Most gigabit phys are a real problem to buy in small numbers and even worse to get a datasheet. It's probably not the best part but we use this one because datasheet is in the public domain and our customers can get the datasheet. It's also easy to get. John Adair Enterpoint Ltd. On Feb 10, 5:18=A0am, Allan Wang <alla...@gmail.com> wrote: > On the topic of gigabit ethernet PHY's, where can one obtain prototype > quantities of them? I can't find any on Digikey. Which manufacturers > and models are recommended? > > Allan > > On Feb 9, 11:25=A0pm, John Miles <jmi...@gmail.com> wrote: > > > One other drawback to the Atlys is their use of a gigabit-Ethernet PHY > > that requires a signed NDA before the vendor (Marvell) will let you > > see the data sheet. =A0That means no open source development can > > (legally) be conducted with this board, at least as far as Ethernet > > connectivity is concerned.* =A0Why a company with Digilent's tradition > > of hacker-friendliness went with a vendor like Marvell, I can't begin > > to guess. > > > It's a really nice development board otherwise. =A0I was disappointed t= o > > see the Marvell part on there, and told them as much. > > > *:Yes, a copy of the data sheet stamped with "Marvell Confidential" > > and someone else's NDA number can be downloaded from various sources. > > No, that's not a good substitute for a legally-unencumbered design. > > > -- john, KE5FXArticle: 150773
What about the VSC8601? How come it is so cheap compared to the DP83865DVH? Forgive my lack of knowledge, but are PHY's mostly compatible with each other? Thanks, Allan On Feb 10, 3:12=A0am, John Adair <g...@enterpoint.co.uk> wrote: > Look at DP83865DVH available in Digikey. Most gigabit phys are a real > problem to buy in small numbers and even worse to get a datasheet. > It's probably not the best part but we use this one because datasheet > is in the public domain and our customers can get the datasheet. It's > also easy to get. > > John Adair > Enterpoint Ltd. > > On Feb 10, 5:18=A0am, Allan Wang <alla...@gmail.com> wrote: > > > > > > > > > On the topic of gigabit ethernet PHY's, where can one obtain prototype > > quantities of them? I can't find any on Digikey. Which manufacturers > > and models are recommended? > > > Allan > > > On Feb 9, 11:25=A0pm, John Miles <jmi...@gmail.com> wrote: > > > > One other drawback to the Atlys is their use of a gigabit-Ethernet PH= Y > > > that requires a signed NDA before the vendor (Marvell) will let you > > > see the data sheet. =A0That means no open source development can > > > (legally) be conducted with this board, at least as far as Ethernet > > > connectivity is concerned.* =A0Why a company with Digilent's traditio= n > > > of hacker-friendliness went with a vendor like Marvell, I can't begin > > > to guess. > > > > It's a really nice development board otherwise. =A0I was disappointed= to > > > see the Marvell part on there, and told them as much. > > > > *:Yes, a copy of the data sheet stamped with "Marvell Confidential" > > > and someone else's NDA number can be downloaded from various sources. > > > No, that's not a good substitute for a legally-unencumbered design. > > > > -- john, KE5FXArticle: 150774
Speaking of alternative ways... I should tell you about my latest project, a bi-"linear" image scaler (up+down) with very wide scaling range (and tweakable "linear" function for improved image on large scaling factors). This is mainly developed in OPENOFFICE CALC! :) And I do the simulation in real-time as I correct formulas. I make sure to write formulas in a logic style, so it can be translated to vhdl. I can now put pixels into a cell area to simulate the input image, and I get an area with the output image (hex values, cause the spreadsheet can't turn rgb values into cell colors (yet)) I'm about to translate the formulas into vhdl and simulate a bit to verify that the result matches with the spreadsheet (that means I've translated the spreadsheet correctly into vhdl). It turns out to work very well so far. What would do this a lot simpler is if the spreadsheet could do these simple things: -Take formula parameters with labels from the row above. Now it can only work with labels from the current row, unless you want to write some complex offset functions in there, but that will make the formula unreadable. -color a cell from RGB values (would give REAL images as test data) To improve my current situation I could probably make a seperate sheet named 'prev' for the previous variables and access the previous states with a prev.<label>, but that would require me to pay extra attention when inserting or deleting columns. I guess I cold easily make some conditional formatting that would help me detect if the columns were out of sync, so I may try that to make it even simpler. Maybe some scripting of the openoffice would help you translate the sheet directly to some other hdl format that FPGA tools can work on. Now, what irritates me is that there is no FPGA adapted tool that would work this way. In my head I can visualize how it should work, and it would be very similar to a spreadsheet, and you could even get real time information about fan-outs (non optimized of course), signal type (combinatorical or FF or other blackboxes). If the days had more hours, I would start coding it myself :) [In the end I also plan to do two pixels pr clk for high bandwidth support :) ]
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