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On Feb 2, 3:56=A0am, Emanuele Carraro <emanuele83katam...@googlemail.com> wrote: > Hello everybody, > I got on Friday a new board, with brand new FPGAs soldered rightly (it se= ems). > Now I test my non-working FW and the 3 boards that I have behaves equally= , so I have only two possibility: > > a_ the synthesis tool is failing, bu I tried the same FW on a different m= achine with a brand new copy of ISE 12.4 installed and it behaves the same = in each and every board. > > b_ my coding style is somehow wrong. I checked the Xilinx's seminar on th= e web at this address and I watched all the basic HDL and Spartan 3 FPGA sp= ecific seminars. Ok, my code is not perfectly written but not with huge err= ors (for example everything is synchronous the reset path is correctly done= , but I use nested if and case that are not the right thing (this is what X= ilinx says) > For example, the reset code pointed out by Mike herehttps://groups.google= .com/d/msg/comp.arch.fpga/eQ5EeHECOQw/rO5YroyQhaUJ > is, in Xilinx's opinion, not the best choice. > > Now I decided to rewrite the whole project following Xilinx's advices but= before, please, focus on these two questions and only on these two: > > 1_ since I have constrained the clock period and offset in and out, with = only one clock domain in the entire FPGA( in other words everything is cloc= ked by the same source) and all the constraints are met must I trust the cl= ock report? Even if the design does not behave as expected? I mean, with th= e same code and constraints, only changing a synthesis parameters (from AUT= O to one-hot encoding, for example) the constraints are always met and the = timing report does not show any setup/hold violation, how is it possible th= at the FPGA behaves differently, if not for a synthesis error/mistake or an= HW failure? > > 2_ If this is normal: if, changing the code style, or the used resources,= the behaviour changes even with all the constraints met, how am I supposed= to use a debugger like CHIPSCOPE, which uses the internal FPGA resources? = In other words, if introducing a CHIPSCOPE debugger the used resources chan= ge and subsequently is expected that the behaviour changes, how is possible= to debug correctly? > > Only doing errors is possible to learn, but without understanding them is= not possible to learn at all. > > Many thanks, > Emanuele > > P.S. I am using the ISE tool for my projects, have you got advices for a = different/surely-better tool for synthesis, translate, map and PAR with als= o a spread availability of IPs? You are barking up the wrong tree. Clearly you have not done much HDL debug. The tools are the very last thing you should suspect. In my 15 odd years of programming in HDL I have only once seen a problem with the tools relating to timing and that we very clearly a tool problem once we tested on the hardware. You need to pay attention to what people are telling you instead of focusing on the idea that the problem has to have something to do with timing constraints. I have already suggested that you need to look at external interfaces to see if they could be causing a problem. If you have asynchronous signals entering your design and they are not properly handled, they can cause intermittent and unpredictable problems. You could easily have problems with the hardware design. Ground bounce is always a concern when you have many outputs switching at the same time. I suggest that you simplify your code to isolate the problem. Cut out sections of logic until the design pieces work reliably. If that is not practical, write some new code to test the various external interfaces. Do something other than just testing with your entire body of code. Or insert debug signals that come out to pins you can probe. This is the tried and true method in place of chipscope. Obviously what you are doing now is not getting you very far. You need to change tactics. You need to take some good advice. RickArticle: 150676
On Feb 2, 6:33=A0am, comp arch <comparchf...@gmail.com> wrote: > 2) Chipscope has helped me countless times, it really is a great tool. > I do see the dilemma here where you are concerned that adding it will > change the utilization, and as a result change the behavior again. So > the only suggestions i have here are: > - turn on design preservation. This should retain the synthesis and > placement/routing of unchanged parts of the design, and should fit > chipscope blocks into 'free' space. Of course some of the design may > have to be moved, but the tools do all they can to prevent that. If > the place and route are preserved, then so should design behaviour > - if inserting chipscope does cause the design to start functioning - > then I would keep iterating and making small tweaks until the design > is failing once more, but this time with chipscope in. Bingo! This is not uncommon in software development. Turn on debug output and the problem goes away. Solution, ship with debug on if your memory allows it. In the case of FPGAs chipscope is much less likely to cause fit problems. With with chipscope turned on and see what you can get done. Even if the symptoms change, at some point the probes and the problem should converge. RickArticle: 150677
rickman wrote: > On Feb 2, 3:56 am, Emanuele Carraro > <emanuele83katam...@googlemail.com> wrote: >> 1_ since I have constrained the clock period and offset in and out, >> with only one clock domain in the entire FPGA( in other words >> everything is clocked by the same source) and all the constraints >> are met must I trust the clock report? Even if the design does not >> behave as expected? I mean, with the same code and constraints, only >> changing a synthesis parameters (from AUTO to one-hot encoding, for >> example) the constraints are always met and the timing report does >> not show any setup/hold violation, how is it possible that the FPGA >> behaves differently, if not for a synthesis error/mistake or an HW >> failure? > > You are barking up the wrong tree. Clearly you have not done much HDL > debug. The tools are the very last thing you should suspect. In my > 15 odd years of programming in HDL I have only once seen a problem > with the tools relating to timing and that we very clearly a tool > problem once we tested on the hardware. > > You need to pay attention to what people are telling you instead of > focusing on the idea that the problem has to have something to do with > timing constraints. > > I have already suggested that you need to look at external interfaces > to see if they could be causing a problem. If you have asynchronous > signals entering your design and they are not properly handled, they > can cause intermittent and unpredictable problems. You could easily > have problems with the hardware design. Ground bounce is always a > concern when you have many outputs switching at the same time. > > I suggest that you simplify your code to isolate the problem. Cut out > sections of logic until the design pieces work reliably. If that is > not practical, write some new code to test the various external > interfaces. Do something other than just testing with your entire > body of code. Or insert debug signals that come out to pins you can > probe. This is the tried and true method in place of chipscope. > > Obviously what you are doing now is not getting you very far. You > need to change tactics. You need to take some good advice. > > Rick Good advice from Rick. As another answer to your question #1, I had a design where some of the LOC constraints from the UCF file were commented out as part of an unrelated experiment. They were not put back and the result was that after every map run those top level nets moved to different pins, depending on the placement of the related logic. I was new to FPGA at the time and also blamed timing problems, and it took quite a while to track down the problem. So there is more to it than just functional simulation and passing timing constraints. Regarding timing constraints, don't rely on the timing score reported by par. A design that gets a timing score of 0 in par can have a negative score from the timing analyzer. I think this is because par doesn't look at unconstrained paths. Run a timing report, and be sure to run it with -u (I believe) to report unconstrained paths. Your goal should be no unconstrained paths, although that can be hard on more complicated designs. Using FPGA editor you can insert probes that are routed around your existing logic. The online help has specific directions for doing this. Bring out some internal nets and look at them on the scope. This is my first choice method of debug, after functional simulation, because the turn time is much faster than rerunning map/par. --steveArticle: 150678
In my travels I have found that -- in the US at least -- HDL choice is very strongly correlated to location: designers on the west coast tend to use Verilog instead of VHDL, the obverse is the true of folks on the east coast. Designers on each coast like to adopt a cosmopolitan air and claim to be _completely agnostic_ about which language that they'd prefer to use -- at least during the job interview. Then when it comes time to actually write lines of code, most of them will kick and scream (or at least quietly hyperventilate) if they don't get to use the language that they're accustomed to. So -- where are you from, and what HDL do you use? Have you seen patterns of language use in your area change in the last decade or so? I'm particularly interested in hearing from folks outside the US, and from folks in the US but not on the coasts. Noting whether you're from a military hardware background or purely civilian is of interest, too. TIA. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 150679
On Wed, 02 Feb 2011 15:08:31 -0800, Tim Wescott wrote: > In my travels I have found that -- in the US at least -- > HDL choice is very strongly correlated to location: > designers on the west coast tend to use Verilog > instead of VHDL, the obverse is the true of folks on > the east coast. There's certainly some truth in that, but there's probably a stronger correlation with target technology: FPGA folks are still predominantly VHDL everywhere, ASIC shops use Verilog. That gives a geographic bias as well, because of the heavy concentration of ASIC shops on the west coast. Of course there are plenty of exceptions. I know of a fair few ASIC places that use VHDL for front-end RTL design even though their backend flow is necessarily Verilog. Front-end tools mostly don't care these days, certainly not the industrial-strength tools that ASIC designers can afford. > Designers on each coast like to adopt a cosmopolitan air > and claim to be _completely agnostic_ about which language > that they'd prefer to use -- at least during the job > interview. Then when it comes time to actually write > lines of code, most of them will kick and scream (or > at least quietly hyperventilate) if they don't get >to use the language that they're accustomed to. If you're in a steady job, there's little motivation to learn stuff (like another HDL) that isn't actively used in your work. It's as easily forgotten as learnt unless you practise. So while I agree with your observation, I don't find it very surprising. And I certainly sympathize; I've done some pretty heavy breathing myself recently when faced with truckloads of Perl and Ruby, in neither of which am I fluent. Learning fast, though :-) >So -- where are you from, England, though I've travelled widely for training and contract work. > and what HDL do you use? SystemVerilog at my current work; plenty of both VHDL and Verilog in the past. Always VHDL when doing contract design/verification work for small FPGA-using companies. Occasional use of e (Specman) for verification. > Have you seen patterns of language use in your > area change in the last decade or so? Yes, but not that fast. SystemVerilog has definitely moved the goalposts by offering all the benefits of VHDL, and plenty more, for verification; that's pushed many users over the edge to Verilog, I think (although the relative stagnation of VHDL may have contributed too). FPGA tools now are language-neutral so newcomers to FPGAs can choose their preferred HDL, whereas ten years ago they were likely encouraged to use VHDL in most cases. The use of giant FPGAs as ASIC prototypes has boosted Verilog use in the FPGA world. There are military users, and a few high-end telecoms companies, that routinely use VHDL for all RTL design; that doesn't seem to be changing much. Not too surprising when any large organization will have built up a big collection of in-house IP and knowhow in their existing HDL. Again it's worth remembering that most front-end tools support both languages, so HDL inertia is always a viable option. Tools support mixed- language designs too, so you can buy in Verilog IP and incorporate it in your VHDL design, or vice versa. > Noting whether you're from a military hardware > background or purely civilian is of interest, too. Never done any mainstream military stuff myself, though I've taught a fair few training courses at companies in the military market and they do indeed tend to be VHDL users. At least, they're much more likely to be VHDL users than comparable organizations in the civilian segment. It would be interesting to hear comments from users in the huge and rapidly evolving design sectors in Asia. My instinct, and the limited anecdotal evidence I have, suggests that Verilog and SystemVerilog utterly dominate there. -- Jonathan BromleyArticle: 150680
Hi, For my project we are using Xilinx Virtex-6 FPGAs. I have a specific requirement where I would like to change the IO voltage(VCCO) of one bank from 3.3V to 1.8V. Assuming that the core is working at a different voltage and IOs on different. Core at the start works with 3.3V and then drives the IOs to Z and then we would like to change the VCCO of this particular bank and start working at 1.8V. Note that we do not want to recreate bitmap or reload the design. While this swithcing is happening we would like to let our core work continuously with other set of IO bank whose voltage is not switching. Is this dynamic voltage switching possible. If yes it would be great to know how this can be achieved. I believe some kind of registers will need to be programmed to achieve this. Thanks Kolar --------------------------------------- Posted through http://www.FPGARelated.com From prenom.nom@gmail.com Thu Feb 03 05:37:26 2011 Path: unlimited.newshosting.com!s02-b36.iad!npeersf01.iad.highwinds-media.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!news4.google.com!proxad.net!feeder1-2.proxad.net!cleanfeed4-a.proxad.net!nnrp4-1.free.fr!not-for-mail Date: Thu, 3 Feb 2011 14:37:26 +0100 From: Matthieu Michon <prenom.nom@gmail.com> Newsgroups: comp.arch.fpga Subject: Suggestions for a FPGA friendly 10 Mbit/s industrial bus ? Message-Id: <20110203143726.be1ae17e.prenom.nom@gmail.com> X-Newsreader: Sylpheed 3.0.2 (GTK+ 2.10.14; i686-pc-mingw32) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 26 Organization: Guest of ProXad - France NNTP-Posting-Date: 03 Feb 2011 14:37:57 MET NNTP-Posting-Host: 213.215.9.6 X-Trace: 1296740277 news-1.free.fr 26424 213.215.9.6:54798 X-Complaints-To: abuse@proxad.net Xref: unlimited.newshosting.com comp.arch.fpga:108417 X-Received-Date: Thu, 03 Feb 2011 13:37:57 UTC (s02-b36.iad) Hi all I'm looking at different solutions for connecting a FPGA-based system (hw/fw designed by us) to a industrial controller (NI CompactRIO), and would make use of some suggestions or clues to be sure that I don't get the wrong idea our locked in a dead-end. The estimated data rate is around 5 to 10 Mbit/s unidirectionnal (FPGA system -> CompactRIO), and maximum latency should be under 1 ms (jitter is not an issue). Cable length So far I came across the following protocols supported by the CompactRIO: * Fast-Ethernet * Profibus The Fast-Ethernet electrical implementation appears to be more complex then Profibus (RS-485), on the other side the implementation of the UDP/IP/Ethernet stack seems easier (a lot) than Profibus. At first sight I was about to go with Profibus, however after looking into the high-level layers of Profibus and how to implement them in our system (designing our own Profibus controller in HDL, or using an IP, or even a AM1810), I'm less confident with this solution and starting to think that Ethernet would be better for us. Does anybody have some thoughts about all this ? Kind regards --- Matthieu MichonArticle: 150681
I would of thought that if it was possible to do that then the user guides would tell you how. Cant you just use an external circuit to do the same thing? Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150682
>Hi, > >For my project we are using Xilinx Virtex-6 FPGAs. I have a specific >requirement where I would like to change the IO voltage(VCCO) of one bank >from 3.3V to 1.8V. Assuming that the core is working at a different voltage >and IOs on different. Core at the start works with 3.3V and then drives the >IOs to Z and then we would like to change the VCCO of this particular bank >and start working at 1.8V. > >Note that we do not want to recreate bitmap or reload the design. While >this swithcing is happening we would like to let our core work continuously >with other set of IO bank whose voltage is not switching. > >Is this dynamic voltage switching possible. If yes it would be great to >know how this can be achieved. I believe some kind of registers will need >to be programmed to achieve this. > >Thanks >Kolar I am > 90% certain that it isn't possible. But just to be sure, ask at: http://forums.xilinx.com/t5/Virtex-Family-FPGAs/bd-p/Virtex --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150683
Does your FPGA have a built in ethernet MAC? If so, the answer to your question should be pretty clear - basic Ethernet (unidirectional UDP packets) is relatively easy if you have a MAC. ChrisArticle: 150684
This has been discussed before, though I can't find the thread. The general= pattern is that VHDL/Verilog is about 50/50 in the FPGA world, with a bias= towards VHDL on the east side of N. America and Europe. The exception is C= alifornia where Verilog dominates FPGA work. ASIC work is largely dominated= by Verilog. I'm not sure what the historical reasons for this pattern are. Generally in= a given region one tends to be more dominant than the other due mostly to = availability of workers and what relevant courses in neighbouring universit= ies have used over the years. Here in the Toronto area I have the impression it's mostly VHDL, except in = the North East where there a fair bit of chip development and Verilog tends= to be dominant. ChrisArticle: 150685
On Feb 3, 5:24=A0am, "kolar" <kamleshrr@n_o_s_p_a_m.gmail.com> wrote: > Hi, > > For my project we are using Xilinx Virtex-6 FPGAs. I have a specific > requirement where I would like to change the IO voltage(VCCO) of one bank > from 3.3V to 1.8V. Assuming that the core is working at a different volta= ge > and IOs on different. Core at the start works with 3.3V and then drives t= he > IOs to Z and then we would like to change the VCCO of this particular ban= k > and start working at 1.8V. > > Note that we do not want to recreate bitmap or reload the design. While > this swithcing is happening we would like to let our core work continuous= ly > with other set of IO bank whose voltage is not switching. > > Is this dynamic voltage switching possible. If yes it would be great to > know how this can be achieved. I believe some kind of registers will need > to be programmed to achieve this. > > Thanks > Kolar > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com The IO configuration bits would need to be reprogrammed to enable this to work. This isn't a register write, but a reload of the configuration bits. Ed McGettigan -- Xilinx Inc.Article: 150686
On Feb 2, 5:08=A0pm, Tim Wescott <t...@seemywebsite.com> wrote: > In my travels I have found that -- in the US at least -- HDL choice is > very strongly correlated to location: designers on the west coast tend > to use Verilog instead of VHDL, the obverse is the true of folks on the > east coast. > > Designers on each coast like to adopt a cosmopolitan air and claim to be > _completely agnostic_ about which language that they'd prefer to use -- > at least during the job interview. =A0Then when it comes time to actually > write lines of code, most of them will kick and scream (or at least > quietly hyperventilate) if they don't get to use the language that > they're accustomed to. > > So -- where are you from, and what HDL do you use? =A0Have you seen > patterns of language use in your area change in the last decade or so? > > I'm particularly interested in hearing from folks outside the US, and > from folks in the US but not on the coasts. =A0Noting whether you're from > a military hardware background or purely civilian is of interest, too. > > TIA. > > -- > > Tim Wescott > Wescott Design Serviceshttp://www.wescottdesign.com > > Do you need to implement control loops in software? > "Applied Control Theory for Embedded Systems" was written for you. > See details athttp://www.wescottdesign.com/actfes/actfes.html I'm in Texas and use both VHDL and Verilog because I've worked for defense and commercial semiconductor companies. The defense sector generally uses VHDL. Verilog dominates the commercial SoC industry (which is mostly west coast), though I know of one large development group at Texas Instruments (Dallas location) that uses VHDL. Sometimes I'll use both languages in one project because the IP I stitch together will be a mixture of VHDL and Verilog. In the old days, most test benches would use VHDL, even if the device itself was done in Verilog. Now with SystemVerilog and some of the special verification languages (e.g., Specman), VHDL no longer has the advantage for test- bench development. My preferred HDL is Verilog. It's simpler, and I don't like to remember all of the type conversion semantics that VHDL imposes - just let me load the register - sheesh! Darol KlawetterArticle: 150687
On Feb 3, 8:24=A0am, "kolar" <kamleshrr@n_o_s_p_a_m.gmail.com> wrote: > Hi, > > For my project we are using Xilinx Virtex-6 FPGAs. I have a specific > requirement where I would like to change the IO voltage(VCCO) of one bank > from 3.3V to 1.8V. Assuming that the core is working at a different volta= ge > and IOs on different. Core at the start works with 3.3V and then drives t= he > IOs to Z and then we would like to change the VCCO of this particular ban= k > and start working at 1.8V. > > Note that we do not want to recreate bitmap or reload the design. While > this swithcing is happening we would like to let our core work continuous= ly > with other set of IO bank whose voltage is not switching. > > Is this dynamic voltage switching possible. If yes it would be great to > know how this can be achieved. I believe some kind of registers will need > to be programmed to achieve this. > > Thanks > Kolar > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com I'm pretty sure the maximum Vcco for Virtex 6 is 2.5V, not 3.3V. Within the usable range of Vcco, you can use the same LVCMOS I/O standard without changing the bitstream, just by picking the lowest voltage to be used. What you end up with is I/O that drives considerably stronger that the standard you picked when Vcco is larger than that standard's nominal value. For example starting with LVCMOS_18 @4 mA and driving Vcco to 2.5V will result in much more drive than 4 mA. If you really need to change IO standard, rather than "fudging it" with variable Vcco LVCMOS, then you would need to do at least partial reconfiguration. -- GaborArticle: 150688
> I'm particularly interested in hearing from folks outside the US, and from > folks in the US but not on the coasts. Noting whether you're from a > military hardware background or purely civilian is of interest, too. Lithuania, Europe. I prefer VHDL. Moving to the new company, which specializes in RF, Satellite, etc, so they use VHDL for their production.Article: 150689
Tim Wescott <tim@seemywebsite.com> wrote: >In my travels I have found that -- in the US at least -- HDL choice is >very strongly correlated to location: designers on the west coast tend >to use Verilog instead of VHDL, the obverse is the true of folks on the >east coast. > >Designers on each coast like to adopt a cosmopolitan air and claim to be >_completely agnostic_ about which language that they'd prefer to use -- >at least during the job interview. Then when it comes time to actually >write lines of code, most of them will kick and scream (or at least >quietly hyperventilate) if they don't get to use the language that >they're accustomed to. > >So -- where are you from, and what HDL do you use? Have you seen >patterns of language use in your area change in the last decade or so? > >I'm particularly interested in hearing from folks outside the US, and >from folks in the US but not on the coasts. Noting whether you're from >a military hardware background or purely civilian is of interest, too. They tought me VHDL in school in NL. I looked at Verilog a few times but I can't make heads or tails from it. To me Verilog looks like a netlist from a schematic capture package. I recently did a small CPLD project. I used VHDL for that as well. I like the way you can do complex operations with simple functions and use records to keep related signals together. Using VHDL is more like writing software. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 150690
Our existing Xilinx FPGA board has some test output pins of type IO_LXXY_#. They are now configured as IOSTANDARD = LVDS_25 and IOSTANDARD = LVTTL. They are connected to TSW connectors. We wanted to configure them as input pins. Is there anything that we should pay attention on? Where can I find the information on how to design the input and output buffers on PCB? Thanks in advance!Article: 150691
On Feb 2, 6:08=A0pm, Tim Wescott <t...@seemywebsite.com> wrote: > In my travels I have found that -- in the US at least -- HDL choice is > very strongly correlated to location: designers on the west coast tend > to use Verilog instead of VHDL, the obverse is the true of folks on the > east coast. > > Designers on each coast like to adopt a cosmopolitan air and claim to be > _completely agnostic_ about which language that they'd prefer to use -- > at least during the job interview. =A0Then when it comes time to actually > write lines of code, most of them will kick and scream (or at least > quietly hyperventilate) if they don't get to use the language that > they're accustomed to. > > So -- where are you from, and what HDL do you use? =A0Have you seen > patterns of language use in your area change in the last decade or so? > > I'm particularly interested in hearing from folks outside the US, and > from folks in the US but not on the coasts. =A0Noting whether you're from > a military hardware background or purely civilian is of interest, too. > > TIA. > > -- > > Tim Wescott > Wescott Design Serviceshttp://www.wescottdesign.com > > Do you need to implement control loops in software? > "Applied Control Theory for Embedded Systems" was written for you. > See details athttp://www.wescottdesign.com/actfes/actfes.html I'm in the eastern US (New Hampshire) and use pretty much exclusively Verilog. I went through college before there were any HDL's, and spent the first decade of my career with pencil and vellum for schematics. My first programmable logic was PALs and I used PALASM for that, then moved on to Abel, CUPL, and finally back to schematics with Abel when I started out on FPGA's. Verilog came later, but it feels pretty natural to me now. I use it because it's what makes me the most productive. I've never worked for large companies, so the "existing culture" was never a driving force in tool selection. Personally I feel I have benefited by learning logic design before learning HDL's. So many of the clueless answer- seekers on the Xiinx forums seem to think logic design is some sort of software. My preference would be to continue using schematics for a top level design and Verilog underneath. However, the Xilinx tools have a miserable excuse for a schematic editor since they dropped Aldec and rolled their own. It seems Xilinx isn't very interested in schematics and so those of us who can't afford expensive third party tools learn to live without it. Grumble... -- GaborArticle: 150692
Tim Wescott wrote: > In my travels I have found that -- in the US at least -- HDL choice is > very strongly correlated to location: designers on the west coast tend > to use Verilog instead of VHDL, the obverse is the true of folks on the > east coast. > > Designers on each coast like to adopt a cosmopolitan air and claim to be > _completely agnostic_ about which language that they'd prefer to use -- > at least during the job interview. Then when it comes time to actually > write lines of code, most of them will kick and scream (or at least > quietly hyperventilate) if they don't get to use the language that > they're accustomed to. > > So -- where are you from, and what HDL do you use? Have you seen > patterns of language use in your area change in the last decade or so? Seattle, which is on the coast but is mostly a VHDL town, unlike Oregon and California. I use both VHDL and Verilog. I slightly prefer VHDL, however many of the reasons to prefer one language over the other have gone away...Except for the impact of SystemVerilog, which I have not yet used. Civilian projects. -- Phil Hays Phil underbar Hays at ieee dot orgArticle: 150693
On Feb 2, 6:08=A0pm, Tim Wescott <t...@seemywebsite.com> wrote: > In my travels I have found that -- in the US at least -- HDL choice is > very strongly correlated to location: designers on the west coast tend > to use Verilog instead of VHDL, the obverse is the true of folks on the > east coast. > > Designers on each coast like to adopt a cosmopolitan air and claim to be > _completely agnostic_ about which language that they'd prefer to use -- > at least during the job interview. =A0Then when it comes time to actually > write lines of code, most of them will kick and scream (or at least > quietly hyperventilate) if they don't get to use the language that > they're accustomed to. > > So -- where are you from, and what HDL do you use? =A0Have you seen > patterns of language use in your area change in the last decade or so? > > I'm particularly interested in hearing from folks outside the US, and > from folks in the US but not on the coasts. =A0Noting whether you're from > a military hardware background or purely civilian is of interest, too. I started FPGA design using schematics in the 4000 series Xilinx parts. I had a new job where they sent me to school to learn their new design package where they had one day on their HDL tool in VHDL. I came back and told the management that we should not design in schematic anymore and we switched. Although it was a government contracting position, I don't think they influenced the choice of language. Later I worked for a comms test equipment company and they only used Verilog, so I worked in that without any training. When I left there Verilog didn't stick with me and I've been using VHDL since... until the last month when I had a task where the customer wanted Verilog. So I spent the time to actually learn the language, a bit at least. I found Verilog pretty useful and didn't have the hangover I usually get from strong typing. I did find one bug relating to my assumption on what happens when a counter is decremented below 0 (I assumed -1 would be next and Verilog assumed it should wrap around or something). I can't say I wasn't warned... So I may spend more time with Verilog. I learned quite a few things about Verilog doing this project and even talked about some that I found to be uniquely useful only to find that with the 2008 redo of VHDL it has them too for the most part. So the only real difference, if I understand it correctly, is that while Verilog lets you do what you want without excessive explanation, it also makes assumptions about what you mean which may give you something different than what you intended. Otherwise I think Verilog is just plain easier to work with. Just learn the Verilog assumptions and you should be pretty good to go. RickArticle: 150694
>Our existing Xilinx FPGA board has some test output pins of type >IO_LXXY_#. They are now configured as IOSTANDARD = LVDS_25 and >IOSTANDARD = LVTTL. They are connected to TSW connectors. >We wanted to configure them as input pins. Is there anything that we >should pay attention on? > >Where can I find the information on how to design the input and output >buffers on PCB? Thanks in advance! > I am unsure of what exactly you are asking. IO_LXXY_# gives the location of the IO pin inside the FPGA. You have set these as LVDS and LVTTL. The buffers are contained in the IO block of the FPGA that you are using. You need to look in the user guide at the section that gives info about the IO standards. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150695
"Tim Wescott" <tim@seemywebsite.com> wrote in message news:UPCdna5sk-ORedTQnZ2dnUVZ_j-dnZ2d@web-ster.com... > In my travels I have found that -- in the US at least -- HDL choice is > very strongly correlated to location: designers on the west coast tend to > use Verilog instead of VHDL, the obverse is the true of folks on the east > coast. > > Designers on each coast like to adopt a cosmopolitan air and claim to be > _completely agnostic_ about which language that they'd prefer to use -- > at least during the job interview. Then when it comes time to actually > write lines of code, most of them will kick and scream (or at least > quietly hyperventilate) if they don't get to use the language that they're > accustomed to. > > So -- where are you from, and what HDL do you use? Have you seen patterns > of language use in your area change in the last decade or so? > > I'm particularly interested in hearing from folks outside the US, and from > folks in the US but not on the coasts. Noting whether you're from a > military hardware background or purely civilian is of interest, too. > > TIA. > > -- > > Tim Wescott > Wescott Design Services > http://www.wescottdesign.com > > Do you need to implement control loops in software? > "Applied Control Theory for Embedded Systems" was written for you. > See details at http://www.wescottdesign.com/actfes/actfes.html I'm in the UK (South West Scotland) and use VHDL. Like one of the other posters I much prefer to use schematic entry at the top level. I have an Aldec license so I use their schematic entry and it does all that tedious gluing of the VHDL blocks together. I write the blocks in VHDL but use the Aldec tools to generate template files. I would look at Verilog but my Aldec license would need an expensive upgrade so there would need to be a compelling commercial reason to go that way. Michael KellettArticle: 150696
Tim Wescott <tim@seemywebsite.com> writes: > So -- where are you from, and what HDL do you use? Have you seen > patterns of language use in your area change in the last decade or so? > Summary: UK-based, VHDL, automotive applications. We were "shown" VHDL at University, we built a stepper-motor controller in Abel. I was taught VHDL at work within a year or so of graduation (some of my colleagues at that time were using AHDL and schematic entry) and did some small tasks. I've been using VHDL seriously since 2000. I don't miss schematics, I use Emacs to do the tedious wiring part of the top-level design and Visio to document the block interactions. In the last couple of years I'm starting to feel some "push-out-of-VHDL" because the simulation vendors have been pushing SystemVerilog so much. An awful lot of verification now seems to be being done in SV, even of VHDL RTL code. I'm currently VHDL throughout, but wondering if I should change :0 Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 150697
On Feb 3, 10:39=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > Tim Wescott <t...@seemywebsite.com> wrote: > >In my travels I have found that -- in the US at least -- HDL choice is > >very strongly correlated to location: designers on the west coast tend > >to use Verilog instead of VHDL, the obverse is the true of folks on the > >east coast. > > >Designers on each coast like to adopt a cosmopolitan air and claim to be > >_completely agnostic_ about which language that they'd prefer to use -- > >at least during the job interview. =A0Then when it comes time to actuall= y > >write lines of code, most of them will kick and scream (or at least > >quietly hyperventilate) if they don't get to use the language that > >they're accustomed to. > > >So -- where are you from, and what HDL do you use? =A0Have you seen > >patterns of language use in your area change in the last decade or so? > > >I'm particularly interested in hearing from folks outside the US, and > >from folks in the US but not on the coasts. =A0Noting whether you're fro= m > >a military hardware background or purely civilian is of interest, too. > > They tought me VHDL in school in NL. I looked at Verilog a few times > but I can't make heads or tails from it. To me Verilog looks like a > netlist from a schematic capture package. I recently did a small CPLD > project. I used VHDL for that as well. I like the way you can do > complex operations with simple functions and use records to keep > related signals together. Using VHDL is more like writing software. > > -- > Failure does not prove something is impossible, failure simply > indicates you are not using the right tools... > nico@nctdevpuntnl (punt=3D.) > -------------------------------------------------------------- Wow, strange that you have the same opinion as me, except the languages are reversed! I use Verilog almost exclusively (have had to hack some VHDL to add ports from time to time, for debug of IP cores provided to me) Whenever I look into a VHDL design, I always marvel at how needlessly verbose it is with the package and entity, etc. How hard it is to find the 'meat' of the code, how crazy the case insensitivity is, and how I have to convert signals to and from std_logic_vector to other types to simply increment a value. (I know the strict typing is part of VHDL's pros for most people - but it's not for me) I suppose it's what you are used to - if you use Verilog, anything else will look alien, and likewise for VHDL. As for the Map - work in an ASIC house, in northern europe, and the company is San Jose based. We use verilog exclusively for ASIC design, but IP we ship externally is in VHDLArticle: 150698
"Gabor" <gabor@alacron.com> wrote in message news:7067a8f2-b504-4eb2-bbc6-2f7bb0b73708@o1g2000yqb.googlegroups.com... > I'm in the eastern US (New Hampshire) and use pretty much exclusively > Verilog. I'm on the west coast, and use VHDL (although my last gig involved Verilog). > I went through college before there were any HDL's, and > spent the first decade of my career with pencil and vellum > for schematics. Likewise. > My first programmable logic was PALs and I used PALASM > for that, then moved on to Abel, CUPL, Started with 82S153s and 82S105s, where I had to mark up the map and send it off to Signetics for programming. When we got a programmer, but I had to use freeze spray while the parts were programming. I'd forgotten CUPL -- what a great language (compared with PALASM or even Abel). I used to work across the street from the guy who wrote it, so I would just walk across the road for tech support. > Personally I feel I have benefited by learning logic > design before learning HDL's. Likewise. I use Aldec for VHDL sim. I couldn't get them to cut me a deal on Verilog, so I ended up using the free Altera ModelSim. If I get more Verilog gigs I'll probably spring for Aldec.Article: 150699
> >So -- where are you from, and what HDL do you use? Have you seen >patterns of language use in your area change in the last decade or so? > Started my career in CO. Started with Verilog but also used VHDL (company PQR vs XYZ). I am fluent with Verilog and VHDL but have a slight preference for Verilog, simply because it is the language I first used and it's little ingrained. I am now in MN, my current and previous projects are in Verilog. I would also state that I use MyHDL as frequently as possible for IP blocks if the boss(es) allow. I would like to think I would be agnostic to HDL language selection on a particular project. I might be more opinionated on tools. Chris Felton --------------------------------------- Posted through http://www.FPGARelated.com
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