Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
> >So: if the design cycle that I'm quoting for ASICs sounds accurate to >you (I'm just forwarding a long-ago conversation), and the design cycle >for FPGA work makes you think "ewww!", then FPGA work isn't for you. If, >on the other hand, you get no joy from spending 90% of your time >verifying before you actually get to see your work working -- maybe >you'll like FPGA work. > This advice is a couple of years old and outdated. Todays larger fpgas are forcing fpgas designers to adopt asic design methods if you ever hope to get your design working. The best plan combines the two so that you create a robust simulation suite to ensure that it should work and use real hardware to run the bench tests needed for the corner cases. Two minutes on a fpga breadboard tests as much as a month of simulation. Got a repeatable hardware failure that your sims say should work? Use scan assisted debug. Run the hardware and freeze the state sometime before the error appears. Then use the scan chain to extract the state of all the flip flops and load that into your simulation. Run it to see if it fails. You can use a binary search to narrow it down to the exact clock cycle where the hardware gets a bad state. John Eaton --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153001
In article <oP6dneyod_9EnCHTnZ2dnUVZ_vKdnZ2d@web-ster.com>, Tim Wescott <tim@seemywebsite.com> wrote: >On Wed, 09 Nov 2011 20:54:19 -0800, googler wrote: > >> Hi folks, >> >> I am an ASIC design engineer with over 6 years experience. My experience >> in ASIC design spans across microarchitecture, RTL coding, synthesis, >> timing closure and verification. Is it advisable for me if I change to a >> FPGA design job? I mean, what are the pros and cons? I do not have much >> experience in FPGA other than school projects. How much learning is >> involved? Will it be difficult to switch back to ASIC design position in >> the future if I move to a FPGA job? Do FPGA design involve less work and >> stress than ASIC? Please provide your opinion, experience or any other >> comment. > >I knew a guy who had done really good FPGA designs for years, and for >years had yearned to do ASIC design with the "big boys". He lasted a >year or two -- not because he wasn't up to the job, but because he hadn't >realized the difference in the design cycle between ASIC and FPGA, and he >vastly preferred FPGA design. <snip> I made the jump to FPGAs about 6 years ago, after doing ASICs for around 11 years. I prefer FPGAs for many of the reasons that Tim mentioned - you get to actually touch and fiddle with the hardware - often! In all those year of ASIC design it was just rush to tapeout, the on to the next rush. Others handled the actual bringup. Not satisfying. I never touched the finished products. Lab debug is very satisfying (well can be frustrating too!). And a good skill to have. You gotta want to do it though. From a design point of view, yeah FPGA's are different than ASICs. But they're 90% the same. You can pickup the 10% on the job. Plus, as others in the thread have pointed out, FPGAs because of their size, are starting to need some of the same flows that ASICs need. So your experience there is a benefit. Stick next to an experienced FPGA guy. You'll learn from him why 'we do things this way in FPGAs'. He'll learn from you some of the ASIC methodologies that can be applied to his flows. Less Work / Less Stress? That's a more company culture question IMHO, and unrelated. Going back to ASIC after years in FPGA - well, I'm not interested. But I think it'd be doable too. My 2 cents... --MarkArticle: 153002
Mark Curry <gtwrek@sonic.net> wrote: (snip, someone wrote) >>> I am an ASIC design engineer with over 6 years experience. (snip) >>I knew a guy who had done really good FPGA designs for years, and for >>years had yearned to do ASIC design with the "big boys". He lasted a >>year or two -- not because he wasn't up to the job, but because he hadn't >>realized the difference in the design cycle between ASIC and FPGA, and he >>vastly preferred FPGA design. > I made the jump to FPGAs about 6 years ago, after doing ASICs for > around 11 years. I prefer FPGAs for many of the reasons that > Tim mentioned - you get to actually touch and fiddle with the > hardware - often! In all those year of ASIC design it was just > rush to tapeout, the on to the next rush. This reminds me, some years ago I was told (in one of these newsgroups) that ASIC designers prefered verilog and FPGA people liked VHDL. It seems that the FPGA tools now support both equally, so maybe things have changed. Without starting a flame war, is it still true that verilog is more popular in the ASIC world, and VHDL in the FPGA world? -- glenArticle: 153003
On Nov 10, 12:31=A0pm, gtw...@sonic.net (Mark Curry) wrote: > > I made the jump to FPGAs about 6 years ago, after doing ASICs for around = 11 years. > I prefer FPGAs for many of the reasons that Tim mentioned - you get > to actually touch and fiddle with the hardware - often! =A0In all those > year of ASIC design it was just rush to tapeout, the on to the next rush. > Others handled the actual bringup. =A0Not satisfying. =A0I never touched > the finished products. Thanks for your comments! > > Lab debug is very satisfying (well can be frustrating too!). =A0And a goo= d > skill to have. =A0You gotta want to do it though. Yes, I agree. > > From a design point of view, yeah FPGA's are different than ASICs. =A0But > they're 90% the same. =A0You can pickup the 10% on the job. =A0Plus, > as others in the thread have pointed out, FPGAs because of their size, ar= e > starting to need some of the same flows that ASICs need. =A0So your > experience there is a benefit. But most of the tools are different, aren't they? I understand that the essential/basic knowledge applies to both more or less the same, but learning different tools can take time sometimes. Anyway, my bigger concern in switching to FPGA is - AFAIK the scope of FPGA designs are smaller than ASIC and many of the stages/features that exit in ASIC do not apply to FPGA (or are significantly simpler). Is that right? For example, I heard that FPGAs cannot support clock gating, whereas for ASICs, it is almost essential these days. Other examples may be scan, formal verification, etc So my point is, if I am not using some of the knowledges/skills on a daily basis (because they do not apply to FPGA), I may lose them. I don't know how much of this concern is actually true, since I have very limited FPGA experience. > > Stick next to an experienced FPGA guy. > You'll learn from him why 'we do things this way in FPGAs'. > > He'll learn from you some of the ASIC methodologies that can be applied > to his flows. > > Less Work / Less Stress? =A0That's a more company culture question IMHO, = and > unrelated. You mention "rushing to tapeouts" with ASICs. That's exactly how my experience have been with ASICs too. It can get very stressful these days especially with such a huge competition among companies for time- to-market. That's why I asked if working in FPGAs is better in this respect (although I understand the company culture does have a big part to play). > > Going back to ASIC after years in FPGA - well, I'm not interested. =A0But= I think > it'd be doable too. > > My 2 cents... > > --Mark- Hide quoted text - > > - Show quoted text -Article: 153004
In article <j9hed3$8m4$1@speranza.aioe.org>, glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: >Mark Curry <gtwrek@sonic.net> wrote: > >(snip, someone wrote) >>>> I am an ASIC design engineer with over 6 years experience. > >(snip) >>>I knew a guy who had done really good FPGA designs for years, and for >>>years had yearned to do ASIC design with the "big boys". He lasted a >>>year or two -- not because he wasn't up to the job, but because he hadn't >>>realized the difference in the design cycle between ASIC and FPGA, and he >>>vastly preferred FPGA design. > >> I made the jump to FPGAs about 6 years ago, after doing ASICs for >> around 11 years. I prefer FPGAs for many of the reasons that >> Tim mentioned - you get to actually touch and fiddle with the >> hardware - often! In all those year of ASIC design it was just >> rush to tapeout, the on to the next rush. > >This reminds me, some years ago I was told (in one of these >newsgroups) that ASIC designers prefered verilog and FPGA people >liked VHDL. It seems that the FPGA tools now support both equally, >so maybe things have changed. Without starting a flame war, >is it still true that verilog is more popular in the ASIC world, >and VHDL in the FPGA world? I don't really know what's more popular. I've worked at two places with FPGAs. Both were verilog houses. Before that, two ASIC houses - both verilog. But at all we had to deal with VHDL too. In one way or another, we were forced to mixed language flows. IP from one place or another came in the other language. IMHO, one will have his or her prefered language, but you'd better be able to do the basics in the other too. --MarkArticle: 153005
googler <pinaki_m77@yahoo.com> wrote: (snip) > But most of the tools are different, aren't they? I understand that > the essential/basic knowledge applies to both more or less the same, > but learning different tools can take time sometimes. Anyway, my > bigger concern in switching to FPGA is - AFAIK the scope of FPGA > designs are smaller than ASIC FPGAs are getting big amazingly fast. (Though the really big ones are expensive.) As far as I know, they are big enough that you still need to "think big." > and many of the stages/features that > exit in ASIC do not apply to FPGA (or are significantly simpler). Is > that right? For example, I heard that FPGAs cannot support clock > gating, whereas for ASICs, it is almost essential these days. As far as I know, you can do it for very slow clocks. But it is usual to have FF's with a clock enable. That changes the design a little bit, but, it seems to be, not a lot. > Other examples may be scan, formal verification, etc So my point > is, if I am not using some of the knowledges/skills on a daily > basis (because they do not apply to FPGA), I may lose them. Maybe, but you would probably get them back pretty fast if needed. Like the old story about never forgetting about how to ride a bicycle. > I don't know how much of this concern is actually true, > since I have very limited FPGA experience. It seems to me that the big difference is in the cost of a redo. That shifts the testing and verification needed. You still have to design to avoid rare timing errors, though, but many more obvious failures can be found in actual testing instead of verification. >> Stick next to an experienced FPGA guy. >> You'll learn from him why 'we do things this way in FPGAs'. -- glenArticle: 153006
In article <770abbbe-86b6-4d1e-8eb5-4f47fac0679f@h31g2000prl.googlegroups.com>, googler <pinaki_m77@yahoo.com> wrote: ><gtwrek@sonic.net wrote> >> >> From a design point of view, yeah FPGA's are different than ASICs. But >> they're 90% the same. You can pickup the 10% on the job. Plus, >> as others in the thread have pointed out, FPGAs because of their size, are >> starting to need some of the same flows that ASICs need. So your >> experience there is a benefit. > >But most of the tools are different, aren't they? I understand that >the essential/basic knowledge applies to both more or less the same, >but learning different tools can take time sometimes. Anyway, my >bigger concern in switching to FPGA is - AFAIK the scope of FPGA >designs are smaller than ASIC and many of the stages/features that >exit in ASIC do not apply to FPGA (or are significantly simpler). Is >that right? For example, I heard that FPGAs cannot support clock >gating, whereas for ASICs, it is almost essential these days. Other >examples may be scan, formal verification, etc So my point is, if I am >not using some of the knowledges/skills on a daily basis (because they >do not apply to FPGA), I may lose them. I don't know how much of this >concern is actually true, since I have very limited FPGA experience. Tools are just tools. From 10,000 ft they look the same. A tool takes your RTL and synthesizes it. Another maps to the technology. Another does Place and Route. Sure there's details, but that's constantly changing for all of them. As long as you understand the "goes intos" and the "goes outtas" you're most of the way there. As to scope issues of FPGAs vs ASICs. Well, as I said, I left ASICs around 6 years ago. One of the current FPGA I'm working on is getting pretty darned close to the abilities of that last ASIC I worked on. The FPGA's today are big - you're "big ASIC" experience is a benefit. (What's the current marketing term for "big ASIC" anyway? - "SOC" seems to be falling out) >> Less Work / Less Stress? That's a more company culture question IMHO, and >> unrelated. > >You mention "rushing to tapeouts" with ASICs. That's exactly how my >experience have been with ASICs too. It can get very stressful these >days especially with such a huge competition among companies for time- >to-market. That's why I asked if working in FPGAs is better in this >respect (although I understand the company culture does have a big >part to play). It can get quite stressful when that end-of-quarter demo to the VP isn't working at the 11th hour. Is the problem software, firmware, hardware, mechanical, etc., etc. To steal an overused line, "Meet the new boss, same as the old boss..." I find that just about anywhere I've worked, there's peaks and valleys of work-load, stress, and accomplishments. Deal with them how you can. --MarkArticle: 153007
"jt_eaton" <z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >> >>So: if the design cycle that I'm quoting for ASICs sounds accurate to >>you (I'm just forwarding a long-ago conversation), and the design cycle >>for FPGA work makes you think "ewww!", then FPGA work isn't for you. If, > >>on the other hand, you get no joy from spending 90% of your time >>verifying before you actually get to see your work working -- maybe >>you'll like FPGA work. >> > >This advice is a couple of years old and outdated. > >Todays larger fpgas are forcing fpgas designers to adopt asic design >methods >if you ever hope to get your design working. The best plan combines the >two >so that you create a robust simulation suite to ensure that it should work >and use real hardware to run the bench tests needed for the corner cases. >Two minutes on a fpga breadboard tests as much as a month of simulation. IMHO it depends on the complexity of what you are doing. If you can divide a design in many small pieces then you can test each piece and put it together later on. I've worked on mid range FPGA designs which where a piece of cake and small CPLD designs which where hard to get right. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 153008
On 11/10/2011 20:33, jt_eaton wrote: > This advice is a couple of years old and outdated. Depends. >From the point of view of an (or better: the only) FPGA Engineer in a 600+ employees measurement instrument company, Tim's description sounds pretty familiar to me. The big thing that has changed in the last 10 years: While with a Spartan XL I really had trouble fitting my few stepper drivers, PWMs and preripheral interfacing in, With Spartan 3 (which we still use for most products) I drag more and more functionality from firmware down into the FPGA to make use of all the logic cells I get after picking the smallest device with sufficient IO count. So, your mileage may vary with the team, project and device size. - Philip -- Democracy: Three wolves and a sheep voting on what's for dinner.Article: 153009
The Main differences between asics and fpgas:
1) Test
Making an asic design scan testable affects how you do all your
asynchronous logic. Fpgas come pretested and you don't need to do a
parts test with your logic.
2) Clocking
Asics can easily have 20-30 clock domains and you have the tools to
manage
them. Fpgas have a finite number of global clock routing resources and
you
really want to keep your design under that number.
Both asics and fpgas work with clock enables and you should use them as
much as you can. Fpgas have clock enabled flops and asics will use
power
compiler to turn them into separate clock domains.
3) Flexibility
Asics can do anything. Want a and/or gate or invertor feeding your
flop?
An asic can do it. So can a fpga but it will cost you 1 LUT. Fpga
designs
work best if you have a consistent amount of logic between each stage.
To
much and you have to use 2 LUT's and the speed goes down. To little and
you have unused resources and your gate count goes down.
4) Performance
Asics will always win. Hard coded paths beat switched paths any day. We
would use fpgas to prototype all of our asics and we:
a) Target the system clock to well under the asic process maximums
b) Design the prototype for 1/4 the actual system clock.
If you can show that your embedded system can perform each task @ 1/4
clock speed then you buy yourself a nice safety margin for the product.
John Eaton
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 153010Michael S wrote: > On Nov 7, 12:43=A0pm, "zsolt.garamvolgyi" <zsolt.garamvol...@gmail.com> > wrote: > > On Nov 6, 1:10=A0pm, Michael S <already5cho...@yahoo.com> wrote: > > > On Nov 4, 1:15=A0pm, "zsolt.garamvolgyi" <zsolt.garamvol...@gmail.com= > > > > wrote: > > > > > > Hi, > > > > > > I'm looking for an FPGA-based PCI Express development board which i= s > > > > capable of transmitting data at about 1.4 GByte/sec to the host > > > > computer (PCIe Gen1 x8 or Gen2 x4/x8). >>>>> [snip] > > > > > In our experience Altera's hard IP PCIe core present in StratixIV GX > > > and in ArriaII GX is broken rather badly. > > > That is, you can find certain hosts where it appears to work most of > > > the time, but that's exception rather than rule. > > > Soft IP core in these devices works relatively better, but still badl= y > > > violates power up timing specifications defined in the PCIe standard, > > > so we generally prefer to plug it into slots that support hot plug, > > > since such slots are typically more tolerant to this sort of timing > > > violations. Unfortunately for you, you want x8 slot. x8 slots with > > > support for hot plug are significantly rarer than x4/x1 slots. > > > > This is really interesting. Can you tell me, exactly which hosts (if > > any) did you manage to get the hard IP core work with correctly? > > > I did a little more research. The situation with Altera Hard IP is not as hopeless as I presented in my previous posts. In Quartus 10.1 (and hopefully in 11, but I didn't test) Altera seems to implement a workarounds for majority of the Startix IV and Arria II hard IP silicon problems. Powerup timing is still non standard, and I'd guess, not much could be done about it, but the rest works o.k. At least so far we saw no problems with Terrasic DE4 on Intel X58-based PC. Our problems with Hard IP on Arria2-GX could be traced back to combination of bug in Quartus 9.1. and lack of attention on part of our board developer. Hard IP in Arria2 GX requires certain fixed assignment of the PCIe lanes to FPGA GX transceivers. However, Quartus 9.1 does not properly detects incorrect assignments. We were just unlucky to fall into this pitfall. You can be 100% sure that nothing like that would happen if you buy development board from Altera or Terrasic. Back to recommended host platform. I think, among single-CPU platforms, Intel X58 (the platform used with Core-i7 9xx series of CPUs) is still the safest. Of course, it is not as popular or easy-to-find as platforms based on Intel LGA 1156 or LGA 1155 processors, but it does feature hot plug on all PCIe slots. As a consolation for higher price and lower price/performance, X58 gives you the highest memory bandwidth and the highest memory capacity. For comparison, typical LGA 1156- based boards have just one hot-plug x4 Gen1 slot. All x8/x16 and/or Gen2 slots have no support for hot plug, so it's far more likely that non-standard powerup timing of Altera cores (both soft and hard IP variants) will cause problems, even in "cold plug" scenarios. I have no 1st hand experience with Altera PCIe solutions on the newest Intel platform, i.e. LGA 1155, a.k.a. i7 Gen2, a.k.a. Sandy Bridge. I am afraid that it is similar to LGA 1156 and is similarly unforgiving to timing violations. But test it yourself - this one is easiest to get and even if you find that it does not satisfy you as PCIe host, at least you will enjoy ass- kicking development machine ;-) As to dual-CPU Intel platforms, IIRC, on dual-CPU chipsets all PCIe slots support hot plug, so, in theory everything should work. However, except for old and obsolete Blackford (5000 series), I didn't try it myself.Article: 153011
We have some new, and some not so new, offerings this week. The first out is a new member of the Merrick family. Merrick3 has 26 FPGAs and if that's not enough we can stack these boards. Details on http://enterpoint.co.uk/products/asic-development-high-performance-computing/merrick-3/ . For those of you that like the high I/O availability of our Raggedstone family we have gone and cut a new derivative of Raggedstone2 to offer more. Lamachan2 offers 266 I/O in our simple DIL Header format and allows you to do some really daft combinations of interfaces and functions in a true lego like approach. We will be showing an example this week supporting 256 ADC channels at 12bit 200 KHz sampling. Details http://enterpoint.co.uk/products/lamachan-2/ . And finally we have pushed out our Broaddown3 concept into proper manufacture. it's been reworked a lot since we talked about the initial concept but we have retained the 5 Virtex-6 FPGAs as part of it. There will be a Webpack compatible version of this board for those of you who don't like to pay for tools. Details on http://enterpoint.co.uk/products/broaddown-3/. John Adair Enterpoint Ltd.Article: 153012
As to dual-CPU Intel platforms, IIRC, on dual-CPU chipsets all PCIe slots support hot plug, so, in theory everything should work. However, except for old and obsolete Blackford (5000 series), I didn't try it myself. Hello, maybe anyone can confirm that? What's the scenario of fpga restart then? Unload the module, reflash the binary and load module again? What about development on Windows then? Regards, Tomas D.Article: 153013
John Adair <g1@enterpoint.co.uk> wrote: > We have some new, and some not so new, offerings this week. The first > out is a new member of the Merrick family. Merrick3 has 26 FPGAs and > if that's not enough we can stack these boards. Details on > http://enterpoint.co.uk/products/asic-development-high-performance-computing/merrick-3/ > . > > For those of you that like the high I/O availability of our > Raggedstone family we have gone and cut a new derivative of > Raggedstone2 to offer more. Lamachan2 offers 266 I/O in our simple DIL > Header format and allows you to do some really daft combinations of > interfaces and functions in a true lego like approach. We will be > showing an example this week supporting 256 ADC channels at 12bit 200 > KHz sampling. Details http://enterpoint.co.uk/products/lamachan-2/ . > > And finally we have pushed out our Broaddown3 concept into proper > manufacture. it's been reworked a lot since we talked about the > initial concept but we have retained the 5 Virtex-6 FPGAs as part of > it. There will be a Webpack compatible version of this board for those > of you who don't like to pay for tools. Details on > http://enterpoint.co.uk/products/broaddown-3/. The FPGAs on this picture http://enterpoint.co.uk/wp-content/uploads/2011/10/BROADDOWN3.jpg look like a bad joke. IMO such an ugly photoshop work unnecessarily sheds grim light on an otherwise interesting product... MarkoArticle: 153014
Hi, I am looking for a decent PCIe (Gen1 & Gen2) based FPGA board with preferably 2 Xilinx Virtex 5 FPGAs on it. A 2GB DDR2 SODIMM and minimum 256 MB RAM is preferred. Other onboard periphals may include gigbit ethernet and a USB 2.0. FPGAs must be Virtex-5 LX330T or higher capacity. Other than that nothing much is actually required. I have been searching for such a board but most of them are packed with other peripherals making them too costly. I basically need 2 (or more) V5 LX330T FPGAs on a board with PCIe (x8) with 2GB DDR2 and 256 or higher RAM. Any suggestions please........Article: 153015
Actually it's not a photoshop but cardboard Virtex, and a couple of other cardboard semi chips, mounted on a real board and real passives. That particular board is only for the show stand and we don't take anything that costly with real chips that we let people can maul on stand. We do have a real one being played with back at base 5000-6000 miles away and that being careful brought up into full functionality. For anyone coming to SC11 the Merrick3 and Lamachan2 will be real boards and running real FPGA designs in the display part of the stand. I don't think we did badly building on our line last week for the first time 3 new complex designs and bringing 2 of they fully working in less than 3 days to the US and especially given the extreme design cycle my team worked on under on the Merrick3 and Lamachan2 developments. 10 weeks ago Merrick3 and Lamachan2 were merely a concept I bounced around the team meeting when we decided to show at SC11. John Adair Enterpoint Ltd. On Nov 14, 11:48=A0am, Marko Zec <z...@fer.hr> wrote: > John Adair <g...@enterpoint.co.uk> wrote: > > We have some new, and some not so new, offerings this week. The first > > out is a new member of the Merrick family. Merrick3 has 26 FPGAs and > > if that's not enough we can stack these boards. Details on > >http://enterpoint.co.uk/products/asic-development-high-performance-co... > > . > > > For those of you that like the high I/O availability of our > > Raggedstone family we have gone and cut a new derivative of > > Raggedstone2 to offer more. Lamachan2 offers 266 I/O in our simple DIL > > Header format and allows you to do some really daft combinations of > > interfaces and functions in a true lego like approach. We will be > > showing an example this week supporting 256 ADC channels at 12bit 200 > > KHz sampling. Detailshttp://enterpoint.co.uk/products/lamachan-2/. > > > And finally we have pushed out our Broaddown3 concept into proper > > manufacture. it's been reworked a lot since we talked about the > > initial concept but we have retained the 5 Virtex-6 FPGAs as part of > > it. There will be a Webpack compatible version of this board for those > > of you who don't like to pay for tools. Details on > >http://enterpoint.co.uk/products/broaddown-3/. > > The FPGAs on this picture > > http://enterpoint.co.uk/wp-content/uploads/2011/10/BROADDOWN3.jpg > > look like a bad joke. =A0IMO such an ugly photoshop work unnecessarily > sheds grim light on an otherwise interesting product... > > MarkoArticle: 153016
John Adair <g1@enterpoint.co.uk> wrote: >first time 3 new complex designs and bringing 2 of they fully working >in less than 3 days to the US and especially given the extreme design >cycle my team worked on under on the Merrick3 and Lamachan2 Be a good boss and make them see some rewards around Christmas :-) -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 153017
On Nov 14, 10:42=A0am, "scrts" <hid...@email.com> wrote: >> As to dual-CPU Intel platforms, IIRC, on dual-CPU chipsets all PCIe >> slots support hot plug, so, in theory everything should work. However, >> except for old and obsolete Blackford (5000 series), I didn't try it >> myself. > > Hello, > maybe anyone can confirm that? Confirm what? > > What's the scenario of fpga restart then? > Unload the module, reflash the binary and load module again? What about > development on Windows then? > > Regards, > Tomas D. On Windows it is the same. Assuming you have plug&play driver (which, for PCIe, is the only reasonable option anyway) and assuming that your device is not a boot device and not a main display card: 1) disable your device in Device Manager; 2) reload FPGA; 3) re-enable device in Device Manager. Or, if PCI Vendor/Device ID of your new design differs from the previous one, you instruct device manager to scan for new devices between steps 2 and 3.Article: 153018
"Michael S" <already5chosen@yahoo.com> wrote in message news:f6ea35a5-8957-4b6e-98e4-fb70d273a3bb@v5g2000yqn.googlegroups.com... On Nov 14, 10:42 am, "scrts" <hid...@email.com> wrote: >> As to dual-CPU Intel platforms, IIRC, on dual-CPU chipsets all PCIe >> slots support hot plug, so, in theory everything should work. However, >> except for old and obsolete Blackford (5000 series), I didn't try it >> myself. > > Hello, > maybe anyone can confirm that? >Confirm what? Dual-CPU chipsets really support PCI-e hotplug? In this case, all the current chipset systems should support that feature. The part about image reflash is clear now, thanks. Regards, Tomas D.Article: 153019
On Nov 15, 9:05=A0am, "scrts" <hid...@email.com> wrote: > "Michael S" <already5cho...@yahoo.com> wrote in message > > news:f6ea35a5-8957-4b6e-98e4-fb70d273a3bb@v5g2000yqn.googlegroups.com... > On Nov 14, 10:42 am, "scrts" <hid...@email.com> wrote: > > >> As to dual-CPU Intel platforms, IIRC, on dual-CPU chipsets all PCIe > >> slots support hot plug, so, in theory everything should work. However, > >> except for old and obsolete Blackford (5000 series), I didn't try it > >> myself. > > > Hello, > > maybe anyone can confirm that? > >Confirm what? > > Dual-CPU chipsets really support PCI-e hotplug? In this case, all the > current chipset systems should support that feature. > What you mean by "all the current chipset systems"? >99% of the desktops sold are single CPU, not dual. Or do you consider dual-cores as "dual-CPU"? No, that's not what I meant. When I said "dual-CPU" I meant dual-socket. Like Dell Precision T5500 or HP Z600 or majority of servers. However, those are not the cheapest machines around. From the cheaper things I recommend models based on Intel's relatively old X58 chipset, like, for example, any of ASUS P6T series of motherboards or Supermicro C7X58 motherboard. > The part about image reflash is clear now, thanks. > > Regards, > Tomas D.Article: 153020
Hello, I have used the Xilinx LogiCore Integrated Block for PCI Expres several times in the past. On those occasions I have hacked into the autogenerated example design to bring a standard parallel interface up to the top level for access to registers and block ram. This work has always been for prototyping and was not really production firmware. Working this way the PCI Express performance is really low because the Logicore IP does not support burst transfers or DMA. The software engineer hacks the linux driver to prevent any PCI Express accesses of greater than one word so we don't get bus errors. I just genenerated a version 2.4 AXI4 compatible PCIe core for V6 using ISE 13.3 and I see the design still supports only single word accesses. Now we are dong a production design using PCIe and I would like to get the full performance of the interface. In particular I must support burst transfers. Ideally I will also provide DMA logic. Can anyone advise me where to start in order to get where I want to go? Am I starting too low using the Xilinx Logicore design? Does Xilinx provide a better core or reference design with burst transfer and DMA? Any advice is greatly appreciated. PedroArticle: 153021
On Nov 9, 10:54=A0pm, googler <pinaki_...@yahoo.com> wrote: > Hi folks, > > I am an ASIC design engineer with over 6 years experience. My > experience in ASIC design spans across microarchitecture, RTL coding, > synthesis, timing closure and verification. Is it advisable for me if > I change to a FPGA design job? I mean, what are the pros and cons? I > do not have much experience in FPGA other than school projects. How > much learning is involved? Will it be difficult to switch back to ASIC > design position in the future if I move to a FPGA job? Do FPGA design > involve less work and stress than ASIC? Please provide your opinion, > experience or any other comment. > > Thanks! I've done both FPGA and ASIC design (front-end and back-end). I prefer FPGA design because I can spend a greater part of my time doing the interesting architecture and design work. During ASIC development, so much time is spent slogging through the less interesting tasks of corner-case verification, DFT, DFM, DRC, RC back-annotation, etc. Darol KlawetterArticle: 153022
What you mean by "all the current chipset systems"? >99% of the desktops sold are single CPU, not dual. Or do you consider dual-cores as "dual-CPU"? No, that's not what I meant. When I said "dual-CPU" I meant dual-socket. My bad then, I thought You meant one socket multi-core CPUs. From the cheaper things I recommend models based on Intel's relatively old X58 chipset, like, for example, any of ASUS P6T series of motherboards or Supermicro C7X58 motherboard. So what's the procedure on single socket CPU boards? Turn off PC, load config to FPGA and start the machine again? I wonder if PCI-e standard defines PCI-e hotplug or not. Regards, Tomas D.Article: 153023
> This reminds me, some years ago I was told (in one of these > newsgroups) that ASIC designers prefered verilog and FPGA people > liked VHDL. =A0It seems that the FPGA tools now support both equally, > so maybe things have changed. =A0Without starting a flame war, > is it still true that verilog is more popular in the ASIC world, > and VHDL in the FPGA world? In my experience, ASICs are 95% of the time in Verilog. FPGAs 50/50. Also starting to see people use SystemVerilog for ASIC design as well as verification. JonArticle: 153024
Hello all. I am trying to migrate from Xilinx ISE to Actel Libero. I created a new project in Libero and copied the *.vhd files from the ISE project. Then I replaced all the Xilinx FIFOs and CLKDLLs with the equivalent Libero specific cores. When I tried to synthesize the project using Synplify Pro, I obtained the following error message. "Can't open input file C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\xilinx\unisim.vhd" I am not using any Unisim components in the Actel Libero project. Then what cause can result in this error. Thank you. --------------------------------------- Posted through http://www.FPGARelated.com
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z