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On Nov 28, 5:04=A0am, Giuseppe Marullo <giuseppe.marullonos...@iname.com> wrote: > Hi, > I see on Ebay cheap USB Cables(40-60USD) that claims to be compatible > with the Xilinx ones. I don't understand wich one, if any, they emulate > (DLC9G). > > Do they work? Are they supported on latest webise under Win7 64bit? Wich > cable they are compatible with? They are clones of Xilinx USB-JTAG cables. The one I've had a look at was a clone of the DLC9G. The circuitry is a 100% clone, so the XIlinx SW cannot distinguish it from a real DLC9G. This means that it is 100% compatible with the Xilinx SW, including accepting firmware updates that Xilinx release from time to time. Unfortunately the build quality is much lower than the Xilinx original cables - the unit I examined worked just like an original until the USB A socket in it broke after a few cable insertion / removal cycles. This was repairable, but an annoying waste of time. Your mileage may vary. Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au $49 Spartan 6 board with 32MB DDR DRAM ? http://www.sioi.com.au/shop/product_info.php/products_id/47Article: 153076
> They are clones of Xilinx USB-JTAG cables. The one I've had a look at > was a clone of the DLC9G. Stephen, thanks for your answer. So they can be a [cheap] alternative, now the last question: what's up about the 6 vs 7 pin debate? Is it really needed? I see also a breakout board, does it make a difference? Thanks in advance. Giuseppe MarulloArticle: 153077
>On Nov 28, 5:04=A0am, Giuseppe Marullo ><giuseppe.marullonos...@iname.com> wrote: >They are clones of Xilinx USB-JTAG cables. The one I've had a look at >was a clone of the DLC9G. >The circuitry is a 100% clone, so the XIlinx SW cannot distinguish it >from a real DLC9G. This means that it is 100% compatible with the >Xilinx SW, including accepting firmware updates that Xilinx release >from time to time. I haven't checked but I am pretty sure that the Xilinx download agreement doesn't allow you to do this. After all they do say that you cannot use their software to generate bits for anything other than a Xilinx part it would be out of character if they let you use their firmware upgrades for a competitors product. BTW: where did they get the bits that are shipped with their probe? I'm sure they put together a crack reverse engineering team that was so good that it came out to be bit for bit identical to a rom dump of the xilinx product. This isn't a technical question. It is a personal morality one. John Eaton --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153078
> This isn't a technical question. It is a personal morality one. John, why would it be a personal morality one? >software to generate bits for anything other than a Xilinx part it >would be The adaper does contain a Xilinx part at least (A spartan 3A if I am not mistaken), AFAIK. >out of character if they let you use their firmware upgrades for a >competitors product Given that their cable is 6x the price of the boards I would like to use, they can be smart and allow this. I don't pay 300USD for their cable: stil remain a user of their chips. I want the original one if I need better quality and support: I get their one and pay for a better product. Anyway, I am not a layer but as long it is your, you can force/crack/destroy it once paid it full. *No*DCMA*yet*here.* Giuseppe Marullo PS: first time I got caught by FPGA police. I was thinking it was peculiar to ham radio, LOLArticle: 153079
I use Altera USB Blaster clone from eBay for ~10USD. Works perfectly: drivers are exact the same as for original device, programming speed is also the same, but the best thing is that the clone is nearly 3-4 times smaller and has mini-USB connector. "Giuseppe Marullo" <giuseppe.marullonospam@iname.com> wrote in message news:javm1e$nm0$1@speranza.aioe.org... > >> This isn't a technical question. It is a personal morality one. > John, why would it be a personal morality one? > > >software to generate bits for anything other than a Xilinx part it would > >be > The adaper does contain a Xilinx part at least (A spartan 3A if I am not > mistaken), AFAIK. > > >out of character if they let you use their firmware upgrades for a > >competitors product > Given that their cable is 6x the price of the boards I would like to use, > they can be smart and allow this. > I don't pay 300USD for their cable: stil remain a user of their chips. > > I want the original one if I need better quality and support: I get their > one and pay for a better product. > > Anyway, I am not a layer but as long it is your, you can > force/crack/destroy it once paid it full. *No*DCMA*yet*here.* > > Giuseppe Marullo > > PS: first time I got caught by FPGA police. I was thinking it was peculiar > to ham radio, LOLArticle: 153080
Am 24.11.2011 12:33, schrieb Tim: > These prices come up on Avnet Express. I searched via www.findchips.com. > > Low end: XC7V2000T-1FH1761C - $29897.06 > High end: XC7V2000T-G2FLG1925E - $67150.00 > > Does that make the the XC7V2000 the most expensive "standard production" > chip in the history of the galaxy? > > Of course, it's probably pretty cheap in terms of transistors per > dollar. Heroic engineering, but I'm glad I am not a stockholder. Think of how much money you have to invest, in order to fill 2.4 million LUTs with useful logic. Then the price appears in another light. MatthiasArticle: 153081
On 28 Nov., 12:24, Matthias Alles
<matthiasPuTDoTHerEal...@creonic.com> wrote:
> Am 24.11.2011 12:33, schrieb Tim:
>
> > These prices come up on Avnet Express. I searched viawww.findchips.com.
>
> > Low end: XC7V2000T-1FH1761C =A0- =A0$29897.06
> > High end: XC7V2000T-G2FLG1925E =A0- =A0$67150.00
>
> > Does that make the the XC7V2000 the most expensive "standard production=
"
> > chip in the history of the galaxy?
>
> > Of course, it's probably pretty cheap in terms of transistors per
> > dollar. Heroic engineering, but I'm glad I am not a stockholder.
>
> Think of how much money you have to invest, in order to fill 2.4 million
> LUTs with useful logic. Then the price appears in another light.
>
> Matthias
You design just once, but maybe want to sell many units... But at
least the prices are precisly calculated, look at the 6 cents of the
"low-end" part.
But seriously: When you look what you can do with a 40kLUTs part, then
designs that large are either bad/inefficient, brute-force-approaches
("do the same thing 100 times") or incredible huge projects. So I
guess, the real useful application is ASIC-prototyping, so you are
right...
Thomas
Article: 153082On 11/28/2011 12:13 PM, scrts wrote: > I use Altera USB Blaster clone from eBay for ~10USD. Works perfectly: Thanks, could you kindly post an example of what I need to search? Giuseppe MarulloArticle: 153083
> Thanks, could you kindly post an example of what I need to search? ebay.com -> search "altera usb" E.g. http://www.ebay.com/itm/NEW-USB-BLASTER-CABLE-CPLD-FPGA-JTAG-Altera-Programmer-/110767654671?pt=LH_DefaultDomain_0&hash=item19ca44470fArticle: 153084
On 11/28/2011 4:05 PM, scrts wrote: >> Thanks, could you kindly post an example of what I need to search? > > ebay.com -> search "altera usb" > E.g. > http://www.ebay.com/itm/NEW-USB-BLASTER-CABLE-CPLD-FPGA-JTAG-Altera-Programmer-/110767654671?pt=LH_DefaultDomain_0&hash=item19ca44470f > > Sorry to ask, but is this supposed to work for Xilinx too? Too good to be true.Article: 153085
> >> This isn't a technical question. It is a personal morality one. >John, why would it be a personal morality one? > Sometimes the reason that they can offer their product at such a discount is because instead of paying a design team to create the product they simply copied straight from the original manufacturer. This is piracy and is nothing more than stealing. I can get you a great price on an iPad if your willing to ignore the fact that it is stolen and I am fencing it for pennies on the dollar. Now there is a lot of overhead built into the prices from a large company. It is quite possible to reverse engineer and create a "clean room" design that functions the same but you can build and sell for a lot less money. The entire ibm pc-clone market did this. I would want to see who designed this probe before buying. The guys that can do that stuff like to brag about it. It is also possible that Xilinx never designed that probe and simply went to an OEM to rebrand one of their products. In that case you could get a better deal if you go straight to the source. Either way I would want to know something about the manufacturer. John Eaton --------------------------------------- Posted through http://www.FPGARelated.comArticle: 153086
I could use a FPGA (and development board) with a way to connect to a desktop. But any of those is not in VHDL. How do use a FPGA with serial port or whatever bus or interface. By the way, I need some ram too, 1000 bytes or less. How do use that.Article: 153087
Here is a $50 alternative that is supported by Xilinx. Support for this cable is built into ISE 13.2 and later, and previous versions by installing a plugin. https://www.em.avnet.com/en-us/design/drc/Pages/Digilent-JTAG-HS1-Programming-Cable.aspx In our testing at Avnet, we found this cable to be as fast or faster than the Platform Cable USB-II. This is especially noticeable when performing indirect Flash programming. You can order these cables online or through your local Avnet/Silica office. BryanArticle: 153088
On Nov 28, 9:11=A0am, Giuseppe Marullo <giuseppe.marullonos...@iname.com> wrote: > On 11/28/2011 12:13 PM, scrts wrote:> I use Altera USB Blaster clone from= eBay for ~10USD. Works perfectly: > > Thanks, could you kindly post an example of what I need to search? > > Giuseppe Marullo How about "Altera USB Blaster eBay"? RickArticle: 153089
On 11/28/2011 6:40 PM, Bryan wrote: > Here is a $50 alternative that is supported by Xilinx. Support for > Bryan Bryan, glad to know. Tomorrow I will be in Avnet/Silica to attend a free seminar near Milan on the little LX9 board, the board which has the most elusive documentation on the net (or off the net, because of the several broken links, or crashes even when attempting to register). While there, I will ask about the cable. Giuseppe MarulloArticle: 153090
> How about "Altera USB Blaster eBay"? > > Rick Rick, many thanks but I googled it and nowhere it was able to program a Xilinx part, hence the question. Giuseppe MarulloArticle: 153091
On 11/28/2011 9:32 PM, Giuseppe Marullo wrote: > On 11/28/2011 6:40 PM, Bryan wrote: >> Here is a $50 alternative that is supported by Xilinx. Support for > >> Bryan > > Bryan, glad to know. Tomorrow I will be in Avnet/Silica to attend a free > seminar near Milan on the little LX9 board, the board which has the most > elusive documentation on the net (or off the net, because of the several > broken links, or crashes even when attempting to register). > > While there, I will ask about the cable. > > Giuseppe Marullo > > > Ok, got it using FireFox, no dice with IE.Article: 153092
On Nov 28, 4:55=A0pm, Giuseppe Marullo <giuseppe.marullonos...@iname.com> wrote: > > How about "Altera USB Blaster eBay"? > > > Rick > > Rick, many thanks but I googled it and nowhere it was able to program a > Xilinx part, hence the question. > > Giuseppe Marullo No, the Altera cable won't do Xilinx, but only because of software support. The Xilinx devices require a Xilinx cable clone which is also sold on eBay. I think I saw some for around $10 or so up to about $50 for the ones they say are "exact" duplicates of the Xilinx design. RickArticle: 153093
rickman <gnuarm@gmail.com> writes: > No, the Altera cable won't do Xilinx, but only because of software I seem to remember that I've generated SVF files using Xilinx Impact which I've played back using urjtag and an Altera USB Blaster connected to a Xilinx FPGA. Not a supported toolchain and no guarantee that it will work and not damage your devices... Also it's not possible to use Chipscope this way. //Petter -- .sig removed by request.Article: 153094
I've designed a PDP8 computer and RK08 disk drive controller. I'm trying to test the RK08 controller with a simulated RK05 disk drive. The RK05 disk drive essentially has 6496 sectors and each sector has 256 (16 bit, 4 bits unused) words. All disk operations occurs on sectors: a sector can be read or written. I have a 3,325,952 byte disk image that has the OS image for testing. I'm trying to write a testbench in VHDL that simulates the RK05 disk drive using file IO. I don't do a lot of file IO in VHDL and I'm struggling. As far as I can see: VHDL seems to preclude opening a file for read and write, (or modification). VHDL doesn't seem to have an easy way to 'seek' through a file. Verilog has $fseek() which seems like it would significantly simplify everything. I'm not sure if Verilog can open a file for read/write/update, either. I *could* re-do the testbench in Verilog if doing this in VHDL was impossible but: - I'm much less competent in Verilog. - I'd have to give up having a nice PDP8 simulator executable generated by GHDL. My preference would be to stick with VHDL. Any suggestions? Rob.Article: 153095
On Tue, 29 Nov 2011 01:58:36 -0700, Rob Doyle wrote: > I've designed a PDP8 computer and RK08 disk drive controller. I'm trying > to test the RK08 controller with a simulated RK05 disk drive. The RK05 > disk drive essentially has 6496 sectors and each sector has 256 (16 bit, > 4 bits unused) words. All disk operations occurs on sectors: a sector > can be read or written. > > I have a 3,325,952 byte disk image that has the OS image for testing. > My preference would be to stick with VHDL. One suggestion would be to reduce the seek times by using multiple smaller files ... 6496 would be way too many; how many tracks on that drive? That suggests loading/modifying/saving an entire track (file) when you need write access. It'll be plenty fast enough to simulate PDP11 file I/O! A sconversion program between the whole disk image and a directory full of tracks should be easy, even in VHDL. If that's a binary image, be aware that binary file formats are not well defined in VHDL; the most you can be certain of is that you can write and read back in the same version of the same simulator. Modelsim seems to read commercial binary files in the expected (little-endian) manner. However Xilinx ISIM (a) assumes opposite-endian-ness to Modelsim, and insists on adding an undocumented header (which varies between ISIM versions) on file output, and expects the same on file input. You can work around this (on Linux) using "head" and "tail" to extract header and data from an ISIM output file, and "cat" to join a previously extracted header to a standard binary file so that ISIM can read it, but it's tedious, unnecessary, and Xilinx refuse to document the process or fix it. Start by writing some known data in ISIM, and look at the file in a hex editor. I have no experience with GHDL and binary file I/O (or with GHDL at all) Alternatively it might be easier to be extravagant with disk space, and make the converter translate into a textual format (e.g. hex) for portable VHDL. - BrianArticle: 153096
Bryan <bryan.fletcher@avnet.com> writes: > Here is a $50 alternative that is supported by Xilinx. Support for > this cable is built into ISE 13.2 and later, and previous versions by > installing a plugin. > https://www.em.avnet.com/en-us/design/drc/Pages/Digilent-JTAG-HS1-Programming-Cable.aspx > > In our testing at Avnet, we found this cable to be as fast or faster > than the Platform Cable USB-II. This is especially noticeable when > performing indirect Flash programming. You can order these cables > online or through your local Avnet/Silica office. Does this contain the same logic as the JTAG SMT1? http://digilentinc.com/Products/Detail.cfm?NavPath=2,395,923&Prod=JTAG-SMT1 I can use the Xilinx Platform Cable USB II with Impact (ISE 13.3), but I can't get the Digilent JTAG SMT1 to work. I just get a "Cable connection failed" error message. Using lspci the Xilinx cable shows up as: Bus 002 Device 036: ID 03fd:0008 Xilinx, Inc. And the Digilent JTAG SMT1: Bus 002 Device 060: ID 0403:6010 Future Technology Devices International, Ltd FT2232C Dual USB-UART/FIFO IC The Xilinx cable in /proc/bus/usb/devices < T: Bus=02 Lev=01 Prnt=01 Port=06 Cnt=02 Dev#= 59 Spd=480 MxCh= 0 < D: Ver= 2.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1 < P: Vendor=03fd ProdID=0008 Rev= 0.00 < S: Manufacturer=XILINX < S: Product=XILINX < C:* #Ifs= 1 Cfg#= 2 Atr=80 MxPwr=300mA < I:* If#= 0 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=(none) < E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms < E: Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms The Digilent JTAG SMT1 in /proc/bus/usb/devices < T: Bus=02 Lev=01 Prnt=01 Port=07 Cnt=02 Dev#= 60 Spd=480 MxCh= 0 < D: Ver= 2.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1 < P: Vendor=0403 ProdID=6010 Rev= 7.00 < S: Manufacturer=Digilent < S: Product=Digilent Adept USB Device < S: SerialNumber=210203299904 < C:* #Ifs= 2 Cfg#= 1 Atr=80 MxPwr= 94mA < I:* If#= 0 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=ftdi_sio < E: Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms < E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms < I:* If#= 1 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=ftdi_sio < E: Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms < E: Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms //Petter -- .sig removed by request.Article: 153097
Rob Doyle <radioengr@gmail.com> writes: > I've designed a PDP8 computer and RK08 disk drive controller. > I'm trying to test the RK08 controller with a simulated RK05 > disk drive. The RK05 disk drive essentially has 6496 > sectors and each sector has 256 (16 bit, 4 bits unused) words. > All disk operations occurs on sectors: a sector can be read > or written. > > I have a 3,325,952 byte disk image that has the OS image > for testing. > > I'm trying to write a testbench in VHDL that simulates the > RK05 disk drive using file IO. I don't do a lot of file IO > in VHDL and I'm struggling. Just do the file IO once at startup: read the whole file into an array of integers within your disk drive model. Close that file and then operate directly on the array. If desired, provide a "write it back to disk" function which writes the whole array back out all at once - to the same file, or somewhere else. You might find simulations quicker if you make the big array a variable within a process rather than a signal, but if you only write to it rarely, it might not make much difference. Finally, reading binary can be a pain in VHDL, some simulators behave differently to others. It can sometimes be easier to convert the binary file to a huge list of the same numbers but rendered in ASCII. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 153098
On 11/29/2011 3:52 AM, Martin Thompson wrote:
> Rob Doyle<radioengr@gmail.com> writes:
>
>> I've designed a PDP8 computer and RK08 disk drive controller.
>> I'm trying to test the RK08 controller with a simulated RK05
>> disk drive. The RK05 disk drive essentially has 6496
>> sectors and each sector has 256 (16 bit, 4 bits unused) words.
>> All disk operations occurs on sectors: a sector can be read
>> or written.
>>
>> I have a 3,325,952 byte disk image that has the OS image
>> for testing.
>>
>> I'm trying to write a testbench in VHDL that simulates the
>> RK05 disk drive using file IO. I don't do a lot of file IO
>> in VHDL and I'm struggling.
>
> Just do the file IO once at startup: read the whole file into an array
> of integers within your disk drive model. Close that file and then
> operate directly on the array.
That's a really good idea.
I was worried that it might take a while to read the entire disk image
into the 'big array' but it seemed like it was the simplest approach
and it made seeking around the disk simple also.
I decided to write a test program to see what kind of performance this
approach might achieve. If it is too slow, I'll try "Plan B".
> If desired, provide a "write it back to disk" function which writes the
> whole array back out all at once - to the same file, or somewhere else.
I'm going to put this off until later. That way I can't mung up the
disk image.
> You might find simulations quicker if you make the big array a variable
> within a process rather than a signal, but if you only write to it
> rarely, it might not make much difference.
Both Xilinx ISE and GHDL hang if the 'big array' is signal. I had to
reboot the PC to get control back from ISE... The mouse barely moved,
the disk drive lite was on continuously, and I couldn't even get into
Task Manager to kill ISE. I manually aborted GHDL after a while.
It looks like I *can* use a shared variable for the 'big array' - that
way I can access the 'big array' from multiple processes. Again, this
works for both ISE and GHDL - and the performance is pretty good.
> Finally, reading binary can be a pain in VHDL, some simulators behave
> differently to others. It can sometimes be easier to convert the binary
> file to a huge list of the same numbers but rendered in ASCII.
The disk image is little-endian. I read the disk image a character at
at time and built the 16-bit "words" properly. I believe this to be
portable to different simulators. The disk image, however, is probably
not portable to big-endian systems.
> Cheers,
> Martin
>
I really really appreciate the assistance and good ideas from everyone.
The PDP8 thing isn't my day job.
Just a minor plug for GHDL -
I can compile the PDP8 VHDL code with GHDL and get a 'stand-alone'
PDP-8 simulator executable. For example, I used to have an
executable that had the RAM preloaded with FOCAL-69. I can
synthesize the same code with Xilinx XST and load it into the
target hardware.
Regards,
Rob.
-------------------------- test program ----------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity test_disk is
end test_disk;
architecture behav of test_disk is
subtype word_t is std_logic_vector(0 to 15);
type image_t is array(0 to 1662976) of word_t;
file OUTFILE : text is out "STD_OUTPUT";
type imageFILE_t is file of character;
file imageFILE : imageFILE_t;
shared variable image : image_t;
shared variable size : integer := 0;
begin
process
variable c : character;
variable lin : line;
variable word : word_t;
begin
write(lin, string'("Reading Disk Image..."));
writeline(OUTFILE, lin);
file_open(imageFILE, "diskpack.rk05", read_mode);
while not endfile(imageFILE) loop
read(imageFILE, c);
word(8 to 15) := std_logic_vector(to_unsigned(
character'pos(c), 8));
read(imageFILE, c);
word(0 to 7) := std_logic_vector(to_unsigned(
character'pos(c), 8));
image(size) := word;
size := size + 1;
end loop;
write(lin, string'("Done Reading Disk Image."));
writeline(OUTFILE, lin);
write(lin, string'("Read "));
write(lin, size * 2);
write(lin, string'(" bytes"));
writeline(OUTFILE, lin);
wait;
end process;
process
variable index : integer := 10;
variable lin : line;
begin
write(lin, string'("----> "));
hwrite(lin, image(index));
writeline(OUTFILE, lin);
wait;
end process;
end behav;
------------------------------- end test program ---------------------
------------------------------- simulation results -------------------
$ time ghdl -r -g --workdir=work --ieee=synopsys test_disk
Reading Disk Image...
Done Reading Disk Image.
Read 3325952 bytes
----> 007F
real 0m1.950s
user 0m0.000s
sys 0m0.016s
Article: 153099On 11/29/2011 11:43 AM, Petter Gustad wrote: > Bryan<bryan.fletcher@avnet.com> writes: > >> Here is a $50 alternative that is supported by Xilinx. Support for >> this cable is built into ISE 13.2 and later, and previous versions by >> installing a plugin. >> https://www.em.avnet.com/en-us/design/drc/Pages/Digilent-JTAG-HS1-Programming-Cable.aspx >> >> In our testing at Avnet, we found this cable to be as fast or faster >> than the Platform Cable USB-II. This is especially noticeable when >> performing indirect Flash programming. You can order these cables >> online or through your local Avnet/Silica office. > > Does this contain the same logic as the JTAG SMT1? > > http://digilentinc.com/Products/Detail.cfm?NavPath=2,395,923&Prod=JTAG-SMT1 > > I can use the Xilinx Platform Cable USB II with Impact (ISE 13.3), but > I can't get the Digilent JTAG SMT1 to work. I just get a "Cable > connection failed" error message. > > > Using lspci the Xilinx cable shows up as: > Bus 002 Device 036: ID 03fd:0008 Xilinx, Inc. > > And the Digilent JTAG SMT1: > Bus 002 Device 060: ID 0403:6010 Future Technology Devices International, Ltd FT2232C Dual USB-UART/FIFO IC > > The Xilinx cable in /proc/bus/usb/devices > < T: Bus=02 Lev=01 Prnt=01 Port=06 Cnt=02 Dev#= 59 Spd=480 MxCh= 0 > < D: Ver= 2.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1 > < P: Vendor=03fd ProdID=0008 Rev= 0.00 > < S: Manufacturer=XILINX > < S: Product=XILINX > < C:* #Ifs= 1 Cfg#= 2 Atr=80 MxPwr=300mA > < I:* If#= 0 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=(none) > < E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms > < E: Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms > > > The Digilent JTAG SMT1 in /proc/bus/usb/devices > < T: Bus=02 Lev=01 Prnt=01 Port=07 Cnt=02 Dev#= 60 Spd=480 MxCh= 0 > < D: Ver= 2.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1 > < P: Vendor=0403 ProdID=6010 Rev= 7.00 > < S: Manufacturer=Digilent > < S: Product=Digilent Adept USB Device > < S: SerialNumber=210203299904 > < C:* #Ifs= 2 Cfg#= 1 Atr=80 MxPwr= 94mA > < I:* If#= 0 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=ftdi_sio > < E: Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms > < E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms > < I:* If#= 1 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=ftdi_sio > < E: Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms > < E: Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms > > > //Petter Those cables are not exactly equivalent to the Xilinx platform USB (though Digilent makes one that is, for a bit of a higher price). For the Digilent-specific ones, you need to install the Digilent Plugin for Xilinx Tools, which they kindly offer for Linux as well as Windows: http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,768&Prod=DIGILENT-PLUGIN Have you done this? If not, I guess that would explain why it doesn't work with impact. Steve
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