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Andrew Holme <ah@nospam.com> wrote: (snip) > I've possibly traced it to a high speed (200 MHz) counter which is reloaded > using data from another clock domain . That data is stable when the counter > reloads; but the point where it changes relative to the counter clock is > uncontrolled. > I've checked the counter implementation using FPGA editor and noticed > something curious about the LUT equations. When it works I get: > <F>=((A1*A4)@A2); bel <vco_fa[0]/Mxor_d_Result1>. > when it doesn't work I get: > <F>=((~A2*(A1*A4))+(A2*(~A1+~A4))); bel <vco_fa[0]/Mxor_d_Result1>. Looks the same to me. Though carry logic is important in counters, and if you get that wrong it won't work. > for the same LUT, which is bit 0 of the counter. > A1 is the reload control > A2 is counter Q[0] > A4 is the load input from another clock domain. > The above two boolean expressions are equivalent; but why does FPGA Editor > dump them in different formats and how do I verify what is actually in the > LUT? > I'm wondering if a glitch is coming through the LUT when A4 changes Tradition would be to use a Gray code counter when crossing clock domains, such that it either gets the count before or after. But you aren't actually sending a count across a clock domain. Seems to me that the failure mode would be some bits get the load value and some don't. Can you bring load into the same clock domain, and then use it? That might require it to come some number of clocks earlier. -- glenArticle: 152326
"Andrew Holme" <ah@nospam.com> wrote in message news:UPf0q.40$Ei6.0@newsfe15.ams2... > I'm still using ISE 8.2i. Yes, I know. But it's served me well and I > live by the "if it works don't upgrade it principle." > > "Served me well" until now that is. I may have found a bug. My FPGA > works sometimes. Then I make certain innocent, harmless, neutral changes > in an un-related area ... things stop working. Not an uncommon experience > for FPGA engineers, I know. > > I've possibly traced it to a high speed (200 MHz) counter which is > reloaded using data from another clock domain . That data is stable when > the counter reloads; but the point where it changes relative to the > counter clock is uncontrolled. > > I've checked the counter implementation using FPGA editor and noticed > something curious about the LUT equations. When it works I get: > > <F>=((A1*A4)@A2); bel <vco_fa[0]/Mxor_d_Result1>. > > when it doesn't work I get: > > <F>=((~A2*(A1*A4))+(A2*(~A1+~A4))); bel <vco_fa[0]/Mxor_d_Result1>. > > for the same LUT, which is bit 0 of the counter. > > A1 is the reload control > A2 is counter Q[0] > A4 is the load input from another clock domain. > > The above two boolean expressions are equivalent; but why does FPGA Editor > dump them in different formats and how do I verify what is actually in the > LUT? > > I'm wondering if a glitch is coming through the LUT when A4 changes > > TIA > > OK, I checked the technology viewer. The LUT3 inputs are connected in different orders. Working FPGA: LUT3_6C i0 = reload control i1 = from q output i2 = reload data from another domain Broken FPGA: LUT3_6A i0 = from q output i1 = reload control i2 = reload data from another domain Apart from swapping i0 and i1, the LUT equations are identical. I thought LUT's don't glitch when their inputs change; but I'm wondering if they can in this scenario. It sounds like I need to instantiate this counter entirely from primitives.Article: 152327
Andrew Holme <ah@nospam.com> wrote: >> I've possibly traced it to a high speed (200 MHz) counter which is >> reloaded using data from another clock domain . That data is stable when >> the counter reloads; but the point where it changes relative to the >> counter clock is uncontrolled. This statement doesn't make sense. For a synchonous load, the counter reloads on the counter clock. >> I've checked the counter implementation using FPGA editor and noticed >> something curious about the LUT equations. When it works I get: >> <F>=((A1*A4)@A2); bel <vco_fa[0]/Mxor_d_Result1>. This doesn't look right for a counter with a load enable. (snip) > OK, I checked the technology viewer. The LUT3 inputs are connected in > different orders. > Working FPGA: > LUT3_6C > i0 = reload control > i1 = from q output > i2 = reload data from another domain > Broken FPGA: > LUT3_6A > i0 = from q output > i1 = reload control > i2 = reload data from another domain > Apart from swapping i0 and i1, the LUT equations are identical. The equations aren't the same with that swap. > I thought LUT's don't glitch when their inputs change; but I'm > wondering if they can in this scenario. They don't glitch when going to a state with the same output value. That doesn't always happen with a load enable on a counter. > It sounds like I need to instantiate this counter entirely > from primitives. Better to synchronize the enable to the counter clock domain. -- glenArticle: 152328
"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:j1s740$nn7$1@speranza.aioe.org... > Andrew Holme <ah@nospam.com> wrote: > >>> I've possibly traced it to a high speed (200 MHz) counter which is >>> reloaded using data from another clock domain . That data is stable >>> when >>> the counter reloads; but the point where it changes relative to the >>> counter clock is uncontrolled. > > This statement doesn't make sense. For a synchonous load, the > counter reloads on the counter clock. Yes, the reload control is synchronous with the counters clock. The reload data is not but it should be stable for several cycles before and after the reload. The eaxacrt instance at which it later changes could occur anywhere within the counter clock cycle. > >>> I've checked the counter implementation using FPGA editor and noticed >>> something curious about the LUT equations. When it works I get: > >>> <F>=((A1*A4)@A2); bel <vco_fa[0]/Mxor_d_Result1>. > > This doesn't look right for a counter with a load enable. It always adds the counter; but the counter contents are zero in the reload cycle. > > (snip) >> OK, I checked the technology viewer. The LUT3 inputs are connected in >> different orders. > >> Working FPGA: >> LUT3_6C >> i0 = reload control >> i1 = from q output >> i2 = reload data from another domain > >> Broken FPGA: >> LUT3_6A >> i0 = from q output >> i1 = reload control >> i2 = reload data from another domain > >> Apart from swapping i0 and i1, the LUT equations are identical. > > The equations aren't the same with that swap. Why do you say that? They are by my reckoning. > >> I thought LUT's don't glitch when their inputs change; but I'm >> wondering if they can in this scenario. > > They don't glitch when going to a state with the same output value. > That doesn't always happen with a load enable on a counter. > >> It sounds like I need to instantiate this counter entirely >> from primitives. > > Better to synchronize the enable to the counter clock domain. > > -- glen > > Thanks for the suggestion; but, as I said, it is. I tried instatntiating the LUT3 primitive and this did indeed make the "bad" FPGA slice look exactly the same as the "good" FPGA. Unfortunately, the "bad" FPGA still doesn't work :-( I will attempt your earlier suggestion of re-timing the reload data to the counter clock.Article: 152329
Andrew Holme <ah@nospam.com> wrote: (snip) >>>> I've checked the counter implementation using FPGA editor and noticed >>>> something curious about the LUT equations. When it works I get: >>>> <F>=((A1*A4)@A2); bel <vco_fa[0]/Mxor_d_Result1>. >> This doesn't look right for a counter with a load enable. > It always adds the counter; but the counter contents are zero > in the reload cycle. >> (snip) >>> OK, I checked the technology viewer. The LUT3 inputs are connected in >>> different orders. >>> Working FPGA: >>> LUT3_6C >>> i0 = reload control >>> i1 = from q output >>> i2 = reload data from another domain >>> Broken FPGA: >>> LUT3_6A >>> i0 = from q output >>> i1 = reload control >>> i2 = reload data from another domain >>> Apart from swapping i0 and i1, the LUT equations are identical. >> >> The equations aren't the same with that swap. > Why do you say that? They are by my reckoning. They are symmetric on exchange of i0 and i2, which go to A1 and A4. It seems to have been snipped, but that is the way I read the post. -- glenArticle: 152330
Hi, I tried to respond to this yesterday but it seems that my post didn't show up? So I'll try again. What you are actually trying to do, and what you are asking is very unclear, but I assume you mean that you would like to know how to load data into the memory from the PC side. There are a number of ways to do this, and it really depends on what hardware you have, what kind of data rate you want, etc. Also from your code I see that you are using the same address input to control both the writing and the reading, but you can have separate address inputs for read/write, that will be much more convenient for what I think you are probably trying to do overall. Lastly, what kind of hardware do you have, and what kind of interface do you want with the host PC side? USB? A regular old serial port? You can write a state machine in VHDL to process incoming communication, or you can use a soft microcontroller; For a small application like what I suspect you are possibly trying to do, I might use a Picoblaze core, if I was using a Xilinx FPGA.. for other vendors there are other solutions, or there are similar solutions that will work for all vendors (various soft CPUs available at OpenCores). You will have to be more clear on what you're actually trying to do, if you would like help.. but hopefully what I've said here will give you at least an idea of what direction to take. SteveArticle: 152331
On Aug 7, 9:00=A0pm, "ECS.MSc.SOC" <mahdiyar.saray...@gmail.com> wrote: > Hi all > > I want to do a project with a FPGA. The FPGA that I choos is ALTERA > Cyclone III.I think that there is no analog input in that. Of course, > I know that I can use an external ADC(A/D) but I cannot do it because > my inputs and outputs are too much. > > can everyone tell me a FPGA from this family (ALTERA) that have analog > inputs and output? > > Regards Xilinx's new 7 series FPGAs have dual 1MSPS 12 bit ADCs. This feature is called XADC. Regards, Stephen Silicon on Inspiration www.sioi.com.auArticle: 152332
> Hello, > I had problems when installed very old FTDI drivers. Altera programmer gets frustrated when any > FTDI chip is connected, but works if drivers are new. Tell the customer to unplug all the > USB<->UART devices firstly or better to unplug everything from the USB, except the programmer. For future reference.... He got things working by installing Q 11 but pointing his machine at the Q 9 driver files. Nial.Article: 152333
"Andrew Holme" <ah@nospam.com> wrote: > >"Andrew Holme" <ah@nospam.com> wrote in message >news:UPf0q.40$Ei6.0@newsfe15.ams2... >> I'm still using ISE 8.2i. Yes, I know. But it's served me well and I >> live by the "if it works don't upgrade it principle." >> >> "Served me well" until now that is. I may have found a bug. My FPGA >> works sometimes. Then I make certain innocent, harmless, neutral changes >> in an un-related area ... things stop working. Not an uncommon experience >> for FPGA engineers, I know. >> > >OK, I checked the technology viewer. The LUT3 inputs are connected in >different orders. > >Working FPGA: >LUT3_6C >i0 = reload control >i1 = from q output >i2 = reload data from another domain > >Broken FPGA: >LUT3_6A >i0 = from q output >i1 = reload control >i2 = reload data from another domain > >Apart from swapping i0 and i1, the LUT equations are identical. > >I thought LUT's don't glitch when their inputs change; but I'm wondering if >they can in this scenario. > >It sounds like I need to instantiate this counter entirely from primitives. No, this is a clock domain crossing problem. Be sure to put constraints on the signals which go from one domain to the other. Typically one signal should indicate there is 'new data'. Due to sampling this signal is usually delayed by 1 destination clock cycle. The 'new data' should be constrained to go from source domain to destination domain within one period of the destination clock. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 152334
Oops, sorry about the double replies. I don't have a usenet server, and Google Groups just plain sucks. It didn't even show me that there were a couple of replies already, and when my first one went through it said "post was successful" but even a day later the post didn't show up. So I'll start using fpgarelated.com for now, since it seems to be better than Google Groups at least. Anyway, my assumption is that the OP wants to load data into the bram at runtime, not when generating programming file? In that case data2mem doesn't help. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152335
Hello all, HumanData in Osaka, Japan offer some Spartan3-AN and Spartan6 FPGAs, in BGA package, but on a nifty little breakout board that fits into a PLCC68 socket. It's a tad expensive at 12,000 yen per unit (the FPGA itself is only maybe about 20 dollars in single unit prices on Digi-key) but then you don't have to worry about your carrier board being only two layers (or probably even hand wired on proto-board!), and for a hobbyist or otherwise one-off kind of thing, it would save you the cost of doing a four-layer board. Plus, you can simply pop it out of the socket and reuse it as you please! Here's a link: http://www.hdl.co.jp/en/index.php/plcc68-series-menu/xp68-02.html Maybe not super economical, but it's an idea. Cheers, Steve --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152336
sbattazzo wrote: > I don't have a usenet server, and Google Groups just plain sucks. I use SeaMonkey as a news client, with Eternal September (free) as the server. Works well for me.Article: 152337
Before I repeat some of the advice that others have given, let's review some fundamentals: 1) Combinatorial logic is glitchy. Yes, in some cases you can eliminate glitches with careful design and a thorough knowledge of the underlying technology. But unless you've painted yourself into a corner or are doing something incredibly clever, I don't recommend the hand tweaking of low-level combinatorics. 2) For synchronous design, we don't care about the logic glitches. Provided we've met setup and hold requirements, logic levels will settle out by the time we're ready to sample them. (In fact, I suspect that many logic designers aren't aware of combinatorial glitches because they've been doing synchronous design, and are thus blissfully unaware of the glitches that are generated and ignored in their circuits. Anyone who's tried to clock a flip- flop with the terminal count of a 74161 has learned the lesson, or gone into another line of work. Yes, I'm old. Deal with it.) 3) Transferring data or control between mutually-asynchronous subsystems is a whole other matter. In the situation we're discussing here, a LUT glitch can occur just as the counter is updating, regardless of whether the load signal is active. The best approach, as has been suggested by others, is to put a register between the incoming load value and the counter, and clock that register with the counter clock. One other thing: be sure to create a time spec between the register and the counter, and set the spec as low as possible, to give the register plenty of time to come out of a metastable state before the counter clocks. Bob Perlman Cambrian Design WorksArticle: 152338
I found it!
It wasn't a LUT glitch. There are no LUT glitches. I take it back.
It wasn't a clock domain crossing problem. The loaded data is stable before
during and after the reload.
It's a synthesis bug in ISE8.2i which is most easily seen in "View
Technology Schematic" for this:
module Test (
input clk,
output [7:0] out1,
output [7:0] out2
);
function [7:0] bcd2bin;
input [8:0] bcd;
begin
bcd2bin = 8'd100*bcd[8] + 8'd10*bcd[7:4] + bcd[3:0]; // 000 ... 199
end
endfunction
wire [8:0] in1;
reg [8:0] in2;
assign in1 = 9'h155;
always @ (posedge clk) in2 <= 9'h155;
assign out1 = bcd2bin(in1);
assign out2 = bcd2bin(in2);
endmodule
out1 is 8'b00011011
out2 is 8'b10011011
Article: 152339Is there a utility that does peeks and pokes to PCIe devices. I'm developing an FPGA with a PCIe interface and I'd like to do some simple memory accesses before I move on to the more complicated things like DMA. We have a driver in development but I think there is a standard Altera driver already in the kernel which I assume would be good enough for simple accesses. I'm running on Scientific Linux 6.1. lspci identifies the device as an Altera device which is correct. 01:00.0 Unassigned class [ff00]: Altera Corporation Device 0004 (rev 01)Article: 152340
Hi all - I'm running Xilinx ISE 10.1 on a 64-bit linux machine, and I'm getting a weird error. Designs which do not use a coregen generated file compile fine...however, when I try and use coregen, or even generate a core from the coregen GUI, I get kicked out with the following error: Generating IP... -cp: command not found ERROR: coreutil:424 - An Error occured while running Java. Please exaime the console or coregen log file for a specific IP related error WARNING:coreutil:266 - could not remove outfile I'm not sure why it couldn't locate the 'cp' command, as it is located in /bin/. Has anyone come across this error before? I have seen similar threads about the coregen not being able to locate a file, but normally these files are user specific, not the 'cp' command. How can I tell where coregen is looking at for these files? ThanksArticle: 152341
Zach Stechly <lunaticengineer@gmail.com> wrote: > I'm running Xilinx ISE 10.1 on a 64-bit linux machine, and I'm getting > a weird error. Designs which do not use a coregen generated file > compile fine...however, when I try and use coregen, or even generate a > core from the coregen GUI, I get kicked out with the following error: > Generating IP... > -cp: command not found > ERROR: coreutil:424 - An Error occured while running Java. Please > exaime the console or coregen log file for a specific IP related error > WARNING:coreutil:266 - could not remove outfile > I'm not sure why it couldn't locate the 'cp' command, as it is located > in /bin/. The -cp option to java gives the classpath. (Note that in linux, a filename can start with -, such that -cp is a legal (though confusing) command name.) That doesn't really help you fix the problem, but does explain why the cp command isn't helping. One possibility is that an environment variable is expanded inline, and contains a semicolon. That would end the command, such that a following -cp would be expected to be a new command. > Has anyone come across this error before? I have seen similar threads > about the coregen not being able to locate a file, but normally these > files are user specific, not the 'cp' command. -- glenArticle: 152342
We need to code some modules in both VHDL and Verilog and would like to use a parameter/generic to control inferring sync or async resets. Is there a clean way to code this that is similar in both VHDL and Verilog? For example, we could try to use `define in Verilog, but this won't port well to VHDL. I don't see how wen can use generate statements in Verilog to do this nicely, either. Any thoughts? Thanks! John ProvidenzaArticle: 152343
On 08/11/2011 01:44 AM, Pete Fraser wrote: > sbattazzo wrote: > >> I don't have a usenet server, and Google Groups just plain sucks. > > I use SeaMonkey as a news client, with Eternal September (free) > as the server. Works well for me. Cool, thanks! I had looked around for free servers, but I missed over this one.Article: 152344
On Jul 11, 11:46=A0am, wzab <wza...@gmail.com> wrote: > Hi, > > I have prepared a heap-sorter implementation for FPGA. The sources are > licensed under the BSD license and > are available at alt.sources group. > Due to the fact, that I'm on my holidays, I was not able to post the > standard shar archive, and instead I have finally to send the > uuencoded tar.bz archive. > You can find it at:http://groups.google.com/group/alt.sources/msg/ab4bda5= 6ca52cc59?dmode... > (copy the body of the message to the file, then run "uudecode" on this > file, and you'll get sorter.tar.bz2 archive). > > The sorter is able to sort one data record every 2 clock pulses. > I was able to compile into Virtex-6 XC6VLX75T-3FF484 =A0a sorter with > capacity of 65535 records (able to sort the data stream with maximum > distance between unsorted records equal to 65535) with each record > containing 18 bits of time-stamp and 20 bits of payload. > > More information is available at the beginning of my alt.sources post. > The current sources will be available (a little later) athttp://www.ise.p= w.edu.pl/~wzab/fpga_heapsort > -- > HTH & Best regards, > Wojtek Zabolotny Hi Wojtek, Your work is impressive. It may be used in 16-bit integer environment. I want to know what delay time is: from the last input data to the first output sorted data in addition to the one sorted data out for every clock cycle. Your Heapsort's big problem is it can apply to 16-bit integer and the sort is not stable. WengArticle: 152345
On Aug 10, 6:53=A0pm, johnp <jprovide...@yahoo.com> wrote:
> We need to code some modules in both VHDL and Verilog and would like
> to use a parameter/generic
> to control inferring sync or async resets. =A0Is there a clean way to
> code this that is similar in both
> VHDL and Verilog?
>
> For example, we could try to use `define in Verilog, but this won't
> port well to VHDL. =A0I don't see how
> wen can use generate statements in Verilog to do this nicely, either.
>
> Any thoughts?
>
> Thanks!
>
> John Providenza
In VHDL, you could do have an entity generic control whether the async
reset logic gets called or not as shown below. The 'Do reset stuff'
can be implemeted as a procedure that gets invoked in the two places.
That way there is no need to copy/paste the reset actions into the two
places in the code.
process(Clock, Reset)
begin
if rising_edge(Clock) then
if (Reset =3D '1') and not(DO_ASYNC_RESET) then
-- Do reset stuff here
else
...
end if;
end if;
if (Reset =3D '1') and DO_ASYNC_RESET then
-- Do reset stuff here
end if;
end process;
Kevin Jennings
Article: 152346On 08/08/2011 09:52 PM, linobi wrote: > Hi there! > > I need some advice. I want to make a circuit to drive a VGA monitor. I've > done it with the FPGA trainer boards with Xilinx chips, but now I want to > design a custom board that host only the necessary circuitry to do so and > not depend on eval boards with lot of stuff I don't need. > > I've got already a bit experience on designing PCBs, I get pretty much > along with the EagleCad, I've build mostly boards with microcontrollers and > simply stuff. But now for what I see, handling FPGA is a completely > different thing. > > For what I've been reading, FPGA need a lot of requirements, 50-ohms > impedance for some clock traces, copper layer thickness, lots of different > power planes,... heck, there is even some excel spreasheet from altera to > calculate power supply stage decoupling caps =S > > Now I realize this might be a project beyond my current training, however, > I want to give it a shot. I just need the basics: voltage regulators, > configuration ROM, 50MHz clock, downloading cable interface; and of course, > the VGA dac and some extra broke out pins to interface a microcontroller. I've just released a product that's very close to what you're looking for: http://www.sioi.com.au/shop/product_info.php/products_id/48 Price is $79 for one, cheaper for 3+ boards. I has an FPGA big enough to hold a VGA controller plus a MicroBlaze microcontroller, 256Mb DRAM for your frame buffer, 62.5MHz clock, voltage regs, JTAG port for programming, configuration ROM, 38 break out pins. You'd need to add the VGA DAC yourself, that would involve making a simple PCB with the VGA DAC and VGA connector to plug into the expansion connector (64 way edge connector with 38 available FPGA connections). Stephen Ecob Silicon on Inspiration www.sioi.com.auArticle: 152347
glen herrmannsfeldt <gah@ugcs.caltech.edu> writes: > Zach Stechly <lunaticengineer@gmail.com> wrote: > >> I'm running Xilinx ISE 10.1 on a 64-bit linux machine, and I'm getting >> a weird error. Designs which do not use a coregen generated file >> compile fine...however, when I try and use coregen, or even generate a >> core from the coregen GUI, I get kicked out with the following error: > >> Generating IP... >> -cp: command not found >> ERROR: coreutil:424 - An Error occured while running Java. Please >> exaime the console or coregen log file for a specific IP related error >> WARNING:coreutil:266 - could not remove outfile > >> I'm not sure why it couldn't locate the 'cp' command, as it is located >> in /bin/. > > The -cp option to java gives the classpath. > > (Note that in linux, a filename can start with -, such that -cp > is a legal (though confusing) command name.) > > That doesn't really help you fix the problem, but does explain > why the cp command isn't helping. > > One possibility is that an environment variable is expanded inline, > and contains a semicolon. That would end the command, such that > a following -cp would be expected to be a new command. Might also be that the environment variable JAVA (or whatever) is not set, or set to the empty string.Article: 152348
On 08/10/11 23:39, General Schvantzkoph wrote: > Is there a utility that does peeks and pokes to PCIe devices. I'm > developing an FPGA with a PCIe interface and I'd like to do some simple > memory accesses before I move on to the more complicated things like DMA. > We have a driver in development but I think there is a standard Altera > driver already in the kernel which I assume would be good enough for > simple accesses. > > I'm running on Scientific Linux 6.1. > > lspci identifies the device as an Altera device which is correct. > > 01:00.0 Unassigned class [ff00]: Altera Corporation Device 0004 (rev 01) you don't even need a driver for simple memory access. if your device is detected by the kernel you can directly access the BARs via sysfs: # ls -l /sys/bus/pci/devices/0000\:01\:00.0/ [...] -rw------- 1 root root 256M Aug 11 08:51 resource0 -rw------- 1 root root 256 Aug 11 08:51 resource1 -rw------- 1 root root 64K Aug 2 08:14 resource2 [...] This is an example of a device with 3 BARs. These files can be read/written/mmapped... you could use "dd" or write a little C program to mmap the files. HTHArticle: 152349
In comp.arch.fpga rndhro <rnd@hro.org> wrote: > On 08/10/11 23:39, General Schvantzkoph wrote: >> Is there a utility that does peeks and pokes to PCIe devices. (snip) > you don't even need a driver for simple memory access. if your device is > detected by the kernel you can directly access the BARs via sysfs: > # ls -l /sys/bus/pci/devices/0000\:01\:00.0/ > [...] > -rw------- 1 root root 256M Aug 11 08:51 resource0 > -rw------- 1 root root 256 Aug 11 08:51 resource1 > -rw------- 1 root root 64K Aug 2 08:14 resource2 > [...] I remember doing this with VME based Suns and SunOS. Device mapped VME addressing space, and memory mapped files combine to form memory mapped memory space. -- glen
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