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Ok, I understood. Thanks! Just question about "using a 6T memory cell" Does it mean 6 MOS transistors that handle and ouptut one bit? And did I get correctly the main concern that 2D static RAM I can get from foundry is already overhead free, i.e. there is no penalty due to address decoding, and thus the additional optimization will not make sense? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152176
If you're instantiating a LUT-based multiplier core, you can't expect the t= ools to turn it into a DSP48-based multiplier during the implementation. Th= is is something that you need to do at the RTL level: instantiate as many D= SP48-based multiplier cores as you can, and leave the rest as LUT-based one= s. You may use the VHDL "generate" statement to selectively instantiate DSP-48= or LUT-based multiplier cores. Cheers, Guy. http://guy-eschemann.deArticle: 152177
You may want to check that the input data paths from the pads to the sampli= ng flip-flops are properly constrained. There's an option in the timing ana= lyzer for reporting unconstrained paths. It's also usually a good idea to put those FFs in the IOBs to minimize the = delay from the pads to the FFs. You can use the IOB constraint for that. Af= ter the implementation, you should check that the specified FFs were effect= ively placed in the IOBs - you can use the FPGA editor for that. Hope this helps, Guy. http://guy-eschemann.deArticle: 152178
>You may want to check that the input data paths from the pads to the sampli= >ng flip-flops are properly constrained. There's an option in the timing ana= >lyzer for reporting unconstrained paths. > >It's also usually a good idea to put those FFs in the IOBs to minimize the = >delay from the pads to the FFs. You can use the IOB constraint for that. Af= >ter the implementation, you should check that the specified FFs were effect= >ively placed in the IOBs - you can use the FPGA editor for that. > >Hope this helps, >Guy. >http://guy-eschemann.de > > I have already constrained the data paths from the pads to the sampling FFs.And the FFs are in IOBs because without that i was having a massive timing failure and i verified it using the FPGA editor. So already done that. Thanks =) any other thing i can check ? regards --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152179
On 07/15/2011 07:26 AM, dragonfly wrote: > Ok, I understood. Thanks! > > Just question about "using a 6T memory cell" > > Does it mean 6 MOS transistors that handle and ouptut one bit? Static RAM needs 6 MOS transistors just to remember what it was told: http://en.wikipedia.org/wiki/Static_RAM#Design It still needs sense and address lines to get the data into and out of the memory. Dynamic RAM just needs one MOS transistor and a capacitor, but you have to keep reminding it of what it should already know: http://en.wikipedia.org/wiki/Dynamic_RAM#Operation_principle > And did I get correctly the main concern that 2D static RAM I can get from > foundry is already overhead free, i.e. there is no penalty due to address > decoding, and thus the additional optimization will not make sense? No, it's not that there's no penalty due to address decoding. It's that there's a WHOPPING BIG PENALTY for getting something outside the box: either you get something that's made up out of individual gates, and is therefore huge, or you have to HAND MAKE your ASM, which takes a huge amount of time. Re-read what Andreas said about hand-made RAM vs. compiled. He's comparing the difference between the output of their "memory compiler" (which is hand optimized to generate nothing but RAM) and some memory that was specified with (I assume) plain old HDL. A shift register made up from static cells is still going to need six MOS transistors per cell, although it's not going to need the addressing logic. But if it's not already made for you, then you're back to needing it to be hand made ($$$$$) or synthesized from gates (area area area). Ditto a shift register made from dynamic cells, although then you'd be talking maybe two or three transistors / cell (I don't know my trivia well enough to say). -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 152180
On 2011-07-15, dragonfly <purto@n_o_s_p_a_m.n_o_s_p_a_m.spiritcorp.com> wrote: > Just for sure - Am I correct that one logic cell (logic element) can hold > 16 bits of a sequential shift register and thus to keep 1023x10 bits I need > 1023*10/16=640 elemets as a margin? First of all, there seems to be some confusion regarding whether you target an ASIC or an FPGA. In Xilinx FPGAs some look-up tables (LUTs) can be used as shift registers. An older Xilinx FPGA with 4 input LUTs can store 16 entries whereas newer FPGAs like the Virtex-6 can store 32 bits in a single LUT used as a shift register. Another way to get a very cheap long shift register might be to set a blockram into FIFO mode which is possible on some Xilinx FPGAs. Do note that building a very long shift register would likely consume more power than a FIFO implemented using a blockram. However, if you are mainly targetting ASICs, this kind of design feature in FPGAs is of little interest. I have been involved in a few ASICs, and I've never heard about auto-sequencing memorise being available as hard macros. However, I may just have missed something here. Nevertheless, if we assume that such a memory would be implemented in roughly the same way as a regular SRAM memory (that is, using a 6T memory cell [1] together with row and column lines and sense amplifiers) I don't see that there could be much difference between an ASM and a RAM. (At least for larger memories.) Also note that well optimized memory blocks in ASICs are much more area efficient than the equivalent memory implemented using standard gates. I've found the following numbers from an evaluation I did some time ago for a 130nm ASIC process: * 512 bit register file memory in standard gates: 2.5 area units * 65536 bit custom memory from a memory compiler: 33 area units Note that the custom memory contains 128 times as many bits while being only 13 times larger. (Both memories were optimized for area.) Anyway, as a comparison a 32 bit adder occupied from 0.21 to 1.0 area unit depending on whether it was optimized for area or speed. So the difference between a large custom memory and a large custom memory together with a few small adders/registers that you use for sequencing (effectively turning it into a FIFO) would be quite small. (You wouldn't even need to use adders, you could use LFSR registers to reduce the size of the sequencing circuit.) However, it doesn't hurt to ask if the foundry knows about some very efficient ASM blocks. (If I understand your question correctly it might be better to ask for efficient FIFO blocks since it seems like your problem could be solved using a plain FIFO.) I hope this is of some use to you when deciding on your architecture. regards /AndreasArticle: 152181
On 2011-07-15, Hal Murray <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote: > Can I correct for that by feeding in a clean signal, collecting > a lot of data, and thinking about it? I know that there has been some research in this area and this kind of technology is also commercially available. (Some people from another part of my university have started a quite successful company based on this kind of technology for example.) Anyway, if you want to do this as a learning experience/hobbyist project or something similar I'd say go for it. You might want to search for papers on "time interleaved A/D converters" before deciding to do so though. If you are doing this for commercial reasons you are probably better off buying a faster ADC since it will be a lot easier to get that working correctly than what you are proposing. You'll save yourself some development time and perhaps also some lawyer time (since I'm guessing that there are quite a few patents in this area that you would either have to work around or work out a licensing deal for). Anyway, good luck with your project! regards /AndreasArticle: 152182
I usually use the drawtiming available at http://drawtiming.sourceforge.net However, when I write documentation or article in LaTeX, I often use simply the tikz-timing package. -- HTH & Regards, WojtekArticle: 152183
You may try changing the phase of your sampling clock to see if that helps. Cheers, Guy. http://guy-eschemann.deArticle: 152184
>You may try changing the phase of your sampling clock to see if that helps. > >Cheers, >Guy. >http://guy-eschemann.de > Done that too.. Actually when i changed the phase of the clock, the byte corruption was narrowed down to only 1 bit getting corrupt and performance got better, like the byte corruption was not frequent as before but still it was. So, i delayed the clock a little more , by 1ns , the performance stayed the same. I was thinking of changing the clock termination resistor, at the moment i have a 33Ohms resistor in place, do u think it has anything to do with the termination ? Thanks --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152185
On Jul 15, 9:53=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hi, > I am using a customized board with 1 spartan 3 xc3s4000 FPGA =A0and 2 Gig= abit > Phys. My system clock is 125Mhz and i am facing an issue which occurs aft= er > a while but since it occurs so it is a problem for me. > > I have no timing failures in my design, at least none reported by xilinx > ISE. I also read the delay report to see if there are any of my critical > signals listed under the worst delay paths,none. > > The design is actually a MAC so whatever we receive from one PHY is > transmitted on to the other PHY. > The problem i am facing is that occasionally only one byte in the packet > gets corrupt.And it gets corrupt on the incoming interface i.e. at the > first FF. I can't figure out why would it behave like this occasionally a= s > it works properly otherwise. Any pointers on how i should proceed further > ? > > PS. There are no setup/hold time violations. > > regards =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com One idea is that this problem is being caused by the receiver's inability to recover a "scrolling" source clock frequency. The clock frequency of the source box that is transmitting the traffic into the receiver which is reporting periodic corruption is asynchronous. True, that frequency may be based on 125 MHz +/- some ppm, but it will still "scroll" left or right (temporally speaking) in relation to the receiver clock. But as long as it is in PPM spec, this should happen slowly enough that the receiver can continuously synchronize to the traffic by using the idle time sync bytes. A quick test is to see if the corruption occurs in loopback, in which case, the receiver should be referencing a clock that is synchronous to it, assuming that one single oscillator provides the source frequency to both the Tx and Rx domains. If this is a scroll problem, the receiver should not report corruption. (Be careful not to provide an "external sync" to the receiver in this "isolation" loopback test. Also test to see if the corruption is traffic dependent. Try different packet sizes. Then try varying the traffic content. - JohnArticle: 152186
Hello. I'm a little bit tinkering with soft core cpus for fpgas, but I really have serious issues doing so. Thats why I decided to ask some experts and register here. I tried to find a efficient softcpu that is supported by a c compiler. As I'm working with a Xilinx Spartan-3, I first tried the Microblaze, which indeed worked. But it's not the solution I was looking for. The Microblaze should be usable like the Picoblaze, which can just be integrated in a verilog module with full access to the cpu bus. So I searched further... On OpenCores I've stumbled across the "AVR Core" and the microblaze clones "aeMB" and "openFire". I've tried to integrate these 3 into my project. Here are my experiences. The OpenFire worked in the behavioural simulation as it should. But in post route simulation it seems to have timing issues and starts to get an undefined state after some time. The aeMB has even issues with the same program I used for the openfire in behavioural simulation as some registers became undefined after some time. The AVR Core has the same issues as the openfire. The Picoblaze is the only soft core I've managed to get working. But as the instruction memory is a little bit small and there are no c compilers available, I only used it once. Maybe It's because I've missed something that I should have done. I'm using the somewhat outdated Spartan-3 Starter Kit of Digilent and even found a SoC on OpenCores that uses the openfire exactly for this board. But even with the manual that comes with it, I didn't managed to get it working. Except for this project I'm unable to find other that use these cpus. What I want to know is, wether there a some people around here that actually used one of these or maybe have a better one to recommend. The OpenRISC is to big as it used ~520% of my FPGA. :-D I'm writing all this because I now tried to get these working for 2 weeks and I really can't take it anymore. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152187
Hi what about pacoblaze (open-source Verilog variant of PB?) Also JOP (something different, a hardware Java interpreter: http://www.jopdesign.com) seems to be extensively tested. The Plasma MIPS from Opencores is also a tested design. Kind regards Nikolaos KavvadiasArticle: 152188
I have finally managed to post uncorrupted shar archive with sources of my sorter to alt.sources. Additionally I have provided sources at http://www.ise.pw.edu.pl/~wzab/fpga_heapsort/sorter.tar.bz2 with short description at http://www.ise.pw.edu.pl/~wzab/fpga_heapsort -- Regards, WojtekArticle: 152189
Our ERIC5 (http://www.entner-electronics.com/tl/index.php/eric5.html) addresses all your concerns. However, it is not free (EUR 1500,- including VHDL-code and C-compiler). Regards, Thomas www.entner-electronics.comArticle: 152190
As you have a bit file that does work, could it be a pin constraint problem? (worng UCF file, no ucf file...) could it be that the bit file you are using is not actually the file you intended to use? (impact pickin up the bit file from an other folder?)Article: 152191
On Jul 14, 8:45=A0pm, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hi, > I am using a custom board design in which i have 2 FPGAs (spartan 3 > xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is like > this: > > EEPROM -> FPGA1 -> FPGA2 > > Now the problem is that when i try to program the FPGA using JTAG, my DON= E > goes high, INIT_B stays high and PROG_B stays high after config, iMPACT > says program succeeded but FPGA doesn't work. If i run chipscope, it says= 0 > cores found. > Same goes when i try to program FPGAs using EEPROM. I have tried in daisy > chain and even programming the FPGAs individually by disconnecting them > from the chain. > > Now there's another dynamic to this problem, i have a previously built .b= it > file, when i program the FPGAs using it, they get programmed. But if i tr= y > to program the FPGAs with any other .bit file, they don't. I am clueless > now and i cannot find the problem. > > I need help here.. > > Thanks > regards > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Had this problem about four years ago. From memory, done is connected to both FPGAs with a single pull up. If you program one device using JTAG it lets go of done but the other unprogrammed device still pulls done low and config says that it has failed. Program FPGA A. A lets go of done but B still pulls it low and the final bit of jtag says that it has failed (done is still low). Program FPGA B. B lets go of done which can now go high and B is configured correctly. Now program A again and it drives done low, configures, lets go of done and now knows that it has configured correctly. ColinArticle: 152192
>On Jul 14, 8:45=A0pm, "salimbaba" ><a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: >> Hi, >> I am using a custom board design in which i have 2 FPGAs (spartan 3 >> xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is like >> this: >> >> EEPROM -> FPGA1 -> FPGA2 >> >> Now the problem is that when i try to program the FPGA using JTAG, my DON= >E >> goes high, INIT_B stays high and PROG_B stays high after config, iMPACT >> says program succeeded but FPGA doesn't work. If i run chipscope, it says= > 0 >> cores found. >> Same goes when i try to program FPGAs using EEPROM. I have tried in daisy >> chain and even programming the FPGAs individually by disconnecting them >> from the chain. >> >> Now there's another dynamic to this problem, i have a previously built b= >it >> file, when i program the FPGAs using it, they get programmed. But if i tr= >y >> to program the FPGAs with any other .bit file, they don't. I am clueless >> now and i cannot find the problem. >> >> I need help here.. >> >> Thanks >> regards >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > >Had this problem about four years ago. >From memory, done is connected to both FPGAs with a single pull up. If >you program one device using JTAG it lets go of done but the other >unprogrammed device still pulls done low and config says that it has >failed. > >Program FPGA A. A lets go of done but B still pulls it low and the >final bit of jtag says that it has failed (done is still low). >Program FPGA B. B lets go of done which can now go high and B is >configured correctly. >Now program A again and it drives done low, configures, lets go of >done and now knows that it has configured correctly. > >Colin Colin, i have already done that, no success. On some .bit files it gets programmed,otherwise it doesn't. I saw in FPGA editor that xilinx XST sometimes maps my signals on to INIT_B pad, was wondering if it could create problems. I am not mapping any signal on the INIT_B pad, xilinx maps it i don't know why. > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152193
On Jul 18, 7:08=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > >On Jul 14, 8:45=3DA0pm, "salimbaba" > ><a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > >> Hi, > >> I am using a custom board design in which i have 2 FPGAs (spartan 3 > >> xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is > like > >> this: > > >> EEPROM -> FPGA1 -> FPGA2 > > >> Now the problem is that when i try to program the FPGA using JTAG, my > DON=3D > >E > >> goes high, INIT_B stays high and PROG_B stays high after config, iMPAC= T > >> says program succeeded but FPGA doesn't work. If i run chipscope, it > says=3D > > 0 > >> cores found. > >> Same goes when i try to program FPGAs using EEPROM. I have tried in > daisy > >> chain and even programming the FPGAs individually by disconnecting the= m > >> from the chain. > > >> Now there's another dynamic to this problem, i have a previously built > .b=3D > >it > >> file, when i program the FPGAs using it, they get programmed. But if i > tr=3D > >y > >> to program the FPGAs with any other .bit file, they don't. I am > clueless > >> now and i cannot find the problem. > > >> I need help here.. > > >> Thanks > >> regards > > >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 > >> Posted throughhttp://www.FPGARelated.com > > >Had this problem about four years ago. > >From memory, done is connected to both FPGAs with a single pull up. If > >you program one device using JTAG it lets go of done but the other > >unprogrammed device still pulls done low and config says that it has > >failed. > > >Program FPGA A. A lets go of done but B still pulls it low and the > >final bit of jtag says that it has failed (done is still low). > >Program FPGA B. B lets go of done which can now go high and B is > >configured correctly. > >Now program A again and it drives done low, configures, lets go of > >done and now knows that it has configured correctly. > > >Colin > > Colin, > i have already done that, no success. On some .bit files it gets > programmed,otherwise it doesn't. I saw in FPGA editor that xilinx XST > sometimes maps my signals on to INIT_B pad, was wondering if it could > create problems. I am not mapping any signal on the INIT_B pad, xilinx ma= ps > it i don't know why. > > > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com- Hide quoted text - > > - Show quoted text - Which signal is being mapped on to the INIT_B pad? And where did you constrain this signal to be LOC'ed to? You are using LOC constraints on all of your I/O right? Ed McGettigan -- Xilinx Inc.Article: 152194
>Which signal is being mapped on to the INIT_B pad? And where did you >constrain this signal to be LOC'ed to? > >You are using LOC constraints on all of your I/O right? > >Ed McGettigan >-- >Xilinx Inc. > It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And i am not using LOC constraints on all the IOs .. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152195
>Hi > >what about pacoblaze (open-source Verilog variant of PB?) > >Also JOP (something different, a hardware Java interpreter: >http://www.jopdesign.com) seems to be extensively tested. > >The Plasma MIPS from Opencores is also a tested design. > >Kind regards >Nikolaos Kavvadias > Thank you. I will test them. :-) --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152196
On Jul 18, 8:32=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > >Which signal is being mapped on to the INIT_B pad? =A0And where did you > >constrain this signal to be LOC'ed to? > > >You are using LOC constraints on all of your I/O right? > > >Ed McGettigan > >-- > >Xilinx Inc. > > It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And i am n= ot > using LOC constraints on all the IOs .. =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Creating a design to be downloaded into a board without fully LOC constraining all of the IO is just asking for trouble and can potentially damage the FPGA or another device on the board. You need to fix this ASAP and it will very likely resolve your original problem. Ed McGettigan -- Xilinx Inc.Article: 152197
>On Jul 18, 8:32=A0am, "salimbaba" ><a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: >> >Which signal is being mapped on to the INIT_B pad? =A0And where did you >> >constrain this signal to be LOC'ed to? >> >> >You are using LOC constraints on all of your I/O right? >> >> >Ed McGettigan >> >-- >> >Xilinx Inc. >> >> It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And i am n= >ot >> using LOC constraints on all the IOs .. =A0 =A0 >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > >Creating a design to be downloaded into a board without fully LOC >constraining all of the IO is just asking for trouble and can >potentially damage the FPGA or another device on the board. > >You need to fix this ASAP and it will very likely resolve your >original problem. > >Ed McGettigan >-- >Xilinx Inc. > okay i'll fix it and then update you. Thanks Regards --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152198
On Jul 19, 3:20=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Jul 18, 8:32=A0am, "salimbaba" > > <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > > >Which signal is being mapped on to the INIT_B pad? =A0And where did yo= u > > >constrain this signal to be LOC'ed to? > > > >You are using LOC constraints on all of your I/O right? > > > >Ed McGettigan > > >-- > > >Xilinx Inc. > > > It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And i am= not > > using LOC constraints on all the IOs .. =A0 =A0 > > > --------------------------------------- =A0 =A0 =A0 =A0 > > Posted throughhttp://www.FPGARelated.com > > Creating a design to be downloaded into a board without fully LOC > constraining all of the IO is just asking for trouble and can > potentially damage the FPGA or another device on the board. > > You need to fix this ASAP and it will very likely resolve your > original problem. > > Ed McGettigan > -- > Xilinx Inc. Ed's point is very much valid. You should fully Constrain all the IO signals in your design before you start implementation. I have faced this problem long back. Every board has specific pins for JTAG interface, but if you don't constrain your IOBs, it may end up in using these JTAG specific IO's by your normal logic IO signals. -- vasuArticle: 152199
Anyone familiar with SDXC host controller? I'm not getting the performance I need because I am getting too much delay between writes using CMD25. I'm trying to stream video, do I have to use CMD20 or ACMD23 or how to do I get the maximum performance?
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