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Messages from 152700

Article: 152700
Subject: macro
From: molka <molka.benromdhane@gmail.com>
Date: Tue, 4 Oct 2011 06:49:01 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello everybody,

I need help in dealling with hard macros (in vhdl). I want to
instantiate my macro in a vhdl design.

any one have an idea how to do it ? I tied to do as instantiating vhdl
modules but the synthesizer does not recognize my macro.

Plz help.

thanks in advance.

-------------------------
--Mlle Molka BEN ROMDHANE
--Doctorante Comelec
--Bureau : DA610
--e-mail: benromdh@enst.fr
--tel: 01 45 81 81 80
--------------------------

Article: 152701
Subject: Testbench
From: "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk>
Date: Tue, 04 Oct 2011 10:16:40 -0500
Links: << >>  << T >>  << A >>
I would like to write a testbench in VHDL using constrained random values
and transactions. Are there any free packages that people know about that
do this sort of thing?

TIA

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152702
Subject: Re: macro
From: KJ <kkjennings@sbcglobal.net>
Date: Tue, 4 Oct 2011 08:51:01 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 4, 9:49=A0am, molka <molka.benromdh...@gmail.com> wrote:
> Hello everybody,
>
> I need help in dealling with hard macros (in vhdl). I want to
> instantiate my macro in a vhdl design.
>
> any one have an idea how to do it ? I tied to do as instantiating vhdl
> modules but the synthesizer does not recognize my macro.
>
> Plz help.
>

You likely haven't included the file that has the VHDL component
definition for the hard macro.  Read the instructions for the hard
macro for how to go about including that in your project.

KJ

Article: 152703
Subject: Re: Testbench
From: KJ <kkjennings@sbcglobal.net>
Date: Tue, 4 Oct 2011 08:55:53 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 4, 11:16=A0am, "maxascent"
<maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
> I would like to write a testbench in VHDL using constrained random values
> and transactions. Are there any free packages that people know about that
> do this sort of thing?
>

For constrained randoms, you'll find one here...
http://www.synthworks.com/downloads/index.htm

KJ

Article: 152704
Subject: Re: FPGA acceleration v.s. GPU acceleration
From: Paul Colin Gloster <Colin_Paul_Gloster@ACM.org>
Date: Tue, 4 Oct 2011 18:13:50 +0100
Links: << >>  << T >>  << A >>
Someone sent on September 13th, 2011:
|---------------------------------------------------------------------|
|"[..]                                                                |
|                                                                     |
|As a conclusion, the FPGA acceleration only suits some certain and   |
|fixed application. However in the real world , many projects and many|
|algorithms are very uncertain and arbitrary. With same power         |
|consumption, GPU plan  may lead better results. For a concrete       |
|project, I will consider GPU or DSP, and FPGA at last.               |
|                                                                     |
|Do everybody agree?"                                                 |
|---------------------------------------------------------------------|

GPUs can outperform CPUs, but CPUs can outperform GPUs. It depends.

Article: 152705
Subject: Re: FPGA acceleration v.s. GPU acceleration
From: Tim Wescott <tim@seemywebsite.com>
Date: Tue, 04 Oct 2011 12:17:18 -0500
Links: << >>  << T >>  << A >>
On Tue, 04 Oct 2011 18:13:50 +0100, Paul Colin Gloster wrote:

> Someone sent on September 13th, 2011:
> |---------------------------------------------------------------------|
> |"[..]                                                                |
> |                                                                     |
> |As a conclusion, the FPGA acceleration only suits some certain and   |
> |fixed application. However in the real world , many projects and many|
> |algorithms are very uncertain and arbitrary. With same power         |
> |consumption, GPU plan  may lead better results. For a concrete       |
> |project, I will consider GPU or DSP, and FPGA at last.               |
> |                                                                     |
> |Do everybody agree?"                                                 |
> |---------------------------------------------------------------------|
> 
> GPUs can outperform CPUs, but CPUs can outperform GPUs. It depends.

It depends on the application -- a lot, and the company a little.

I've done a lot of work around (and sometimes even on) a system that does 
a lot of per-pixel video processing.  The actual algorithm is quite 
simple, but it needs to happen at video pixel rates, and the power 
dissipation needs to be low.  For that app, an FPGA doing the pixel-level 
work made lots of sense.  

For the version that I worked on, having a processor working hand-in-hand 
with the FPGA handling management tasks at the video line rate also made 
oodles of technical sense -- but ran afoul of some company political 
decisions (mostly a decision to maintain the illusion that a software guy 
who could handle "big box" GUI and communications interface stuff was the 
right guy to work on software that implemented a PLL at the video line 
rate).

For decisions that are even close to even-steven, being able to hire and 
manage a crew that can do the work becomes an important part of the mix 
-- which means that if you're trying to do this sort of thing in an all-
software company, a GPU solution may make oodles more sense than an FPGA 
solution, even if the FPGA solution is technically better.  Similarly, if 
the hard part of the algorithm needs to have a lot of interaction with 
the hardware, and if management is composed of circuit designers, then an 
FPGA solution may be a better choice even if the better technical 
solution would have been to use a GPU.

-- 
www.wescottdesign.com

Article: 152706
Subject: Re: FPGA acceleration v.s. GPU acceleration
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 4 Oct 2011 18:11:05 +0000 (UTC)
Links: << >>  << T >>  << A >>
Tim Wescott <tim@seemywebsite.com> wrote:
> On Tue, 04 Oct 2011 18:13:50 +0100, Paul Colin Gloster wrote:
>> Someone sent on September 13th, 2011:
                                                                     |
>> |As a conclusion, the FPGA acceleration only suits some certain and   |
>> |fixed application. However in the real world , many projects and many|
>> |algorithms are very uncertain and arbitrary. 
 
>> GPUs can outperform CPUs, but CPUs can outperform GPUs. It depends.

> It depends on the application -- a lot, and the company a little.

> I've done a lot of work around (and sometimes even on) a system that does 
> a lot of per-pixel video processing.  The actual algorithm is quite 
> simple, but it needs to happen at video pixel rates, and the power 
> dissipation needs to be low.  For that app, an FPGA doing the pixel-level 
> work made lots of sense.  

FPGAs work best when you need to do a huge number of small fixed
point operations, especially add/subtract/compare and some, but
not a huge number, of multiplies and divides.  The shifter needed
for floating point addition and subtraction is big, and limits the
use of FPGA for floating point work.

GPUs traditionally are designed to do a lot of single precision
floating point.  The use of the GPU for numerical processing takes
advantage of the economy of scale or building them for display use.

I have heard that there is discussion toward building GPUs to do
double precision, just for this purpose, though.

> For the version that I worked on, having a processor working hand-in-hand 
> with the FPGA handling management tasks at the video line rate also made 
> oodles of technical sense -- but ran afoul of some company political 
> decisions (mostly a decision to maintain the illusion that a software guy 
> who could handle "big box" GUI and communications interface stuff was the 
> right guy to work on software that implemented a PLL at the video line 
> rate).

> For decisions that are even close to even-steven, being able to hire and 
> manage a crew that can do the work becomes an important part of the mix 
> -- which means that if you're trying to do this sort of thing in an all-
> software company, a GPU solution may make oodles more sense than an FPGA 
> solution, even if the FPGA solution is technically better.  Similarly, if 
> the hard part of the algorithm needs to have a lot of interaction with 
> the hardware, and if management is composed of circuit designers, then an 
> FPGA solution may be a better choice even if the better technical 
> solution would have been to use a GPU.

-- glen

Article: 152707
Subject: Re: Testbench
From: backhus <goouse99@googlemail.com>
Date: Tue, 4 Oct 2011 23:55:12 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 4 Okt., 17:55, KJ <kkjenni...@sbcglobal.net> wrote:
> On Oct 4, 11:16=A0am, "maxascent"
>
> <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
> > I would like to write a testbench in VHDL using constrained random valu=
es
> > and transactions. Are there any free packages that people know about th=
at
> > do this sort of thing?
>
> For constrained randoms, you'll find one here...http://www.synthworks.com=
/downloads/index.htm
>
> KJ

Hi,
interesting link.

So, if we take VHDL, expand it  with some ADA for OOP-features and add
these packages (maybe after some improvements) and not to forget some
PSL like assertions,
all bundled in a new standard, what do we get?

SystemVHDL?

Looks like there is some need for it... ;-)

Have a nice Simulation
  Eilert

Article: 152708
Subject: Re: macro
From: backhus <goouse99@googlemail.com>
Date: Wed, 5 Oct 2011 00:02:03 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 4 Okt., 15:49, molka <molka.benromdh...@gmail.com> wrote:
> Hello everybody,
>
> I need help in dealling with hard macros (in vhdl). I want to
> instantiate my macro in a vhdl design.
>
> any one have an idea how to do it ? I tied to do as instantiating vhdl
> modules but the synthesizer does not recognize my macro.
>
> Plz help.
>
> thanks in advance.
>
> -------------------------
> --Mlle Molka BEN ROMDHANE
> --Doctorante Comelec
> --Bureau : DA610
> --e-mail: benro...@enst.fr
> --tel: 01 45 81 81 80
> --------------------------

Hi,
what synthesizer? You missed to mention.
There are many, and each dealing different with this.
If you have a real hard macro, consisting of a pre syntesized netlist,
the synthesis tool doesn't have to touch it at all.
Your instantiation will be recognized as a black box (that's how
Xilinx XST calls it, other tools may act differetn), and the Macro-
netlist will be added to your design at a later stage of the
implementation.
Provided that you have set the Macro-Path information correctly in the
tool properties.

Have a nice synthesis
  Eilert

Article: 152709
Subject: Re: Testbench
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Wed, 5 Oct 2011 11:03:15 +0000 (UTC)
Links: << >>  << T >>  << A >>
On Tue, 04 Oct 2011 23:55:12 -0700, backhus wrote:

> On 4 Okt., 17:55, KJ <kkjenni...@sbcglobal.net> wrote:
>> On Oct 4, 11:16 am, "maxascent"
>>
>> <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
>> > I would like to write a testbench in VHDL using constrained random
>> > values and transactions. Are there any free packages that people know
>> > about that do this sort of thing?
>>
>> For constrained randoms, you'll find one
>> here...http://www.synthworks.com/downloads/index.htm
>>
>> KJ
> 
> Hi,
> interesting link.
> 
> So, if we take VHDL, expand it  with some ADA for OOP-features and add
> these packages (maybe after some improvements) and not to forget some
> PSL like assertions,
> all bundled in a new standard, what do we get?
> 
> SystemVHDL?

YES! (Ada not ADA by the way)
Ada does at last seem to be increasing in popularity, and as of Ada-2005 
has gained flexibility over the 1995 revision (although VHDL-2008 beat 
Ada-2012 to conditional expressions :-)

And Ada has fixed-point types with user-defined ranges built in, so it 
should be ideal for algorithm accuracy simulation before conversion to 
hardware.

I'd like to go further with SystemVHDL though, and exploit the 
similarities between the SPARK subset* of Ada, and the synthesisable 
subset of VHDL. 

SPARK is not regarded as a subset but a new language with annotations, 
effectively contracts, in the form of Ada comments, such that any SPARK 
program is a fully compliant Ada program. It has restrictions imposed on 
it, such that a SPARK program is completely unambiguous, and can be 
formally proven to be error-free (e.g. guaranteed never to overflow an 
integer).

Now, firstly that approach to design verification appeals greatly to the 
hardware engineer in me.

But secondly, many of the restrictions SPARK places on Ada look 
remarkably like the restrictions you have to employ on VHDL if you want 
it to synthesise. For example, no dynamic storage allocation. 
SPARK goes a little further than most synthesis tools by prohibiting 
recursion, but the only synthesisable recursion I can recall is that cute 
"tree of gates" example (which most synth optimisers will generate from a 
linear chain of gates anyway). 

It's not a complete match, but close enough to make me speculate that 
there is some deep-seated commonality between the principles of 
provability (in finite time) and synthesisability (to finite hardware 
resource).

So I'm looking for Ada for OO testbenches and fixed point arithmetic for 
algorithm simulation, and SPARK-HDL, VHDL with SPARK annotations to 
formally prove as much as possible about the synthesisable design.

- Brian

Article: 152710
Subject: wireless module for DSP stratix III
From: "sato" <achraf26@n_o_s_p_a_m.gmail.com>
Date: Wed, 05 Oct 2011 06:58:27 -0500
Links: << >>  << T >>  << A >>
I am new to the world of Altera and FPGA . Really hope to get some helps
from this forum.

Thanks in advance!

My case is:
I have MCSOP running in my stratix III DSP board .

The outputs of the processing part of this system are displayed in the
screen .
I need the data until a base station from where I will transfer the data to
the internet.So how do I transfer (in realtime) the data until the base
station from the FPGA with wireless conection ?

Is there a solution to add wireless module to my DSP board and configure
with my PC in ad-hoc mode to capture this data ?

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152711
Subject: Re: Testbench
From: "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Wed, 05 Oct 2011 07:48:18 -0500
Links: << >>  << T >>  << A >>
[ elided ]

I must say that SystemVHDL appeals to me also.

As an aside, a few years ago, for testbenching purposes I required some
string/character functions such as 'is_whitespace' and found them in an Ada
function package that ModelSim compiled with minimal changes...
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152712
Subject: VHDL connection problem
From: "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk>
Date: Wed, 05 Oct 2011 08:35:57 -0500
Links: << >>  << T >>  << A >>
I have a memory that output a 64-bit slv. I have another module that has a
record type with a data 64-bit slv input. I want to connect the two
together. If I do this I get x. If I disconnect them the mem outputs what I
expect. I can also connect a constant to the record and see that value. Not
sure why I cant connect the two as I get no errors in modelsim.

TIA

J    	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152713
Subject: Spartan-6 PCI speed
From: "Finn S. Nielsen" <removethis_finnstadel@gmail.com>
Date: Wed, 05 Oct 2011 15:54:54 +0200
Links: << >>  << T >>  << A >>
Hello all,

Has anyone used XAPP1052 for testing the speed of the PCI hard macro in 
the spartan-6 LXT FPGAs ?

What speeds are you getting ?

Regards,

Finn S. Nielsen
Morphologic ApS
www.morphologic.dk

Article: 152714
Subject: Xilinx EDK: XPS netlist combination error
From: "Finn S. Nielsen" <removethis_finnstadel@gmail.com>
Date: Wed, 05 Oct 2011 16:09:19 +0200
Links: << >>  << T >>  << A >>

Hello all,

Does anyone know why I keep getting errors like this:

"
ERROR:EDK:708 - Can not get list of netlist files for core
xps_fb_img_xform 1.01.a .
  The pcore has a pre-synthesized netlist specified through BBD and the
list of parameter combinations listed for the instance in MHS does not
match any of the combinations in the BBD.
"

I've enclosed a file showign how the core entry looks like in the MHS 
file, as well as the cores BBD file contents.

Could it be something with directory paths and/or spaces or whatever.
There are no tab characters in the BBD file.

It's quite annoying.

MHS entry:
BEGIN xps_fb_img_xform
 PARAMETER INSTANCE = xps_fb_img_xform_0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x30070000
 PARAMETER C_HIGHADDR = 0x3007FFFF
 PARAMETER C_BUFFER_SIZE = 73728
 PARAMETER C_MPLB_NATIVE_DWIDTH = 32
 PARAMETER C_MPLB_P2P = 1
 PARAMETER C_FIFO_DEPTH = 1024
 BUS_INTERFACE MPLB = plb_32b
 BUS_INTERFACE SPLB = plb_64b
 BUS_INTERFACE SFB = white_balance_0_MFB
 BUS_INTERFACE MFB = xps_fb_img_xform_0_MFB
 PORT FB_Clk = x5_clk
 PORT FB_Rst = fb_rst
 PORT Core_Clk = x2_clk
 PORT Irq = xps_fb_img_xform_0_Irq
 PORT debug_x2 = xform_debug_x2
 PORT debug_x5 = xform_debug_x5
END



core BBD file contents:
C_FAMILY    C_BUFFER_SIZE  C_FIFO_DEPTH  C_MPLB_NATIVE_DWIDTH  FILES
virtex5     94208          512           32                    virtex5/afifo_27bx16d.ngc, virtex5/img_transf_buf.ngc, virtex5/pixel_fifo32x512.ngc
virtex5     94208          512           64                    virtex5/afifo_27bx16d.ngc, virtex5/img_transf_buf.ngc, virtex5/pixel_fifo64x512.ngc 
virtex5     94208          1024          32                    virtex5/afifo_27bx16d.ngc, virtex5/img_transf_buf.ngc, virtex5/pixel_fifo32x1024.ngc
virtex5     94208          1024          64                    virtex5/afifo_27bx16d.ngc, virtex5/img_transf_buf.ngc, virtex5/pixel_fifo64x1024.ngc
spartan6    73728          512           32                    spartan6/afifo_27bx16d.ngc, spartan6/img_transf_buf.ngc, spartan6/pixel_fifo32x512.ngc
spartan6    73728          512           64                    spartan6/afifo_27bx16d.ngc, spartan6/img_transf_buf.ngc, spartan6/pixel_fifo64x512.ngc 
spartan6    73728          1024          32                    spartan6/afifo_27bx16d.ngc, spartan6/img_transf_buf.ngc, spartan6/pixel_fifo32x1024.ngc
spartan6    73728          1024          64                    spartan6/afifo_27bx16d.ngc, spartan6/img_transf_buf.ngc, spartan6/pixel_fifo64x1024.ngc

Thanks all,
Finn S. Nielsen
Morphologic ApS
www.morphologic.dk



Article: 152715
Subject: Re: VHDL connection problem
From: "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Thu, 06 Oct 2011 03:00:12 -0500
Links: << >>  << T >>  << A >>
>I have a memory that output a 64-bit slv. I have another module that has
a
>record type with a data 64-bit slv input. I want to connect the two
>together. If I do this I get x. If I disconnect them the mem outputs what
I
>expect. I can also connect a constant to the record and see that value.
Not
>sure why I cant connect the two as I get no errors in modelsim.
>

Which tool is giving the problem?

Some synthesizers misinterpret your intentions unless you assign all of a
signal in one concurrent assignment statement (that is, not in an explicit
process).
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152716
Subject: Re: Xilinx EDK: XPS netlist combination error
From: "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Thu, 06 Oct 2011 03:03:40 -0500
Links: << >>  << T >>  << A >>
If no-one here answers you, try a at:

http://forums.xilinx.com/t5/EDK-and-Platform-Studio/bd-p/EDK
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152717
Subject: Re: VHDL connection problem
From: Thomas Stanka <usenet_nospam_valid@stanka-web.de>
Date: Thu, 6 Oct 2011 02:58:14 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 5 Okt., 15:35, "maxascent"
<maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
> I have a memory that output a 64-bit slv. I have another module that has a
> record type with a data 64-bit slv input. I want to connect the two
> together. If I do this I get x. If I disconnect them the mem outputs what I
> expect. I can also connect a constant to the record and see that value. Not
> sure why I cant connect the two as I get no errors in modelsim.

X means you have 2 or more active driver on a signal driving different
values. Replace the std_logic_vector by std_ulogic_vector to detect in
compile time your problem.
Modelsim can't throw error, as your code is legal vhdl according to
lrm (but most likely useless/not what you like to get)  and modelsim
simulates it correct.

bye Thomas

Article: 152718
Subject: Re: VHDL connection problem
From: "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk>
Date: Thu, 06 Oct 2011 05:36:16 -0500
Links: << >>  << T >>  << A >>
Thanks for the help. I actually had something else driving the signal.

J	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 152719
Subject: Is it possible to use a remote desktop viewer on NIOS Linux
From: Ahmed Abdelfattah <ahmed.abdelfattah.elshemisy@gmail.com>
Date: Sat, 8 Oct 2011 08:34:55 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello ,
I am having a project where I need to take control of a pc or a smart
phone which has a VNC server using FPGA so I need to run a client from
the FPGA side . Is this possible ?
My kit is the terasic de2-115 .It has USB controller chip and Ethernet
connections .

Article: 152720
Subject: Re: MAXDELAY constraint
From: Guy Eschemann <Guy.Eschemann@gmail.com>
Date: Sun, 9 Oct 2011 05:19:49 -0700 (PDT)
Links: << >>  << T >>  << A >>
Andrew,

here are a few things that you could try:

- Look-up the placements of the BUGMUX and its driving element on an implem=
entation run that meets timing and fix these placements for subsequent runs=
 using LOC constraints in your UCF file. You can either use the FPGA editor=
 or PlanAhead to look-up the placements.

- Try SmartGuide, using an implemented design that meets timing as a refere=
nce.

- Try using a different MAP/PAR cost table. Setup the SmartXPlorer to itera=
te through 15 or so cost tables, and compare the results.

Hope that helps,

Guy Eschemann
FPGA Consultant
Karlsruhe, Germany
http://www.ingenieurbuero-eschemann.de




Article: 152721
Subject: high speed place and route about xilinx
From: "bjzhangwn@gmail.com" <bjzhangwn@gmail.com>
Date: Sun, 9 Oct 2011 07:49:12 -0700 (PDT)
Links: << >>  << T >>  << A >>
Now I am troubled that I must wait several hours  to compile large
circuits,and the place and route result is different from each
time,for example the p&r time for this time is may be 2hrs and may be
5 or 6 hrs next time only becase of little change,can some give me
some tips or advice ,thks.

Article: 152722
Subject: Re: high speed place and route about xilinx
From: BobH <wanderingmetalhead.nospam.please@yahoo.com>
Date: Sun, 09 Oct 2011 12:19:27 -0700
Links: << >>  << T >>  << A >>
On 10/9/2011 7:49 AM, bjzhangwn@gmail.com wrote:
> Now I am troubled that I must wait several hours  to compile large
> circuits,and the place and route result is different from each
> time,for example the p&r time for this time is may be 2hrs and may be
> 5 or 6 hrs next time only becase of little change,can some give me
> some tips or advice ,thks.

I am using version 11.5, so your setup may be different. The next time 
you get a run that completes in an acceptable time and meets your timing 
constraints, save the console output to a file. Look through the place 
and route area of the log and there should be information about the 
placement choices made in this run. There is a comment in the log file 
about using that output for constraining the place and route of future 
runs. I have not tried this method, but have seen the stuff in the log 
files along with the instructions (terse). I assume that you could 
manually cut the constraint information from the log file with a text 
editor and paste it into the .ucf file that has your pin and timing 
constraints in it.

Good Luck,
BobH

Article: 152723
Subject: Re: high speed place and route about xilinx
From: nico@puntnl.niks (Nico Coesel)
Date: Mon, 10 Oct 2011 07:08:49 GMT
Links: << >>  << T >>  << A >>
"bjzhangwn@gmail.com" <bjzhangwn@gmail.com> wrote:

>Now I am troubled that I must wait several hours  to compile large
>circuits,and the place and route result is different from each
>time,for example the p&r time for this time is may be 2hrs and may be
>5 or 6 hrs next time only becase of little change,can some give me
>some tips or advice ,thks.

Check your constraints. See if the constraints cover what you think
they should cover. 

Having everything on a high speed clock usually is a bad idea. I
usually use the DCM to create lower frequency clocks to feed low speed
logic. Because the clock edges are still aligned the clock domain
crossing issues aren't that severe.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

Article: 152724
Subject: Re: high speed place and route about xilinx
From: saardrimer@gmail.com
Date: Mon, 10 Oct 2011 09:38:55 -0700 (PDT)
Links: << >>  << T >>  << A >>
Are you meeting timing? If so, reduce the effort level for map / par so it =
doesn't "try harder" for nothing. In fact, I've seen higher effort settings=
 produce worse results, and take longer to run, than lower effort levels fo=
r the same design, so it might be worth a try even if you're not meeting ti=
ming! (Results depends on the version of tools, your code, constraints, etc=
.)



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