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On Nov 5, 10:14=A0pm, Mark McDougall <ma...@vl.com.au> wrote: > I've had it up to the eyeballs with Xilinx tools now. I'm seriously ready > to go postal in the lobby of Xilinx HQ. I don't expect perfection but thi= s > really is beyond a joke. > > Can someone please put me out of my misery, and finally admit that you > have _all_ been having me on for the past few years now! :O ...that it ha= s > all been an elaborate hoax instigated by someone I offended in a past > life. ...that a team of engineers has been working for years to produce a= n > IDE that crashes randomly, and steadfastly refuses to launch tools on > Tuesday mornings and Friday afternoons? ...working for years on a > synthesizer that removes random bits of logic, or sits spinning in an > infinite loop on an entity that works in another project? ...that corrupt= s > my project file bi-monthly. > > And worst of all - _you_ lot, telling me that Xilinx actually works, and > that you _can_ use it for more than flashing LEDs on the Spartan starter > kit. And I was gullible enough to believe you! :O :( > > I've seen the light. You _cannot_ convince me that it is possible to > produce a commercial product in silicon using these tools. Period. > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266 I thought that they fixed the problem by using the "entitle now" software for downloading. ;) If you can't download the software, you can't find the bugs. And even if you -think- you've downloaded it, they can always claim that you had a network issue. Sadly, Xilinx is writing software that Americans will buy. Features are more important than robustness. Flash is more important than function. Sigh. AL PS: I too have given up on the GUI. I use it -once- per project to get the initial setup, the rest of the time I use makefiles and scripts.Article: 144001
On 11=E6=9C=885=E6=97=A5, =E4=B8=8A=E5=8D=885=E6=97=B637=E5=88=86, John Ada= ir <g...@enterpoint.co.uk> wrote: > There are a lot of ways to achieve logic size reductions I have seen > reductions of 30-50% on customer designs achieved here with a lot of > expert knowledge but does depend on the original design. So starting > with the some simple things: > > (1) Play with state machine encoding selection - changing a 1-hot to > sequential can save a lot. > (2) Play with speed and size settings. They don't always do exactly as > the name suggests. > (3) In the Xilinx mapping make sure you have setting to use i/o > registers. > (4) Consider SRL16 to replace shift register chains. Removing a reset > term will often let the synthesiser do this for you. Can save a lot. > > Beyond these simply looking at how the design is implemented and > restructuring can save more but that is a much more complex subject. > Try the simple first as you don't need much. > > John Adair > Enterpoint Ltd. - Home of Craignell. The DIL FPGA Module. > > On 4 Nov, 14:27, "bjzhan...@gmail.com" <bjzhan...@gmail.com> wrote: > > > > > Hi,recently,I receive a task to add another new function to the > > project previously finished,but the problem is that the old project > > have consume about 5K of total 7K LUTs,and the new function need about > > 2.5K LUTs,so I must optimize the old logic but I have no idea,can > > someone give some advice about the logic optimization,the chip is > > spartan3,the synthesis tool is synplify9.4 pro,P&R tool is 10.1.- =E9= =9A=90=E8=97=8F=E8=A2=AB=E5=BC=95=E7=94=A8=E6=96=87=E5=AD=97 - > > - =E6=98=BE=E7=A4=BA=E5=BC=95=E7=94=A8=E7=9A=84=E6=96=87=E5=AD=97 - Thanks,I have done all the things listed above,but when map the design,log file indicate that not all FFs can be mapped,the total FFs is 5K,total LUTs is 6k,but the total slice is more than 7K,so I think not all the logic cell contain both FF and LUT,some LE contains only LUT and some LE contains only FF,What I want to know is that in what circunstance the LE can't contain both the FF and LUT,What should I consider when I do the plan and select the right device number,and when I add new function(as 2K LUT 1K FFs), how should I know if the old project can add the new function(left 3k lut free and 1k ff free but )?I want to know the more detail ,pls give me some advice or wp,3x.Article: 144002
On Nov 6, 6:35=A0pm, rickman <gnu...@gmail.com> wrote: > On Nov 6, 4:47=A0am, -jg <jim.granvi...@gmail.com> wrote: > > > > > > > On Nov 6, 6:01=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > > > ok some explanations: I was talking PSoC 3, yes, and it > > > HAS VERILOG programmable general purpose CPLD module! > > > I have tested the software and it uses cypress warp compiler > > > the missing "selection" guide is really PITA, I was trying to compare > > > the PSoC 1 versions, and just did give up! > > > The PSoC3 has some nice looking features, and I see it has an errata, > > so real silicon is edging closer.... > > > > Ok, from my point, Cypress could drop ALL their products and just > > > keep PSoC 3 :) > > > Not at the prices they are indicating at the moment! > > You have to really need a good portion of all the resource, > > to be able to justify the costs. > > > That's always been the achilles heel =A0of such 'System on Chip' pitche= s > > Where did you find prices? > > Rick pricing is when you look the order pages, from 12 to 16$ qty 1, cypress online shop but only 3 devices are shipping, so most of the devices do not have price visible AnttiArticle: 144003
On Nov 6, 12:10=A0pm, Antti <antti.luk...@googlemail.com> wrote: > On Nov 6, 6:35=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > On Nov 6, 4:47=A0am, -jg <jim.granvi...@gmail.com> wrote: > > > > On Nov 6, 6:01=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > > > > ok some explanations: I was talking PSoC 3, yes, and it > > > > HAS VERILOG programmable general purpose CPLD module! > > > > I have tested the software and it uses cypress warp compiler > > > > the missing "selection" guide is really PITA, I was trying to compa= re > > > > the PSoC 1 versions, and just did give up! > > > > The PSoC3 has some nice looking features, and I see it has an errata, > > > so real silicon is edging closer.... > > > > > Ok, from my point, Cypress could drop ALL their products and just > > > > keep PSoC 3 :) > > > > Not at the prices they are indicating at the moment! > > > You have to really need a good portion of all the resource, > > > to be able to justify the costs. > > > > That's always been the achilles heel =A0of such 'System on Chip' pitc= hes > > > Where did you find prices? > > > Rick > > pricing is when you look the order pages, from 12 to 16$ qty 1, > cypress online shop > but only 3 devices are shipping, so most of the devices do not have > price visible When I searched I didn't find anything starting with CY8C3. Maybe you need a full part number. Regardless, I don't care so much about the 8051. I am interested in the ARM Cortex M3 version if they have dual (stereo) ADC and DAC. If I have to add a CODEC to the chip to use it what's the point? RickArticle: 144004
On Fri, 6 Nov 2009 13:01:19 +0000 Oscar Almer <o.almer@gmail.com> wrote: > On Fri, 06 Nov 2009 17:14:21 +1100 > Mark McDougall <markm@vl.com.au> wrote: > > > I've had it up to the eyeballs with Xilinx tools now. I'm seriously > > ready to go postal in the lobby of Xilinx HQ. I don't expect > > perfection but this really is beyond a joke. > > > > Can someone please put me out of my misery, and finally admit that > > you have _all_ been having me on for the past few years > > now! :O ...that it has all been an elaborate hoax instigated by > > someone I offended in a past life. ...that a team of engineers has > > been working for years to produce an IDE that crashes randomly, and > > steadfastly refuses to launch tools on Tuesday mornings and Friday > > afternoons? ...working for years on a synthesizer that removes > > random bits of logic, or sits spinning in an infinite loop on an > > entity that works in another project? ...that corrupts my project > > file bi-monthly. > > > > And worst of all - _you_ lot, telling me that Xilinx actually works, > > and that you _can_ use it for more than flashing LEDs on the Spartan > > starter kit. And I was gullible enough to believe you! :O :( > > > > I've seen the light. You _cannot_ convince me that it is possible to > > produce a commercial product in silicon using these tools. Period. > > > > I, at least, gave up on the ise wrapper about a year and a half ago - > it just didn't do it, anymore. Instead I drive the flow (xst, map, > par, etc) from a single makefile, and a short one at that - maybe 20 > lines. > > The things I know im missing out on is 1. the pretty XML reports and > 2. COREgen etc hook-ins. The former I can survive without, as its > easier to grep through plain text reports anyway, and the latter I > typically only need to run once anyway, at which point I suffer ise > long enough to move the generated files somewhere sensible. > > Just my experience. > > //Oscar > Hear hear. I've had very little trouble with the backend Xilinx tools, but the GUI is absolute rubbish. Crashes constantly, takes PHENOMINAL amounts of memory just to exist, and every release moves all of the important options to somewhere new and exciting. I looked into using TCL instead, but that just hides things inside of more magic boxes. Makefiles just work; I switched over around ISE 8 and have never thought of regretting it. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 144005
rickman wrote: > The reason for using commercial tools is supposed to be the great > support and the lack of serious bugs... so if you don't like your > expensive layout tools, why use them? I used FreePCB on my last > project and found it very suitable. I am sure there are some things > that you need to do manually that expensive tools might do > automatically, but hand checking all the nets is not one of them. > > Not trying to be smart, this is a serious question. > > Rick Good question. Mostly inertia. If FreePCB will import our libraries and designs, I'll check it out in a minute. Maintenance is an issue. We are in the medical racket. Product lifetimes can be a dozen years or more. We are still shipping product with XC3142's in them. When parts go obsolete, we often need to quick turn a board to keep shipping product. That means either we keep the tools around for the duration, or find something that can read the files. Most of my new designs are more or less 50% original and 50% cut and pasted from previous designs. It saves a bit of time not having to recreate parts and redraw schematics. I've used Pads, Tango, Calay, Cadroid, Orcad, and a few other packages over the years. Some were better than others, but all of them had problems of one sort or another. I've kind of got to the point where if my PC doesn't catch fire after I install a new version, I consider it a victory. CurtArticle: 144006
Hi folks, we just finished publishing the fall edition of Xcell Journal, which has a cover story focus on the expanding role of FPGAs in the Global Information Grid. The issue also has a lot of great methodology and how-to content. We're now making it available in a one- click download as well as in the Ceros (flash) format. I hope you enjoy it. http://www.xilinx.com/publications/xcellonline/index.htmArticle: 144007
Mark McDougall wrote: > And worst of all - _you_ lot, telling me that Xilinx actually works, and > that you _can_ use it for more than flashing LEDs on the Spartan starter > kit. And I was gullible enough to believe you! :O :( > > I've seen the light. You _cannot_ convince me that it is possible to > produce a commercial product in silicon using these tools. Period. Umm, we have been developing stuff for some time for mostly in-house use here at Washington University, mostly using Virtex 2 stuff here. I also have been doing some very UN-challenging units on both CPLDs and Spartan 2E FPGAs at Pico Systems, my "night job". You can see some of the products I have developed at http://pico-systems.com/oscrc4/catalog/index.php?cPath=3 for CNC motion control. Most of the boards on that page have either a CPLD or an FPGA in them. I have mostly moved development (at both sites) over to Linux and iSE 10.1. I do have an annoying problem where you can't print schematics without some fooling around, but otherwise it seems to work well. I only use schematics now on some interface-type CPLDs, so that's no big deal. I still find their modelsim simulator cumbersome to use, but I live with it. I understand they are phasing out the timing diagram entry for sim stimulus, and I really prefer that to writing the test bench in words. Now, I have to admit, most of this stuff is NOT pushing the chips to the ultimate. I am using 40 MHz clocks on the Spartan 2E, for instance! I do have a CPLD design wehre I used every FF and every macrocell, and any time I want to change something it is a great hassle, but it does get it routed. I have sold about 180 of the motion controller boards, so it is real production to ME, at least! JonArticle: 144008
Synplify Premier includes physical synthesis for Xilinx, which does graph based placement while synthesizing. It knows about all the routing resources and can place logic accordingly. It forwards a boatload of location constraints to the placer. I evaluated it a couple years ago and it didn't work, there was some lack of communication between synthesis and ISE. I'll be using it again in a couple months, this time on big v6 parts. Thanks for the comments everyone. My FPGA work is mainly ASIC emulation, so no IP blocks, no particular PCB concerns (most FPGA I/O is connected to other FPGAs). I just know that the ASIC implementation team spends a lot of time floorplanning, and I was wondering if there was any benefit to applying that to the FPGA. Someone else mentioned the smartguide option... I use this all the time. It cut P&R runtime from 18 hours down to 6 on a 92% full V5 LX330 design. When I get a design that routes successfully and has good timing I keep it and use it to guide the next placement. regards, --steve "rickman" <gnuarm@gmail.com> wrote in message news:a53d433a-97a2-4d7e-a9c2- I wasn't aware that any of the third party tools did *any* placement. I thought they just produced a net list of the primitives and let the Xilinx place and route tools do all of that. Am I mistaken? RickArticle: 144009
I was wondering if someone has tried this and has numbers? Any comparison with PPC440 in V5 would also be very much appreciated? Thanks, /MikhailArticle: 144010
On Nov 7, 6:10=A0am, Antti <antti.luk...@googlemail.com> wrote: > > pricing is when you look the order pages, from 12 to 16$ qty 1, > cypress online shop > but only 3 devices are shipping, so most of the devices do not have > price visible Correct, and when you ratio their other sample prices, to their medium volume prices, you get an indication of $6-8+ - a price that is getting up there... -jgArticle: 144011
I guess I asked a stupid question. I should have started with asking when MB core is going to be made available for V6? I've just tried creating a V6 system in EDK11.3 and found that there are no processors in the IP catalog... /MikhailArticle: 144012
On Nov 7, 4:54=A0am, Curt Johnson <curt.john...@dicombox.net> wrote: > If it is any solace, the Mentor schematic capture and PCB routing tools > are much worse. In addition to continuous license issues, crashes, > version compatibility problems, and file corruption, they produce > unreliable output. I now have to manually check every trace on a 10 > layer PCB with multiple BGA packages ever since we discovered that the > tools can randomly delete nets from a fully routed board without warning. Err, but a random-deleted net is actually easy to find, as you usually have more than one copy (as in, in the SCH, or even in a copy of the PCB ) ? Which Mentor flows/versions are you using ?Article: 144013
I'd pretty much agree with other comments and say I use it as a last resort tool. The problems when parts are changed make it a problem. That all said we used floorplanning in conjunction with FPGA Editor some years ago to achieve our 10Gbit CRC32 IP in relative slow Virtex- II fabric. That particular design has 3 levels of LUTs in some of it and had to run at 300Mhz+. We got down to identifying individual inputs of the LUT to use in interconnecting logic in some cases to make go quick enough. A long job but in the end successful. I would always play with synthesis, map and P&R options before using floorplanning for these reasons. I would also look at the worst areas in the design too and see if the design could change to sort a timing issue that way. Using the multiple P&R seeds is often worth one or two nS. John Adair Enterpoint Ltd. On 5 Nov, 19:56, "Steve Ravet" <steve.ra...@arm.com> wrote: > Do any of you advanced users ever use the floorplanning tools to do > placement? =A0I'm not talking about placing clock buffers or other indivi= dual > items, I'm talking about ASIC style floorplanning for units and sub-units= . > I've asked AE's about that and the response is always to let the tool do > placement. =A0So I'm asking experts: =A0Do you ever floorplan, and if so = why? > To speed up map? =A0To help with timing? =A0Thanks for any insight, > > --steveArticle: 144014
On Nov 7, 1:10=A0am, "MM" <mb...@yahoo.com> wrote: > I guess I asked a stupid question. I should have started with asking when= MB > core is going to be made available for V6? I've just tried creating a V6 > system in EDK11.3 and found that there are no processors in the IP > catalog... > > /Mikhail you can sometimes enable "early access" support, by changing some things in the EDK, or just be adding the new family to the MPD files AnttiArticle: 144015
On Nov 6, 8:01=A0pm, Oscar Almer <o.al...@gmail.com> wrote: > On Fri, 06 Nov 2009 17:14:21 +1100 > > > > Mark McDougall <ma...@vl.com.au> wrote: > > I've had it up to the eyeballs with Xilinx tools now. I'm seriously > > ready to go postal in the lobby of Xilinx HQ. I don't expect > > perfection but this really is beyond a joke. > > > Can someone please put me out of my misery, and finally admit that you > > have _all_ been having me on for the past few years now! :O ...that > > it has all been an elaborate hoax instigated by someone I offended in > > a past life. ...that a team of engineers has been working for years > > to produce an IDE that crashes randomly, and steadfastly refuses to > > launch tools on Tuesday mornings and Friday afternoons? ...working > > for years on a synthesizer that removes random bits of logic, or sits > > spinning in an infinite loop on an entity that works in another > > project? ...that corrupts my project file bi-monthly. > > > And worst of all - _you_ lot, telling me that Xilinx actually works, > > and that you _can_ use it for more than flashing LEDs on the Spartan > > starter kit. And I was gullible enough to believe you! :O :( > > > I've seen the light. You _cannot_ convince me that it is possible to > > produce a commercial product in silicon using these tools. Period. > > I, at least, gave up on the ise wrapper about a year and a half ago - > it just didn't do it, anymore. Instead I drive the flow (xst, map, par, > etc) from a single makefile, and a short one at that - maybe 20 lines. > > The things I know im missing out on is 1. the pretty XML reports and 2. > COREgen etc hook-ins. The former I can survive without, as its > easier to grep through plain text reports anyway, and the latter I > typically only need to run once anyway, at which point I suffer ise > long enough to move the generated files somewhere sensible. > > Just my experience. > > //Oscar I used to do the same. And I still use the scripts when I just need to recompile the entire thing because of an RTL change in my code. But, since ISE 11, I have started to create MPD files and use EDK to put together the system. The GUI is now (for me at least) very stable, and reasonable easy to use. (This is all on linux). I am even starting to support the EDK plugin for most of our IP cores, as it seems to be actually working pretty well now. Regards, rudiArticle: 144016
I've been eavesdropping on this interesting C4 / S6 discussion. Anyone have any idea (and willing to share) how many developers are chopping and choosing between Xilinx and Altera (and other FPGAs) for different projects? Are people doing this switching, or are they finding their "ideal" FPGA provider and sticking with this? Michael.Article: 144017
Michael <m.pont@rapiditty.co.uk> writes: > different projects? Are people doing this switching, or are they > finding their "ideal" FPGA provider and sticking with this? I think the latter is quite common since many will fall into the trap of using proprietary IP from a given vendor like NIOS/Microblaze, Megawizard/Coregen components, specific IO macros, certain PLL configurations, package options, programming solutions, etc. Also there is some investment in learning the vendor provided tools, even though if you know one it's easier to learn the another. Being able to switch in the middle of the development cycle, or even between projects requires a bit of planning, e.g. using a vendor independent soft CPU and structuring your HDL so the vendor dependant parts are in separate modules or use wrappers. This planning can of course be an advantage if you at any point would migrate to lets say an ASIC or a new FPGA vendor with some great features. When you first start using FPGA's the differences mentioned above does not seem obvious since there is so much new stuff to learn. You will focus on getting your part up as quickly as possible and that typically involves prototyping using a dev kit from a given vendor and use as much ready IP (which is often vendor dependent) as possible. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 144018
On Thu, 5 Nov 2009 13:56:22 -0600, "Steve Ravet" <steve.ravet@arm.com> wrote: >Do any of you advanced users ever use the floorplanning tools to do >placement? I'm not talking about placing clock buffers or other individual >items, I'm talking about ASIC style floorplanning for units and sub-units. >I've asked AE's about that and the response is always to let the tool do >placement. So I'm asking experts: Do you ever floorplan, and if so why? >To speed up map? To help with timing? Thanks for any insight, I last seriously tried floorplanning in the ISE 6.3 era. (And previously in 3.1). My approach then was to try floorplanning significant blocks (e.g. multipliers in logic), and save them as black boxes with RLOCs, then incorporate them in larger blocks (e.g. interpolators) in a hierarchical manner, and so on, until the remaining logic would auto-place as I wanted. This was using Floorplanner (not PlanAhead), and saving as relatively placed modules (large UCF files full fo RLOCs). Conclusions then: (a) hierarchical floorplanning worked, sort of, IF you could step oh so carefully around all the bugs not just in Floorplanner but in the back end tools as well. (b) It must have been almost completely untested, judging by the number and type of bugs I was finding. (c) You had to flatten each level of hierarchy after floorplanning, ending up with one huge UCF file of RLOCs to use at the next level up but... (d) performance on a large block increased from 80 to 130MHz. Then... (e) it would degrade again if you packed several such blocks together, apparently due to routing straying outside one block increasing congestion in its neighbour. "Guard bands" between them helped, but waste space... I got about half my design running well in a hierarchical floorplanned manner, in several weeks (about 75% chasing bugs), before I couldn't dedicate (waste?) any more time on the project. And I haven't made time to try again with newer releases, to see how Floorplanner has improved, or if PlanAhead is better. Short answer then was: left alone, the tools leave at least 30% of possible speed on the table, but to do better on a large design would be a lot of work. (I guess that sort of work may be worthwhile in ASIC design, and the tools support it better) You may argue that experience from so long ago isn't worth describing; but other comments here suggest things aren't much better today. The bugs can be worked around, then fixed. But if packing the fast blocks together still loses their performance, it really isn't worthwhile (except for specific purposes, e.g. around hard IP like DSPs, or to fix specific instances of poor auto-placement. One placement approach I have successfully used is to let the tools do their thing and JUST fail to meet timing (say 50 or fewer timing errors). Then examine the timing report; typically all 50 errors are related to one FF or LUT in an obviously stupid place. Use FPGA editor to move it, and run reentrant PAR to fix the offending routes. Quick, easy, and about half the time, effective. Of course the GUI-based reentrant flow in ISE10 was set up to delete the old file, run PAR reentrant, and fall over because the old file was missing... - BrianArticle: 144019
On Nov 7, 6:10=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > One placement approach I have successfully used is to let the tools do th= eir > thing and JUST fail to meet timing (say 50 or fewer timing errors). Yep > Then examine > the timing report; typically all 50 errors are related to one FF or LUT i= n an > obviously stupid place. Use FPGA editor to move it, and run reentrant PAR= to fix > the offending routes. > In that situation, I'll first look into ways of changing the logic in the source code to effectively breaks up the long path or remove unneeded signal dependencies and I may never hear from that timing path again regardless of fitter placement. If that doesn't cut it, turning loose the fitter to vary the synthesis and fitter settings and seeds and such is rather painless and generally comes back with better settings that stand up to future design iterations. KJArticle: 144020
I'm trying to look into the status of free software/open source efforts relating to FPGA (because rms asked me to). After searching in this group, wikipedia, etc., the one I've been able to find is slipway/abits from Adam Megacz (Adam, are you still here?), but from checking out the sources it seems development stalled a while back, understandably enough since I gathered from the last post I saw about it that the manufacturer didn't have much interest in the hardware any more. Are there any other ongoing projects? Any info greatly appreciated. Thanks in advance. Karl Berry (karl /at/ gnu /dot/ org)Article: 144021
On Nov 7, 7:53=A0pm, Karl Berry <kberr...@gmail.com> wrote: > I'm trying to look into the status of free software/open source > efforts relating to FPGA (because rms asked me to). > > After searching in this group, wikipedia, etc., the one I've been able > to find is slipway/abits from Adam Megacz (Adam, are you still here?), > but from checking out the sources it seems development stalled a while > back, understandably enough since I gathered from the last post I saw > about it that the manufacturer didn't have much interest in the > hardware any more. > > Are there any other ongoing projects? =A0Any info greatly appreciated. > Thanks in advance. > > Karl Berry (karl /at/ gnu /dot/ org) AT40/AT94 is the only family with open bitstream information, unfortunatly AnttiArticle: 144022
Mark McDougall <markm@vl.com.au> wrote:
>I've had it up to the eyeballs with Xilinx tools now. I'm seriously ready
>to go postal in the lobby of Xilinx HQ. I don't expect perfection but this
>really is beyond a joke.
>
>Can someone please put me out of my misery, and finally admit that you
>have _all_ been having me on for the past few years now! :O ...that it has
>all been an elaborate hoax instigated by someone I offended in a past
>life. ...that a team of engineers has been working for years to produce an
>IDE that crashes randomly, and steadfastly refuses to launch tools on
>Tuesday mornings and Friday afternoons? ...working for years on a
>synthesizer that removes random bits of logic, or sits spinning in an
>infinite loop on an entity that works in another project? ...that corrupts
>my project file bi-monthly.
>
>And worst of all - _you_ lot, telling me that Xilinx actually works, and
>that you _can_ use it for more than flashing LEDs on the Spartan starter
>kit. And I was gullible enough to believe you! :O :(
>
>I've seen the light. You _cannot_ convince me that it is possible to
>produce a commercial product in silicon using these tools. Period.
Its about time someone writes a decent Eclipse plugin / makefile
generator.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
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Article: 144023On Sat, 7 Nov 2009 07:34:05 -0800 (PST), KJ <kkjennings@sbcglobal.net> wrote: >On Nov 7, 6:10 am, Brian Drummond <brian_drumm...@btconnect.com> >wrote: > >> One placement approach I have successfully used is to let the tools do their >> thing and JUST fail to meet timing (say 50 or fewer timing errors). > >Yep > >> Then examine >> the timing report; typically all 50 errors are related to one FF or LUT in an >> obviously stupid place. Use FPGA editor to move it, and run reentrant PAR to fix >> the offending routes. >> > >In that situation, I'll first look into ways of changing the logic in >the source code to effectively breaks up the long path or remove >unneeded signal dependencies and I may never hear from that timing >path again regardless of fitter placement. Agreed that is often a better option. I wasn't very clear; I have seen this happen on one signal, exactly like 2^8 other signals which meet timing, except this has one FF placed at X99Y99 in the opposite corner to the rest of the block. (I'm only exaggerating slightly!) In that case moving the errant FF can be faster than a new placement, and certainly less disruptive than a redesign. As you say, another PAR seed (or try 5 with a home-scripted MPPR), or even an unrelated design change, can also make the problem go away. In this situation, placement is just one more tool in the box. And maybe less useful than it was with earlier tool versions. - BrianArticle: 144024
Karl Berry schrieb: > I'm trying to look into the status of free software/open source > efforts relating to FPGA (because rms asked me to). > > After searching in this group, wikipedia, etc., the one I've been able > to find is slipway/abits from Adam Megacz (Adam, are you still here?), > but from checking out the sources it seems development stalled a while > back, understandably enough since I gathered from the last post I saw > about it that the manufacturer didn't have much interest in the > hardware any more. > > Are there any other ongoing projects? Any info greatly appreciated. > Thanks in advance. Waht exactly are you looking for? Synthesis? Place & Route? While Icarus Verilog is mostly aimed at simulation AFAIR XNF and EDIF synthesis work. While the Icarus FAQ only mentions using Xilinx tools for subsequent Place & Route, AFAIR someone wrote (rather primitive and inefficient) tools for those steps, too and was able to get a simple design onto a Xilinx FPGA that way. Philipp
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