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>I'm not sure what part is giving you trouble. Without giving away the answe= >r, think about using some combination of appropriately triggered counters. = >Try walking through your problem (on paper) for various amounts of input da= >ta - then it should become obvious how when you should trigger various even= >ts and how much the counters will count to before they trigger something el= >se. > >Chris > OK I think I have gotten it, well sort of. I found a good example for driving a VGA monitor. I have modified it, but I keep getting the following errors: Line 32. The type of the element in aggregate does not correspond to any array type. Line 44. The type of the element in aggregate does not correspond to any array type. Line 32 is: if (h_counter => "0111100010") and (h_counter <= "1000001011") then Line 44 is: if (v_counter => "0100010010") and (v_counter <= "0100011100") then What am I doing wrong? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150526
>I'm not sure what part is giving you trouble. Without giving away the answe= >r, think about using some combination of appropriately triggered counters. = >Try walking through your problem (on paper) for various amounts of input da= >ta - then it should become obvious how when you should trigger various even= >ts and how much the counters will count to before they trigger something el= >se. > >Chris > OK I think I have gotten it, well sort of. I found a good example for driving a VGA monitor. I have modified it, but I keep getting the following errors: Line 32. The type of the element in aggregate does not correspond to any array type. Line 44. The type of the element in aggregate does not correspond to any array type. Line 32 is: if (h_counter => "0111100010") and (h_counter <= "1000001011") then Line 44 is: if (v_counter => "0100010010") and (v_counter <= "0100011100") then What am I doing wrong? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150527
On 1/25/2011 6:36 AM, Thomas Stanka wrote: > Your description ring my "clock domain" alarm bell. > You should ensure that every clock domain crossing is right, which > implies that you first need to identifiy all different clock domains. > Every input that is not synchron to your clock and proper constraint > is a different clock domain which requires appropriate handling of > these inputs. Internal clocks on the same frequency can form different > clock domains in case clock tree is splitted. This is easy seen in > netlist but sometimes not obvious in RTL code. Or maybe there is a stray latch or asych process hiding somewhere... -- MikeArticle: 150528
On Jan 25, 8:44=A0am, Chris Maryan <kmar...@gmail.com> wrote: > RTFM is the universal answer for all of this. There may be some tutorials= , but they likely won't cover the particular LCD you are using - that said,= try Googling. The "M"'s in "RTFM" are the datasheets for the LCD and the F= PGA. > > Don't get overwhelmed by the size of the datasheets/manuals - odds are th= at you don't need 90% of what's in them - stick with the basics. > > - First start electrically - what does the data sheet for the LCD say is = the electrical format of the signals it accepts? (3.3V TTL? LVDS? 1.8V logi= c? etc.). Then see the FPGA data sheet to see if you can find an IO standar= d that matches. Hook the two up accordingly. > > - Next, write some basic VHDL/verilog/UCF files for the FPGA to instantia= te the signals to the LCD in your FPGA and set everything to the appropriat= e IO standard. > > - Then dig into the LCD datasheet again and figure out what commands or d= ata formating it needs and get cracking on a VHDL/verilog state machine or = data formatter that accomplishes whatever it is that you want to do with th= e LCD. Depending on the application it was meant for, most LCDs are either = command and buffer based (that is, you write some commands to it, then writ= e to a frame buffer on the LCD controller), or they are video stream based = (i.e. no commands necessary, just send raw RGB data continuously). > > Hope that helps. > > Chris OK posting directly here since I kept screwing it up on FPGARelated.com I think I have gotten it...well sort of. I found a good VHDL example for driving a VGA monitor and have modified it to work with the LCD... I got it working and changing the colors on the screen. I have modified it further, but I keep getting the following errors now: Line 32. The type of the element in aggregate does not correspond to any array type. Line 44. The type of the element in aggregate does not correspond to any array type. Line 32 is: if (h_counter =3D> "0111100010") and (h_counter <=3D "1000001011") then Line 44 is: if (v_counter =3D> "0100010010") and (v_counter <=3D "0100011100") then What am I doing wrong? I am still learning VHDL so bear with me...Article: 150529
On 1/25/2011 12:34 PM, frozen001 wrote:
> Line 44 is:
>
> if (v_counter => "0100010010") and (v_counter<= "0100011100") then
>
> What am I doing wrong?
Maybe you mean "greater than or equal" which is >=
-- Mike
Article: 150530On Jan 25, 6:13=A0am, Gabor <ga...@alacron.com> wrote: > On Jan 24, 5:21=A0pm, ghelbig <ghel...@lycos.com> wrote: > > > > > > > On Jan 24, 12:23=A0pm, Gabor <ga...@alacron.com> wrote: > > > > On Jan 24, 1:50=A0pm, ghelbig <ghel...@lycos.com> wrote: > > > > > I think that iMpact is messing with me. > > > > > Here's what I do: > > > > > 1) Create a bit file with ISE 11.5 > > > > 2) Downloading the bit file to my Virtex-5 via JTAG. =A0(I'm using = a > > > > DLC9G and WinXP) > > > > 3) Run a regression test on the system. > > > > > If the regression test passes I do the following: > > > > > 4) Create a MCS file with iMpact. > > > > 5) Load the MCS into the attached SPI chip (again, with the DLC9G) > > > > 6) Power cycle the board. > > > > 7) Re-run the regression test. > > > > > Here's my issue: > > > > > I have two bit files for this project. =A0One was created last mont= h, > > > > one was created last week. =A0The steps above are repeated EXACTLY = for > > > > the two bit files. =A0There are no warnings or errors generated wit= h > > > > steps 2 through 6. > > > > > Step 7 fails for one bit file, and passes for the other. =A0With on= e bit > > > > file, and chip never leaves the DONE state. =A0Keep in mind that bo= th > > > > bit files load and run "just fine" when I load them through the JTA= G > > > > port. > > > > > Has anyone seen this before? =A0I haven't gotten any help from the > > > > factory yet. > > > > > Regards, > > > > G. > > > > The first thing I look for is whether the .mcs file was really create= d > > > correctly. > > > I have been burned by the ISE GUI grabbing an existing impact project > > > that > > > built a new .mcs file from an old .bit file. > > > > If you look in the directory where the .mcs file was built, there > > > should also > > > be a .prm file with the same base file name. =A0In this file you can = see > > > the > > > name and modification date of the .bit file(s) that were used in > > > creating > > > the .mcs file. > > > > Also I have had some issues with indirect SPI programming using > > > impact. =A0However usually these show up as an error when you go to > > > verify the .mcs file in SPI flash. =A0When you say "never leaves the > > > DONE state" do you mean that DONE never goes high? =A0Or does > > > DONE go high, but the chip never comes out of reset. =A0The latter > > > condition can be bitstream-dependent although I've never seen > > > this behavior when using Master-SPI config mode. =A0Just be sure > > > that you use the default startup clock (CCLK) when you run > > > BitGen. > > > > -- Gabor > > > It is the "DONE goes high, but the chip never comes out of reset" > > case. =A0It seems to be bit-stream dependent, I can make good MCS files > > from old BIT files. > > > I'm stumped. =A0The only thing I can see different in the two cases > > (works, does not work) from start to finish is the Verilog code. > > > G. > > Is there anything in the Verilog code that changes that might affect > the reset? =A0Does your reset depend on PLL or DCM lock? =A0That > can often be affected by seemingly unrelated changes especially > if there is a noisy clock input or insufficient power supply bypass. > > -- Gabor- Hide quoted text - > > - Show quoted text - I changed the ISERDES from asynch to synch reset. I added and removed ILA's. Everything else was just bug fixes. The bit-file works if JTAG-ed into the FPGA. I can Write/Verify/Read the SPI flash all day long. The bit-file does not work when loading from SPI. Thanks for helping! Seriously, there are not bad ideas right now. G.Article: 150531
On Jan 25, 12:39=A0pm, Lou <lciot...@gmail.com> wrote: > On Jan 25, 8:44=A0am, Chris Maryan <kmar...@gmail.com> wrote: > > > RTFM is the universal answer for all of this. There may be some tutoria= ls, but they likely won't cover the particular LCD you are using - that sai= d, try Googling. The "M"'s in "RTFM" are the datasheets for the LCD and the= FPGA. > > > Don't get overwhelmed by the size of the datasheets/manuals - odds are = that you don't need 90% of what's in them - stick with the basics. > > > - First start electrically - what does the data sheet for the LCD say i= s the electrical format of the signals it accepts? (3.3V TTL? LVDS? 1.8V lo= gic? etc.). Then see the FPGA data sheet to see if you can find an IO stand= ard that matches. Hook the two up accordingly. > > > - Next, write some basic VHDL/verilog/UCF files for the FPGA to instant= iate the signals to the LCD in your FPGA and set everything to the appropri= ate IO standard. > > > - Then dig into the LCD datasheet again and figure out what commands or= data formating it needs and get cracking on a VHDL/verilog state machine o= r data formatter that accomplishes whatever it is that you want to do with = the LCD. Depending on the application it was meant for, most LCDs are eithe= r command and buffer based (that is, you write some commands to it, then wr= ite to a frame buffer on the LCD controller), or they are video stream base= d (i.e. no commands necessary, just send raw RGB data continuously). > > > Hope that helps. > > > Chris > > OK posting directly here since I kept screwing it up on > FPGARelated.com > > I think I have gotten it...well sort of. =A0I found a good VHDL example > for driving a VGA monitor and have modified it to work with the LCD... > I got it working and changing the colors on the screen. =A0 I have > modified it further, but I keep getting the following errors now: > > Line 32. The type of the element in aggregate does not correspond to > any array type. > > Line 44. The type of the element in aggregate does not correspond to > any array type. > > Line 32 is: > > if (h_counter =3D> "0111100010") and (h_counter <=3D "1000001011") then > > Line 44 is: > > if (v_counter =3D> "0100010010") and (v_counter <=3D "0100011100") then > > What am I doing wrong? I am still learning VHDL so bear with me... VHDL does not understand ">=3D" for vectors - vectors are just a pile of bits to VHDL - it doesn't know if the left or right bit is the most significant bit. You need to convert them to numbers to test for larger or smaller. There are standard packages to do this. Try looking here: <http://www.cs.umbc.edu/portal/help/VHDL/ stdpkg.html> RKArticle: 150532
On Jan 25, 3:48=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > On 1/25/2011 12:34 PM, frozen001 wrote: > > > Line 44 is: > > > if (v_counter =3D> =A0"0100010010") and (v_counter<=3D "0100011100") th= en > > > What am I doing wrong? > > Maybe you mean "greater than or equal" which is =A0>=3D > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- Mike Good catch, Mike! I really like the very informative error message. At least the error pointed to the correct lines in the file. My usual problems with typo's result in an error message pointing several lines down when the missing "end" suddenly causes a syntax error. Regards, GaborArticle: 150533
On Jan 25, 6:53=A0am, Mike Perkins <s...@spam.com> wrote: > On 25/01/2011 10:31, Emanuele83 wrote: > > > > > On Jan 25, 11:23 am, "Nial Stewart" > > <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> =A0wrote: > >>> I do not know, but we are not able to find somebody really able to > >>> perform a good soldering of this BGA packages. we've got 4 PCB for > >>> prototyping and nobody is able to solder this stuff... sometimes the > >>> VCC int is shorted, sometimes the chain is not possible to be > >>> detected... > >>> Yeah, ok the pcb has 12 layers with a lot of power planes, but it is > >>> just a matter to use the correct temp profile.... Uff.. I do hope tha= t > >>> is a matter of HW.... > > >> You need to find an assembly house with a Vapour Phase reflow oven, fr= om > >> what I understand (from my assembly guys) this almost guarantees a goo= d > >> result. > > >> Even without this BGAs are pretty run of the mill, any competent assem= bly > >> house should be able to get this down. > > >> Are you going to a quality assembly house or the cheapest one? > > >> Nial > > > I do not know if it is the cheapest one. I know only that they are > > soldering with IRs reflow. > > I am not the one in the office who has the choice... Now we sent a > > board to be reworked and new FPGAs will be soldered. > > The point is that if they do it with the bad temp profile I am afraid > > that the FPGA can be damaged... > > My experience is that as long as the profile is sufficient for solder to > flow, and with a quality paste, it's unusual for things to go wrong. =A0I > have also found from building prototypes in-house that whilst going over > temperature is not disasterous, though may affect long term reliability. > > Do you have a backup of an old snapshot of your design? =A0Can you check > the PCB works in the same way it did when the snapshort was taken? > > Whilst a 80 MHz clock is low, there are a myriad of reasons why a design > change may stop the FPGA from funtioning as exected. =A0I assume you have > checked the design will work with the specified clock rate? =A0There mayb= e > issues with simulatenous switching, or through compromised decoupling. > > Personally I would use, and I beleive its more conventional for: > > histogram_calculation_process : process (clk_120) > begin > =A0 =A0if rst =3D '1' then -- not reset > =A0 =A0 =A0 state_m_1 <=3D idle; > =A0 =A0elsif clk_120'event and clk_120=3D'1' then -- clk rising edge > =A0 =A0 =A0 =A0case state_m_1 is > =A0 =A0 =A0 =A0 =A0when idle =3D> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0A_tcspc <=3D input_a; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0B_tcspc <=3D input_b; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0state_m_1 <=3D state_1; > =A0 =A0 =A0 =A0 =A0when state_1 =3D> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 output_sum <=3D S; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0state_m_1 <=3D idle; > =A0 =A0 =A0 =A0 =A0when others =3D> null; > =A0 =A0 =A0 =A0end case > =A0 =A0 end if; > end if; > > This also reduces the complexity of the LUT. I can't believe you opened that can of worms. The OP's reset is synchronous and your reset is asynchronous. Async reset are fine if you know how to bring the circuit out of reset. But if you just let every part of your design leave async reset without coordination, it can start off in an invalid state due to the different parts starting off on different edges of the clock. With a sync reset, if it meets timing, it should run ok. RickArticle: 150534
On Jan 25, 9:48=A0am, n...@puntnl.niks (Nico Coesel) wrote: > Emanuele83 <emanuele83katam...@googlemail.com> wrote: > >Good day to everybody, > > >Chipscope core to debug my modifications, the design was no more able > >to perform correct operations nor to communicate with some external > >chips creating corrupted data. Even if ALL the constraints at 40MHz > > IMHO this is a problem with unconstrained paths. Did you constrain > input to ff and ff to output paths? Did you constrain paths between > unrelated clock domains? > > >Some info: > >1_I have no possibility to check if the FPGA HW is broken or not. X- > >ray or what else. I just wait for a new board which should be backed > >carefully > >2_I have no chances to perform post route simulations for the whole > >project (I am in a hurry) and with my old design I did not do it > >(SPARTAN 2) and everything was perfectly working (also without setting > >any constraint over PERIOD or OFFSET) > >3_I have 3 boards, when I program them with the same bitstream they > >behave sometimes differently. > > This may be due to FPGA variations. I'd get the constraints sorted out > first. Perhaps you could buy a development board and verify your > design on that so you have a proper reference. That is one of the things I have always felt was lacking, a way to verify timing constraints. I've talked to FPGA vendors and their attitude is just that an engineer should be able to write the constraints correctly, period. No need to verify! Boy, that goes against everything I've ever learned about engineering. You can have problems with ANY part of a design. Being able to verify all aspects of your design is much better than "testing". Testing can prove the existence of faults, but it can't prove the absence... at least not without a LOT of effort and analysis. In fact, testing is a lot like constraints, you have to do it "right" and how do you prove that you have done the testing "right"? RickArticle: 150535
On Jan 25, 5:21=A0pm, Gabor <ga...@alacron.com> wrote: > On Jan 25, 3:48=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > > > On 1/25/2011 12:34 PM, frozen001 wrote: > > > > Line 44 is: > > > > if (v_counter =3D> =A0"0100010010") and (v_counter<=3D "0100011100") = then > > > > What am I doing wrong? > > > Maybe you mean "greater than or equal" which is =A0>=3D > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- Mike > > Good catch, Mike! =A0I really like the very informative error message. > At least the error pointed to the correct lines in the file. =A0My > usual problems with typo's result in an error message pointing > several lines down when the missing "end" suddenly causes > a syntax error. > > Regards, > Gabor The error message is based on what you typed, not what you are thinking. The =3D> symbol is used for associations in aggregates. So it told you your aggregate was wrong. RickArticle: 150536
On Jan 26, 6:44=A0am, rickman <gnu...@gmail.com> wrote: > On Jan 25, 9:48=A0am, n...@puntnl.niks (Nico Coesel) wrote: > > > > > > > > > > > Emanuele83 <emanuele83katam...@googlemail.com> wrote: > > >Good day to everybody, > > > >Chipscope core to debug my modifications, the design was no more able > > >to perform correct operations nor to communicate with some external > > >chips creating corrupted data. Even if ALL the constraints at 40MHz > > > IMHO this is a problem with unconstrained paths. Did you constrain > > input to ff and ff to output paths? Did you constrain paths between > > unrelated clock domains? > > > >Some info: > > >1_I have no possibility to check if the FPGA HW is broken or not. X- > > >ray or what else. I just wait for a new board which should be backed > > >carefully > > >2_I have no chances to perform post route simulations for the whole > > >project (I am in a hurry) and with my old design I did not do it > > >(SPARTAN 2) and everything was perfectly working (also without setting > > >any constraint over PERIOD or OFFSET) > > >3_I have 3 boards, when I program them with the same bitstream they > > >behave sometimes differently. > > > This may be due to FPGA variations. I'd get the constraints sorted out > > first. Perhaps you could buy a development board and verify your > > design on that so you have a proper reference. > > That is one of the things I have always felt was lacking, a way to > verify timing constraints. =A0I've talked to FPGA vendors and their > attitude is just that an engineer should be able to write the > constraints correctly, period. =A0No need to verify! =A0Boy, that goes > against everything I've ever learned about engineering. =A0You can have > problems with ANY part of a design. =A0Being able to verify all aspects > of your design is much better than "testing". =A0Testing can prove the > existence of faults, but it can't prove the absence... at least not > without a LOT of effort and analysis. =A0In fact, testing is a lot like > constraints, you have to do it "right" and how do you prove that you > have done the testing "right"? > > Rick Holy words, fellow, holy words! :) I'll test the Power supply section today, but for example setting lower drive strength of output drivers to be conservative in power, the behaviour changes... Ok when I modify the drive strength also the delay of I/O clocks changes, but, damn it, I am working at 40Mhz and the constraints are met!Article: 150537
On 25 Jan., 13:44, "rizi" <cyclon786@n_o_s_p_a_m.gmail.com> wrote: > Hi > > i am working on FPGAs. > As i am new in vhdl so i do not know how to deal with images in vhdl. > i want to read an image that is already stored in PC. > please can you help me how to read an image from the PC and store it in > FPGA ROM ? > (i want to do this in verilog or vhdl) > > your suggestion will be appreciated. > > Thank you > Rizi > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com hi, search the forum here, or at http://forums.xilinx.com/ This question has been answered a thousand times. Have a nice synthesis EilertArticle: 150538
On Jan 26, 6:44=A0am, rickman <gnu...@gmail.com> wrote: > On Jan 25, 9:48=A0am, n...@puntnl.niks (Nico Coesel) wrote: > > > > > > > > > > > Emanuele83 <emanuele83katam...@googlemail.com> wrote: > > >Good day to everybody, > > > >Chipscope core to debug my modifications, the design was no more able > > >to perform correct operations nor to communicate with some external > > >chips creating corrupted data. Even if ALL the constraints at 40MHz > > > IMHO this is a problem with unconstrained paths. Did you constrain > > input to ff and ff to output paths? Did you constrain paths between > > unrelated clock domains? > > > >Some info: > > >1_I have no possibility to check if the FPGA HW is broken or not. X- > > >ray or what else. I just wait for a new board which should be backed > > >carefully > > >2_I have no chances to perform post route simulations for the whole > > >project (I am in a hurry) and with my old design I did not do it > > >(SPARTAN 2) and everything was perfectly working (also without setting > > >any constraint over PERIOD or OFFSET) > > >3_I have 3 boards, when I program them with the same bitstream they > > >behave sometimes differently. > > > This may be due to FPGA variations. I'd get the constraints sorted out > > first. Perhaps you could buy a development board and verify your > > design on that so you have a proper reference. > > That is one of the things I have always felt was lacking, a way to > verify timing constraints. =A0I've talked to FPGA vendors and their > attitude is just that an engineer should be able to write the > constraints correctly, period. =A0No need to verify! =A0Boy, that goes > against everything I've ever learned about engineering. =A0You can have > problems with ANY part of a design. =A0Being able to verify all aspects > of your design is much better than "testing". =A0Testing can prove the > existence of faults, but it can't prove the absence... at least not > without a LOT of effort and analysis. =A0In fact, testing is a lot like > constraints, you have to do it "right" and how do you prove that you > have done the testing "right"? > > Rick Holy words, fellow, holy words! :) We use more time to writing the correct test (that must be done carefully) than to design the logic... I am going to test the power supply section, but I've already tested yesterday that compiling the same code, setting the drive strength of I/Os to a safer value (from 6 to 2) the behaviour of the system is no more consistent. I left all the timing constraints unchanged, always met, @40Mhz speed, but it does not work....Article: 150539
On Tue, 25 Jan 2011 13:31:46 -0800 (PST), d_s_klein <d_s_klein@yahoo.com> wrote: >On Jan 25, 12:39 pm, Lou <lciot...@gmail.com> wrote: >> On Jan 25, 8:44 am, Chris Maryan <kmar...@gmail.com> wrote: >> >> > RTFM is the universal answer for all of this. There may be some tutorials, but they likely won't cover the particular LCD you are using - that said, try Googling. The "M"'s in "RTFM" are the datasheets for the LCD and the FPGA. >> >> > Don't get overwhelmed by the size of the datasheets/manuals - odds are that you don't need 90% of what's in them - stick with the basics. >> >> > - First start electrically - what does the data sheet for the LCD say is the electrical format of the signals it accepts? (3.3V TTL? LVDS? 1.8V logic? etc.). Then see the FPGA data sheet to see if you can find an IO standard that matches. Hook the two up accordingly. >> >> > - Next, write some basic VHDL/verilog/UCF files for the FPGA to instantiate the signals to the LCD in your FPGA and set everything to the appropriate IO standard. >> >> > - Then dig into the LCD datasheet again and figure out what commands or data formating it needs and get cracking on a VHDL/verilog state machine or data formatter that accomplishes whatever it is that you want to do with the LCD. Depending on the application it was meant for, most LCDs are either command and buffer based (that is, you write some commands to it, then write to a frame buffer on the LCD controller), or they are video stream based (i.e. no commands necessary, just send raw RGB data continuously). >> >> > Hope that helps. >> >> > Chris >> >> OK posting directly here since I kept screwing it up on >> FPGARelated.com >> >> I think I have gotten it...well sort of. I found a good VHDL example >> for driving a VGA monitor and have modified it to work with the LCD... >> I got it working and changing the colors on the screen. I have >> modified it further, but I keep getting the following errors now: >> >> Line 32. The type of the element in aggregate does not correspond to >> any array type. >> >> Line 44. The type of the element in aggregate does not correspond to >> any array type. >> >> Line 32 is: >> >> if (h_counter => "0111100010") and (h_counter <= "1000001011") then if h_counter>=482 and h_counter<=523... Although probably more efficient to generate a latched signal that is set on the values than do a greater/less than comparison : if h_counter=482 then window<='1'; elsif h_counter=523 then window<='0'; end if; >RKArticle: 150540
"rizi" <cyclon786@n_o_s_p_a_m.gmail.com> writes: > Hi > > i am working on FPGAs. > As i am new in vhdl so i do not know how to deal with images in vhdl. > i want to read an image that is already stored in PC. > please can you help me how to read an image from the PC and store it in > FPGA ROM ? > (i want to do this in verilog or vhdl) Write a quick script in your favourite scripting language to read the image (for example, Python and the Python Imaging Library can read most formats of images). Your script can then write that image out to a file as a VHDL constant - you can use an array of integers to store the data. Finally, create a clocked process which accesses that constant based on an "address" input. The synthesiser can convert that into a ROM. > > your suggestion will be appreciated. > And there you have it... > Thank you You're welcome. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 150541
Martin Thompson <martin.j.thompson@trw.com> writes: > Your script can then write that image out to a file as a VHDL constant > - you can use an array of integers to store the data. Or generate a MIF file or other ROM format supported by your FPGA vendor. This is usually faster (but not as portable as the above suggestion) to run through the tool-chain and most FPGA vendors have a tool which will quickly merge a new version of a ROM file while everything else being constant. //Petter -- .sig removed by request.Article: 150542
hi, i am using spartan 3 xc3s4000 in my design and i have two gigabit ethernet interfaces integrated to it. I connect one interface to one pc and the other one to 2nd pc , all works fine. Pings going, packets going. When i insert two cisco switches configured on VLAN in the scenario i.e. pc<-> switch <-> FPGA <-> switch <-> pc ; my packets start dropping. I don't know why as i am only performing store and forward. If it is working without switches, it should work with switches as well. Can anyone give me any pointers ? Thanks --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150543
> With a sync reset, if it meets timing, it should run ok. I have had it confirmed that if you generate a reset synchronously then use it 'asynchronously' in the standard process template (VHDL) that Quartus knows it's a synchronous signal and all timing analysis is correctly handled. Nial.Article: 150544
Hi,
I am trying a design that is from ISE 9.2 on the latest 12.4 using
CentOS 64 bit and receive the following error, I can't find anything
on Xilinx that refers to it.
Anyone seen the same and know a solution?
INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24 - Number of bytes
peeked
does not match number of bytes requested. Corrupted file?
INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24 - Number of bytes
peeked
does not match number of bytes requested. Corrupted file?
FATAL_ERROR:NgdBuild:basnbbuspin.c:87:1.20 - Empty or missing BUS_SYNTAX
for PM
base Process will terminate. For technical support on this issue,
please
open a WebCase with this project attached at
http://www.xilinx.com/support.
Release 12.4 - Map M.81d (lin64)
/michael
Article: 150545I am using the following standard libraries: use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; I tried going from binary to decimal, and still get the same error....Article: 150546
On Wed, 2011-01-26 at 06:12 -0600, salimbaba wrote: > hi, > i am using spartan 3 xc3s4000 in my design and i have two gigabit etherne= t > interfaces integrated to it. I connect one interface to one pc and the > other one to 2nd pc , all works fine. Pings going, packets going.=20 > When i insert two cisco switches configured on VLAN in the scenario i.e.= =20 > pc<-> switch <-> FPGA <-> switch <-> pc ; >=20 > my packets start dropping. I don't know why as i am only performing store > and forward. If it is working without switches, it should work with > switches as well. >=20 > Can anyone give me any pointers ? >=20 > Thanks > =20 > =09 > --------------------------------------- =09 > Posted through http://www.FPGARelated.com What does the "gigabit ethernet interface" mean? Did you connect directly the GMII/RGMII/SGMII interfaces of external PHYs or do you use some MACs? If you use Ethernet MACs, do not forget to enable the VLAN support otherwise they probably drop VLAN tagged Ethernet frames. JanArticle: 150547
>Hi, > >I am trying a design that is from ISE 9.2 on the latest 12.4 using >CentOS 64 bit and receive the following error, I can't find anything >on Xilinx that refers to it. > >Anyone seen the same and know a solution? > > > >INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24 - Number of bytes >peeked > does not match number of bytes requested. Corrupted file? >INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24 - Number of bytes >peeked > does not match number of bytes requested. Corrupted file? >FATAL_ERROR:NgdBuild:basnbbuspin.c:87:1.20 - Empty or missing BUS_SYNTAX >for PM > base Process will terminate. For technical support on this issue, >please > open a WebCase with this project attached at >http://www.xilinx.com/support. >Release 12.4 - Map M.81d (lin64) > > >/michael > Is "CentOS 64bit" a supported operating system for ISE 12.4? You could try opening a WebCase for it at http://www.xilinx.com/support, unless you are a student, in which case I suspect your supervisor has to do it. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150548
>What does the "gigabit ethernet interface" mean? Did you connect >directly the GMII/RGMII/SGMII interfaces of external PHYs or do you use >some MACs? > >If you use Ethernet MACs, do not forget to enable the VLAN support >otherwise they probably drop VLAN tagged Ethernet frames. > >Jan > > hey Jan, well i have PHYs connected with FPGA through GMII interface, and i have MACs in FPGA. I am only forwarding the packet, without even looking at it, so even if it has a VLAN header, it should be forwarded.Secondly, I looked at the packet using chipscope, there wasn't any VLAN header, which i came to know that if we are only using one VLAN on one TRUNK line, it doesn't attach VLAN header. Anyway,i further looked at the packet and well my counter is not resetting :s .. It resets to a random value instead of 0. I have no idea why. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150549
On Jan 26, 8:05=A0am, Lou <lciot...@gmail.com> wrote: > I am using the following standard libraries: > > use IEEE.std_logic_1164.all; > use IEEE.std_logic_arith.all; > use IEEE.std_logic_unsigned.all; > > I tried going from binary to decimal, and still get the same error.... I changed the =3D> to <=3D and it worked... stupid error... Of course now I get nothing dispaying again... Part of my problem is I cannot locate the datasheet for this display. It is a TFT plug in module from HUINS (www.huins.com). Website does not contain any datasheets. Tried to e-mail them and got no response.
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