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>On Wed, 02 Feb 2011 15:08:31 -0800, Tim Wescott wrote: > >> In my travels I have found that -- in the US at least -- >> HDL choice is very strongly correlated to location: >> designers on the west coast tend to use Verilog >> instead of VHDL, the obverse is the true of folks on >> the east coast. > >There's certainly some truth in that, but there's probably a >stronger correlation with target technology: FPGA folks are >still predominantly VHDL everywhere, ASIC shops use Verilog. >That gives a geographic bias as well, because of the heavy >concentration of ASIC shops on the west coast. > <snip> The following is a list of projects I have worked on over the last 10 years. This includes time in CO and MN (since this post is interested in geo-local). The duration (in months) includes time actively modifying the HDL, implementation, debug, fixes, feature adds. Duration does *not* include, design and documentation. In this context I define a project as an opportunity to use a different HDL. Duration HDL Target Tech ---------------------------------- 9 Verilog FPGA 6 Verilog FPGA 6 Verilog ASIC 2 Verilog/SV FPGA 3 Verilog ASIC 6 VHDL FPGA 3 VHDL FPGA 5 VHDL FPGA 3 Verilog FPGA 3 MyHDL FPGA 3 Verilog FPGA 3 Verilog ASIC Chris Felton --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150701
Sorry. Let me try again to make it clearer. The existing Xilinx FPGA board has some test *output* pins. Now we wanted to use them an *input* pins instead of *output* pins. What does it need to be done to make it work?Article: 150702
Gabor <gabor@alacron.com> wrote: >On Feb 2, 6:08=A0pm, Tim Wescott <t...@seemywebsite.com> wrote: >> In my travels I have found that -- in the US at least -- HDL choice is >> very strongly correlated to location: designers on the west coast tend >> to use Verilog instead of VHDL, the obverse is the true of folks on the >> east coast. >> >> Designers on each coast like to adopt a cosmopolitan air and claim to be >> _completely agnostic_ about which language that they'd prefer to use -- >> at least during the job interview. =A0Then when it comes time to actually >> write lines of code, most of them will kick and scream (or at least >> quietly hyperventilate) if they don't get to use the language that >> they're accustomed to. >> >> So -- where are you from, and what HDL do you use? =A0Have you seen >> patterns of language use in your area change in the last decade or so? >> >> I'm particularly interested in hearing from folks outside the US, and >> from folks in the US but not on the coasts. =A0Noting whether you're from >> a military hardware background or purely civilian is of interest, too. >> >> TIA. >> >> -- >> >> Tim Wescott >> Wescott Design Serviceshttp://www.wescottdesign.com >> >> Do you need to implement control loops in software? >> "Applied Control Theory for Embedded Systems" was written for you. >> See details athttp://www.wescottdesign.com/actfes/actfes.html > >I'm in the eastern US (New Hampshire) and use pretty much exclusively >Verilog. I went through college before there were any HDL's, and >spent >the first decade of my career with pencil and vellum for schematics. >My first programmable logic was PALs and I used PALASM for that, >then moved on to Abel, CUPL, and finally back to schematics with >Abel when I started out on FPGA's. Verilog came later, but it >feels pretty natural to me now. I use it because it's what makes >me the most productive. I've never worked for large companies, >so the "existing culture" was never a driving force in tool >selection. Personally I feel I have benefited by learning logic >design before learning HDL's. So many of the clueless answer- >seekers on the Xiinx forums seem to think logic design is >some sort of software. My preference would be to continue >using schematics for a top level design and Verilog underneath. IMHO schematics are bad. Most designs are becoming pretty complicated these days. If you still think in logic then you'll lose oversight at some point. With VHDL I have learned not to think in logic but think in functions. Parallel functions to be exact. Since I started using VHDL for real FPGA designs I have always looked for ways to push VHDL to its limits so I have to write as little code as possible (less code=less bugs) and use parameters to define things like bus widths, number of channels, buffer sizes, etc. Let the optimizer deal with putting the logic together in an efficient way. A few years ago I looked for a VHDL implementation of a priority encoder. I was amazed by the large number of people that produce a number of if statements for each input combination. Out of 20 examples only one created a generic function consisting of 3 lines of VHDL code! -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 150703
On Feb 4, 9:32=A0am, Carl Horton <carl.horto...@gmail.com> wrote: > Sorry. Let me try again to make it clearer. The existing Xilinx FPGA > board has some test *output* pins. Now we wanted to use them an > *input* pins instead of *output* pins. What does it need to be done to > make it work? Generate a new FPGA design with input buffers assigned to these pins instead of output buffers. Ed McGettigan -- Xilinx Inc.Article: 150704
"Tim Wescott" <tim@seemywebsite.com> wrote in message news:UPCdna5sk-ORedTQnZ2dnUVZ_j-dnZ2d@web-ster.com... > I'm particularly interested in hearing from folks outside the US, and from > folks in the US but not on the coasts. Noting whether you're from a > military hardware background or purely civilian is of interest, too. Isn't there a generic webservice where you can mark where on the globe you are, and put your hdl accent in there? I think Ive seen it some time ago. Maybe google can help? :) Btw, in Norway its most VHDL that is teached and used. I started with AHDL back in the 90's (Flex10k's) but went for VHDL around when normal clock rates started to go beyond 40Mhz.Article: 150705
>I am interested in bit-accurate C / C++ modeling of hardware. <snip> I agree, use SystemC (if C/C++ is a must). The language is standard, you will be much better off knowing SystemC vs. the other mentioned libs. Side note, if you are more interested if fast development vs. fast execution you can do bit-accurate (and cycle) in Python using MyHDL. Chris Felton --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150706
On Feb 4, 1:10=A0pm, n...@puntnl.niks (Nico Coesel) wrote: [snip] > IMHO schematics are bad. Most designs are becoming pretty complicated > these days. If you still think in logic then you'll lose oversight at > some point. With VHDL I have learned not to think in logic but think > in functions. Parallel functions to be exact. > Maybe you misinterpreted my use of schematics. Think of a VHDL design where the top level file has nothing but component declarations and instantiations. Everything below that is behavioral coding. In that case I find a schematic for the top level to be easier to follow (flow, interconnect) than a huge pile of text. Just my opinion, but I don't think I'm alone on this one. I expressly do NOT use schematics to produce designs at a structural gate level (unless the design is incredibly simple). Under the top level, open any block and there will be HDL. I also do board level design, so this combination of complex functions connected graphically works well for my visualization of the overall project. -- GaborArticle: 150707
Gabor <gabor@alacron.com> wrote: (snip) > Maybe you misinterpreted my use of schematics. Think of a > VHDL design where the top level file has nothing but component > declarations and instantiations. Everything below that is > behavioral coding. I use mostly structural verilog, except for FF's and state machines. So, yes, the top level is usually declarations and instantiations, though maybe some continuous assignments also. Usually I find that more readable than the schematic, but I agree there is some use for the top level schematic. Many tool sets have a HDL to schematic converter, and sometimes it actually works. It helps to have a large format printer. In one pre-verilog design I worked on some years ago, my first try with the netlist to schematic program was the top level. The tool nicely figured out that it would take many pages to print, and did that. I then had it taped up onto a wall. (It was a systolic array, and so very wide and not so tall. > In that case I find a schematic for > the top level to be easier to follow (flow, interconnect) > than a huge pile of text. Just my opinion, but I don't > think I'm alone on this one. I expressly do NOT use > schematics to produce designs at a structural gate > level (unless the design is incredibly simple). I think I disagree, but not so strongly. Most likely it depends on the specific design. Some work better one way, some the other. > Under the top level, open any block and there will be HDL. > I also do board level design, so this combination of > complex functions connected graphically works > well for my visualization of the overall project. Which reminds me of something I was wondering about not so long ago: A verilog to PCB design conversion. If the top level of a design, above the IC level, was in verilog could that be used to (at least partially) generate the PCB design? -- glenArticle: 150708
Carl Horton <carl.horton08@gmail.com> wrote: > Sorry. Let me try again to make it clearer. The existing Xilinx FPGA > board has some test *output* pins. Now we wanted to use them an > *input* pins instead of *output* pins. What does it need to be done to > make it work? If there are external (to the FPGA) unidirectional buffers, then you have to change those. Otherwise, just change the IOB configuration from output to input. -- glenArticle: 150709
Thanks Glen, Some of FPGA output pins are just directly connecting to the connector. With this, I guess we can just change the IOB configuration to input to feed the input signal to the connector, right? Some of FPGA output pins are going through SN75LVDS387 HIGH-SPEED DIFFERENTIAL LINE DRIVERS and then connected to the connector. Is SN75LVDS387 unidirectional? I guess it is, right? We have no way to use them as input pins if we do not replace the unidirectional driver, right? I am not a board designer, therefore I have these questions. Thanks for your kind help!Article: 150710
On Feb 4, 6:35=A0pm, Carl Horton <carl.horto...@gmail.com> wrote: > Thanks Glen, > > Some of FPGA output pins are just directly connecting to the > connector. With this, I guess we can just change the IOB configuration > to input to feed the input signal to the connector, right? > > Some of FPGA output pins are going through SN75LVDS387 HIGH-SPEED > DIFFERENTIAL LINE DRIVERS and then connected to the connector. Is > SN75LVDS387 unidirectional? I guess it is, right? We have no way to > use them as input pins if we do not replace the unidirectional driver, > right? > > I am not a board designer, therefore I have these questions. Thanks > for your kind help! See: http://focus.ti.com/lit/ds/symlink/sn75lvds386.pdf The SN75LVDS387 is a 16-bit LVDS driver. If you want to change the direction of all 16 signals, then you might be in luck. If you remove the 75LVDS387 and replace it with an SN75LVDS386 or SN75LVDT386 chip rotated 180 degrees so that pin 1 goes to the board pad for pin 33, then all 16 bits become inputs. The LVDS pins, LVCMOS pins, Enable pins, Vcc, and GND all line up properly in this orientation. Check out the first page of the datasheets on TI.com to see how the pins line up. I've done this sort of thing on Channel-Link parts as well, which required chips to be upside-down rather than rotated. The 'LVDT part has integrated terminating resistors, which are probably right for you if the board was designed for transmitter only, and therefore has no board-level termination. If all you want is LVCMOS I/O at the connector, then you could just remove the existing chip and wire across. If you need only one or two lines to change direction you can always lift pins and wire around the chip. Whether you rework or re-spin the boards will depend on how many boards you need and whether the rework is acceptable in the end use. HTH, GaborArticle: 150711
On Feb 4, 7:19=A0pm, Gabor <ga...@alacron.com> wrote: > On Feb 4, 6:35=A0pm, Carl Horton <carl.horto...@gmail.com> wrote: > > > Thanks Glen, > > > Some of FPGA output pins are just directly connecting to the > > connector. With this, I guess we can just change the IOB configuration > > to input to feed the input signal to the connector, right? > > > Some of FPGA output pins are going through SN75LVDS387 HIGH-SPEED > > DIFFERENTIAL LINE DRIVERS and then connected to the connector. Is > > SN75LVDS387 unidirectional? I guess it is, right? We have no way to > > use them as input pins if we do not replace the unidirectional driver, > > right? > > > I am not a board designer, therefore I have these questions. Thanks > > for your kind help! > > See:http://focus.ti.com/lit/ds/symlink/sn75lvds386.pdf > > The SN75LVDS387 is a 16-bit LVDS driver. =A0If you want to change the > direction of all 16 signals, then you might be in luck. =A0If you remove > the 75LVDS387 and replace it with an SN75LVDS386 or SN75LVDT386 > chip rotated 180 degrees so that pin 1 goes to the board pad for > pin 33, then all 16 bits become inputs. =A0The LVDS pins, LVCMOS pins, > Enable pins, Vcc, and GND all line up properly in this orientation. > Check out the first page of the datasheets on TI.com to see how > the pins line up. =A0I've done this sort of thing on Channel-Link parts > as well, which required chips to be upside-down rather than rotated. Dang! That is amazing. But for some reason, they didn't design the 8 and 4 bit versions of the chip for the same trick. I guess it was just lucky coincidence driven by a commonality in internal layout. One limitation is that while this will get the inputs and outputs on the right sets of pins, the polarity of the inputs and outputs are reversed, so if this is part of a system cabling might have to change. 1 to 1 cabling won't connect up correctly... but that is just a polarity issue and may be correctable in software or some other place. RickArticle: 150712
Gabor <gabor@alacron.com> wrote: >On Feb 3, 8:24=A0am, "kolar" <kamleshrr@n_o_s_p_a_m.gmail.com> wrote: >> Hi, >> >> For my project we are using Xilinx Virtex-6 FPGAs. I have a specific >> requirement where I would like to change the IO voltage(VCCO) of one bank >> from 3.3V to 1.8V. Assuming that the core is working at a different volta= >ge >> and IOs on different. Core at the start works with 3.3V and then drives t= >he >> IOs to Z and then we would like to change the VCCO of this particular ban= >k >> and start working at 1.8V. >> >> Note that we do not want to recreate bitmap or reload the design. While >> this swithcing is happening we would like to let our core work continuous= >ly >> with other set of IO bank whose voltage is not switching. >> >> Is this dynamic voltage switching possible. If yes it would be great to >> know how this can be achieved. I believe some kind of registers will need >> to be programmed to achieve this. >> >> Thanks >> Kolar >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > >I'm pretty sure the maximum Vcco for Virtex 6 is 2.5V, not 3.3V. >Within the >usable range of Vcco, you can use the same LVCMOS I/O standard without >changing the bitstream, just by picking the lowest voltage to be >used. What >you end up with is I/O that drives considerably stronger that the >standard >you picked when Vcco is larger than that standard's nominal value. >For >example starting with LVCMOS_18 @4 mA and driving Vcco to 2.5V >will result in much more drive than 4 mA. If you really need to >change >IO standard, rather than "fudging it" with variable Vcco LVCMOS, >then you would need to do at least partial reconfiguration. In addition: I recall someone already tried something similar and the conclusion was that you don't need reconfiguration. I'd just test it on a prototype but I'm quite sure it will just work OK. What you need to think of is that the outputs of the Xilinx FPGA are adjustable current sinks/sources. Like Gabor says the current can be adjusted by the bitstream and ofcourse the current will vary with supply voltage. There is nothing magical about it. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 150713
Tim Wescott <tim@seemywebsite.com> writes: > So -- where are you from, and what HDL do you use? Have you seen > patterns of language use in your area change in the last decade or I'm located in Oslo, Norway. I started using HiLo as a student in the mid 80's. I can recall my first Verilog manual was from Gateway so I assume this was around 1990. Then I spent 17 years doing ASIC design using Verilog and some SystemVerilog at the end of the period. During the past three years I've done mostly FPGA design using VHDL. If I had to choose a single language it would probably be SystemVerilog, especially when it comes to writing testbench code. //Petter -- .sig removed by request.Article: 150714
On Feb 4, 10:00=A0pm, rickman <gnu...@gmail.com> wrote: [snip] > > Dang! =A0That is amazing. =A0But for some reason, they didn't design the = 8 > and 4 bit versions of the chip for the same trick. =A0I guess it was > just lucky coincidence driven by a commonality in internal layout. > > One limitation is that while this will get the inputs and outputs on > the right sets of pins, the polarity of the inputs and outputs are > reversed, so if this is part of a system cabling might have to > change. =A01 to 1 cabling won't connect up correctly... but that is just > a polarity issue and may be correctable in software or some other > place. > > Rick O.K. I assume that since the FPGA code was changing the inversion could happen inside the FPGA, but if you really want to stick with non-inverted signals, then flip the chip on its back instead of rotating it. As I said before we do that with Channel Link chips, but generally speaking rotating the part is easier than flipping it over because you don't need to re-form the leads. -- GaborArticle: 150715
A few days ago I had a look at FPGA prices at digikey. Looking at EQFP packages I noticed that at every LE/memory point the Cyclone IV is about 40% more expensive than the equivalent Cyclone III. Why is the Cyclone IV so much more expensive than the Cyclone III? PhilippArticle: 150716
On 02/05/2011 12:13 PM, Philipp Klaus Krause wrote: > A few days ago I had a look at FPGA prices at digikey. Looking at EQFP > packages I noticed that at every LE/memory point the Cyclone IV is about > 40% more expensive than the equivalent Cyclone III. > Why is the Cyclone IV so much more expensive than the Cyclone III? So that Altera can recoup their investment from the folks who _need_ to be on the bleeding edge, before they make the Cyclone V and all those desperate folks abandon the Cyclone IV as "old hat". -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 150717
D/K is not the real pricing. If you are using any decent qty's, the C4 is cheaper than its C3 predecessor. I've got a quote to prove it! And no, I can't share it--that would not be ethical. On 2/5/2011 3:13 PM, Philipp Klaus Krause wrote: > A few days ago I had a look at FPGA prices at digikey. Looking at EQFP > packages I noticed that at every LE/memory point the Cyclone IV is about > 40% more expensive than the equivalent Cyclone III. > Why is the Cyclone IV so much more expensive than the Cyclone III? > > PhilippArticle: 150718
Cyclone IV is expensive in Digikey at the moment. A lot does depend on the numbers you are buying and if you need more than 1 or 2 it would be worth talking to your local distributor. John Adair Enterpoint Ltd. - Home of Raggedstone3. The Cyclone IV GX Development Platform. On Feb 5, 8:13=A0pm, Philipp Klaus Krause <p...@spth.de> wrote: > A few days ago I had a look at FPGA prices at digikey. Looking at EQFP > packages I noticed that at every LE/memory point the Cyclone IV is about > 40% more expensive than the equivalent Cyclone III. > Why is the Cyclone IV so much more expensive than the Cyclone III? > > PhilippArticle: 150719
On Jan 31, 5:08=A0pm, Axel Mammes <fpgause...@gmail.com> wrote: > Hi everyone, > > I'm looking for someone that can develop an FPGA based multiUART with > 32 UARTs for me. > > My software will run on this board: h**p://www.andahammer.com/mini35- > sdk. > > The mini2440 ARM board has 40 pin system expansion bus connector that > will connect to the multiuart PCB you develop. > > Each UART in the multiUART will connect to a gasoline dispenser using > optoisolated 20mA, 30 mA, 45mA current loop. I will provide schematics > for the TTL-current loop conversion. > > I was thinking the UARTs could be the 16750 from opencores.org. It's > supposed to be stable and it works with standard Linux drivers. h**p:// > opencores.org/project,uart16750 > > Check out the schematics of a mini2440 expansion card that Eric > Brombaugh already developed. > h**p://members.cox.net/ebrombaugh1/synth/mini_2440_fpga/index.html > > Regards > Axel It might be easier and cheaper to use an XMOS device: http://www.xmos.com/Article: 150720
This is driving me nuts... Some months ago I tripped over a company who made a multi-line level shifter designed for the I/O DIP headers on the Digilent Spartan 3 board. Unfortunately, I lost the link and cannot seem to turn it up in a Google search. There's a lot of information on chips capable of doing this, but I'm looking for a finished product to use in hobby pursuits. Is this ringing a bell with anyone on the news group? SteveArticle: 150721
On Sun, 06 Feb 2011 15:23:31 -0500, Steven Hirsch <snhirsch@gmail.com> wrote: >This is driving me nuts... Some months ago I tripped over a company who made >a multi-line level shifter designed for the I/O DIP headers on the Digilent >Spartan 3 board. Unfortunately, I lost the link and cannot seem to turn it up >in a Google search. There's a lot of information on chips capable of doing >this, but I'm looking for a finished product to use in hobby pursuits. > >Is this ringing a bell with anyone on the news group? How about this? http://datasheets.maxim-ic.com/en/ds/MAX3000E-MAX3012.pdf -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 150722
On Sun, 06 Feb 2011 15:23:31 -0500, Steven Hirsch <snhirsch@gmail.com> wrote: >This is driving me nuts... Some months ago I tripped over a company who made >a multi-line level shifter designed for the I/O DIP headers on the Digilent >Spartan 3 board. Unfortunately, I lost the link and cannot seem to turn it up >in a Google search. There's a lot of information on chips capable of doing >this, but I'm looking for a finished product to use in hobby pursuits. > >Is this ringing a bell with anyone on the news group? Or this: http://www.nxp.com/documents/data_sheet/74LVC4245A.pdf ? Try "level shifter" on digikey. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 150723
On 02/06/2011 04:52 PM, Muzaffer Kal wrote: > On Sun, 06 Feb 2011 15:23:31 -0500, Steven Hirsch<snhirsch@gmail.com> > wrote: > >> This is driving me nuts... Some months ago I tripped over a company who made >> a multi-line level shifter designed for the I/O DIP headers on the Digilent >> Spartan 3 board. Unfortunately, I lost the link and cannot seem to turn it up >> in a Google search. There's a lot of information on chips capable of doing >> this, but I'm looking for a finished product to use in hobby pursuits. >> >> Is this ringing a bell with anyone on the news group? > > Or this: http://www.nxp.com/documents/data_sheet/74LVC4245A.pdf ? > > Try "level shifter" on digikey. I do thank you for your answer, but I thought I was clear that I'm looking for a finished product - NOT a chip. The unit I spotted was a PCB roughly the size of the Digilent board. It plugged directly into the female header on the FPGA board. I've spent yet another fun-filled 1/2 hour on Google trying to turn up the unit I remember seeing - no luck. It was not a Digilent product, that I do remember. I fear it may have been from a small firm that doesn't rise anywhere near the top of Google search or ones that perhaps has gone out of business... SteveArticle: 150724
On Sun, 06 Feb 2011 17:11:53 -0500, Steven Hirsch <snhirsch@gmail.com> wrote: >On 02/06/2011 04:52 PM, Muzaffer Kal wrote: >> On Sun, 06 Feb 2011 15:23:31 -0500, Steven Hirsch<snhirsch@gmail.com> >> wrote: >> >>> This is driving me nuts... Some months ago I tripped over a company who made >>> a multi-line level shifter designed for the I/O DIP headers on the Digilent >>> Spartan 3 board. Unfortunately, I lost the link and cannot seem to turn it up >>> in a Google search. There's a lot of information on chips capable of doing >>> this, but I'm looking for a finished product to use in hobby pursuits. >>> >>> Is this ringing a bell with anyone on the news group? >> >> Or this: http://www.nxp.com/documents/data_sheet/74LVC4245A.pdf ? >> >> Try "level shifter" on digikey. > >I do thank you for your answer, but I thought I was clear that I'm looking for >a finished product - NOT a chip. The unit I spotted was a PCB roughly the >size of the Digilent board. It plugged directly into the female header on the >FPGA board. > >I've spent yet another fun-filled 1/2 hour on Google trying to turn up the >unit I remember seeing - no luck. It was not a Digilent product, that I do >remember. I fear it may have been from a small firm that doesn't rise >anywhere near the top of Google search or ones that perhaps has gone out of >business... Try these: http://www.sparkfun.com/products/8745 http://www.mikroe.com/eng/products/view/182/5v-3-3v-voltage-translator-board/ -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com
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