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On Jan 31, 7:44=A0am, aleksa <aleks...@gmail.com> wrote: > On Jan 31, 4:25=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > > On Jan 31, 4:46=A0am, aleksa <aleks...@gmail.com> wrote: > > > > some tests I did: > > > > 1. started iMPACT. > > > 2. double click on Boundary scan. > > > 3. right click, Initialize Chain. > > > > I get blue text "Identify succeeded" > > > The part is already shown as unknown. > > > > I'm asked "Do you want to cont. and assign conf. files?" YES > > > "Do you have a BSDL or BIT file?" YES (xc3s50a.bsd) > > > > 4. Debug, Chain integrity test =3D OK. > > > > Everything else fails. > > > What was the IDCODE reported by iMPACT? > > IDCODE =3D all zeros > > > When you put the oscilloscope on the TDO output what voltage levels > > did you see? > > 0 and 3.2V > > > Is the TDO of the part connected to the TDO of the cable? > > Yes, I've placed a JTAG gif herehttp://www60.zippyshare.com/v/18748688/fi= le.html > > > Are there any other devices in the JTAG chain? > > No- Hide quoted text - > > - Show quoted text - Ok, so the TDO is outputing a waveform in the right range of 0 to 3.2V, but the not showing up in the impact software. This means that the problem is in your custom cable. I can't tell exactly how the cable was constructed from the circuit that you posted as the part numbers are not complete and there are no VCC connections of any type. Have you put a scope on the TDO output of the "LVC25" and the "HCT08" devices? Ed McGettigan -- Xilinx Inc.Article: 150651
On 01/30/2011 03:06 PM, aleksa wrote: > I've used the same JTAG programming board for Spartan 2, and it works. > Spartan2, Spartan3A and parallel port JTAG boards were all done by me. Have you tested this cable with the Spartan 2 TODAY? I have blown out my parallel programming pod several times from ESD and bad power outlet grounds on a couple occasions. JonArticle: 150652
On Jan 31, 9:11=A0pm, Jon Elson <jmel...@wustl.edu> wrote: > On 01/30/2011 03:06 PM, aleksa wrote: > > > I've used the same JTAG programming board for Spartan 2, and it works. > > Spartan2, Spartan3A and parallel port JTAG boards were all done by me. > > Have you tested this cable with the Spartan 2 TODAY? =A0I have blown out > my parallel programming pod several times from ESD and bad power outlet > grounds on a couple occasions. > > Jon I just did that, and everything works. For example, IDCODE is '10000000011000010000000010010011' (XC2S50 TQG144)Article: 150653
On Jan 31, 7:27=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Jan 31, 7:44=A0am, aleksa <aleks...@gmail.com> wrote: > > > > > > > On Jan 31, 4:25=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Jan 31, 4:46=A0am, aleksa <aleks...@gmail.com> wrote: > > > > > some tests I did: > > > > > 1. started iMPACT. > > > > 2. double click on Boundary scan. > > > > 3. right click, Initialize Chain. > > > > > I get blue text "Identify succeeded" > > > > The part is already shown as unknown. > > > > > I'm asked "Do you want to cont. and assign conf. files?" YES > > > > "Do you have a BSDL or BIT file?" YES (xc3s50a.bsd) > > > > > 4. Debug, Chain integrity test =3D OK. > > > > > Everything else fails. > > > > What was the IDCODE reported by iMPACT? > > > IDCODE =3D all zeros > > > > When you put the oscilloscope on the TDO output what voltage levels > > > did you see? > > > 0 and 3.2V > > > > Is the TDO of the part connected to the TDO of the cable? > > > Yes, I've placed a JTAG gif herehttp://www60.zippyshare.com/v/18748688/= file.html > > > > Are there any other devices in the JTAG chain? > > > No- Hide quoted text - > > > - Show quoted text - > > Ok, so the TDO is outputing a waveform in the right range of 0 to > 3.2V, but the not showing up in the impact software. =A0This means that > the problem is in your custom cable. > > I can't tell exactly how the cable was constructed from the circuit > that you posted as the part numbers are not complete and there are no > VCC connections of any type. =A0Have you put a scope on the TDO output > of the "LVC25" and the "HCT08" devices? > > Ed McGettigan > -- > Xilinx Inc. LVC125 is powered by 3V3. HCT08 by 5V (to comply with the parallel port) No, I didn't put the scope directly on HCT08, but that must work, since I just tested it again with Spartan 2. Looks like something on my Spartan 3A board is wrong, but don't know what. Here is the sch of Spartan 3A board: http://www41.zippyshare.com/v/38225858/file.html notes: X1 and U2 are not populated. pins not shown on FPGA are GND pins. S1, S2 and S3 are the connecting cable to parallel JTAG prog. Currently, PUDC(99), CS(46) and INIT(48) are pulled to 3V3. (I've soldered 3 extra resistors). PROG has R9 already. M0, M1, M2, DONE, CCLK, DIN and all GCKS are floating. As for the rest of the plain I/O pins: some are floating, some are connected to 3V3 micro.Article: 150654
I should add that S1 and S2 are two-pin connectors, but have five wires: two signals and three GNDs, which are cut just above the connector.Article: 150655
On Jan 31, 2:17=A0pm, aleksa <aleks...@gmail.com> wrote: > I should add that S1 and S2 are two-pin connectors, > but have five wires: two signals and three GNDs, > which are cut just above the connector. Two pin connectors, but five wires??? Could you have a short in this bundle? You should still check the LVC25 and HCT08 connections to see if the TDO signal is getting through. Ed McGettigan -- Xilinx Inc.Article: 150656
You need to probe TDI,TMS and TCK as close to the FPGA pins as possible, and TDO at the parallel port. Are you able to grab a full IDCODE read with all signals on a 4ch scope or logic analyzer? I'd like to see that image.Article: 150657
"Axel Mammes" <fpgausenet@gmail.com> wrote in message news:9e4fa494-8e3b-4b87-ab50-051fcadc4702@y35g2000prc.googlegroups.com... > Hi everyone, > > I'm looking for someone that can develop an FPGA based multiUART with > 32 UARTs for me. > > My software will run on this board: h**p://www.andahammer.com/mini35- > sdk. > > The mini2440 ARM board has 40 pin system expansion bus connector that > will connect to the multiuart PCB you develop. > > Each UART in the multiUART will connect to a gasoline dispenser using > optoisolated 20mA, 30 mA, 45mA current loop. I will provide schematics > for the TTL-current loop conversion. > > I was thinking the UARTs could be the 16750 from opencores.org. It's > supposed to be stable and it works with standard Linux drivers. h**p:// > opencores.org/project,uart16750 > > Check out the schematics of a mini2440 expansion card that Eric > Brombaugh already developed. > h**p://members.cox.net/ebrombaugh1/synth/mini_2440_fpga/index.html > > > > Regards > Axel How much are you thinking of paying ? MKArticle: 150658
On Feb 1, 9:03=A0am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > You need to probe TDI,TMS and TCK as close to the FPGA pins as possible, = and > TDO at the parallel port. > Are you able to grab a full IDCODE read with all signals on a 4ch scope o= r > logic analyzer? I'd like to see that image. OK, I have it working now. I had series res on JTAG side, but not on the FPGA side. I've added them (330E) on all signals, and it works now. Here is the photo of the TMS on scope: http://www23.zippyshare.com/v/50101972/file.html before/after means before/after adding series res on FPGA. Before, LOW level was 0.2V, now is 0.4V. I'll fix that later. And will also use smaller R. The photo is of the TMS. TDI and TCK are similar. TDO I still didn't check, because its not easy to put a probe on a comp below desk. Anyway, signal integrity will be the first thing to check from now on, regardless whether it works on Spartan 2 or not :)Article: 150659
Thanks everyoneArticle: 150660
Xilinx press release here: http://press.xilinx.com/phoenix.zhtml?c=212763&p=irol-newsArticle&ID=1521536 Google News results here: http://www.google.co.uk/search?q=Xilinx+Acquires+AutoESL&oi=news_group&ct=title I wonder how many limbs the tool s/w will cost... --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150661
Hi, Sorry if I'm posting a little bit out of topic here but I'm kinda confused. I read about the PCIe protocol, I read the Xilinx documentation about their PCIe EP and I have a quesstion: I understand that the CPU, through the RC, controls the transfer (issuing a read or write command) but how does the processor know when to issue the read command? I mean if I have a memory, on the EP side, that is updated every lets say 3 sec with new data how do I read the new data: does the software on the CPU side have to make read requests every 3 sec or does the EP signal an interrupt every time new data is available, or...? Thanks, Sebastian --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150662
PCI Express does support interrupts so an interrupt could be generated when new data was available. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150663
In PCIe data transfers either reads or writes can be initiated from either the main processor end or the card end. Interrupts unlike conevntional PCI use an in-band message (data transfer) to signal an interrupt on or off. This gives you 2 principal options. The first is for a memory pointer to written and stored on the card so it can move data directly to memory. It might then use an interrupt to get the processor to process the data. The second, less efficient, way is to store data at the card end and interrupt the processor to read the data and then move it to memory. John Adair Enterpoint Ltd - Home of Raggedstone2. The Spartan-6 PCIe Development Board. On Feb 1, 4:31=A0pm, "sebas" <tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote: > Hi, > > Sorry if I'm posting a little bit out of topic here but I'm kinda confuse= d. > I read about the PCIe protocol, I read the Xilinx documentation about the= ir > PCIe EP and I have a quesstion: I understand that the CPU, through the RC= , > controls the transfer (issuing a read or write command) but how does the > processor know when to issue the read command? I mean if I have a memory, > on the EP side, that is updated every lets say 3 sec with new data how do= I > read the new data: does the software on the CPU side have to make read > requests every 3 sec or does the EP signal an interrupt every time new da= ta > is available, or...? > > Thanks, > Sebastian =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comArticle: 150664
Hey, Thanks for the reply. What do you mean by not efficient? I only have few bytes to transmit (why I use PCIe it's a long story, let's just not get into in to it :) ) so I think the two situations described by you are the same in this case. Am I right or didn't I understand your post? Thanks >In PCIe data transfers either reads or writes can be initiated from >either the main processor end or the card end. Interrupts unlike >conevntional PCI use an in-band message (data transfer) to signal an >interrupt on or off. > >This gives you 2 principal options. The first is for a memory pointer >to written and stored on the card so it can move data directly to >memory. It might then use an interrupt to get the processor to process >the data. > >The second, less efficient, way is to store data at the card end and >interrupt the processor to read the data and then move it to memory. > >John Adair >Enterpoint Ltd - Home of Raggedstone2. The Spartan-6 PCIe Development >Board. > > >On Feb 1, 4:31=A0pm, "sebas" ><tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote: >> Hi, >> >> Sorry if I'm posting a little bit out of topic here but I'm kinda confuse= >d. >> I read about the PCIe protocol, I read the Xilinx documentation about the= >ir >> PCIe EP and I have a quesstion: I understand that the CPU, through the RC= >, >> controls the transfer (issuing a read or write command) but how does the >> processor know when to issue the read command? I mean if I have a memory, >> on the EP side, that is updated every lets say 3 sec with new data how do= > I >> read the new data: does the software on the CPU side have to make read >> requests every 3 sec or does the EP signal an interrupt every time new da= >ta >> is available, or...? >> >> Thanks, >> Sebastian =A0 =A0 =A0 =A0 =A0 >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150665
I am interested in bit-accurate C / C++ modeling of hardware. I have only found two open source projects: Signal Processing Using C++ (http://spuc.sourceforge.net/) and C4Hardware (http://sigpromu.org/ c4hardware/). Does anyone have experience with either of these, or other, projects? Thanks in advance. StephenArticle: 150666
On 1 Feb., 16:30, "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > Xilinx press release here:http://press.xilinx.com/phoenix.zhtml?c=3D21276= 3&p=3Dirol-newsArticle&ID=3D... > > Google News results here:http://www.google.co.uk/search?q=3DXilinx+Acquir= es+AutoESL&oi=3Dnews_grou... > > I wonder how many limbs the tool s/w will cost... > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Hi, why are you concerned about the price now? The tool was already available before Xilinx acquired the company. The real question is: How long will it still be sold separtately, and when will it finally be absorbed into one of the ISE editions. And the next question that may be asked is: Who's next? (Sigasi...???) :-) Regards EilertArticle: 150667
The read method is not efficient because often the processor takes in the data and then writes it out to memory so 2 data movement actions. That mechanism does vary a little with motherboard architecture and that might be offloaded to a peripheral. If it's a small amount of data it is fine to do it this way. For large amounts of data the card end doing the initiation is much better and faster. It's a single transfer and much less affected by other tasks that a CPU might be running. John Adair Enterpoint Ltd. On Feb 1, 11:11=A0pm, "andreiseb" <andrei.jacota@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > Hey, > > Thanks for the reply. What do you mean by not efficient? I only have few > bytes to transmit (why I use PCIe it's a long story, let's just not get > into in to it :) ) so I think the two situations described by you are the > same in this case. Am I right or didn't I understand your post? > > Thanks > > > > > > >In PCIe data transfers either reads or writes can be initiated from > >either the main processor end or the card end. Interrupts unlike > >conevntional PCI use an in-band message (data transfer) to signal an > >interrupt on or off. > > >This gives you 2 principal options. The first is for a memory pointer > >to written and stored on the card so it can move data directly to > >memory. It might then use an interrupt to get the processor to process > >the data. > > >The second, less efficient, way is to store data at the card end and > >interrupt the processor to read the data and then move it to memory. > > >John Adair > >Enterpoint Ltd - Home of Raggedstone2. The Spartan-6 PCIe Development > >Board. > > >On Feb 1, 4:31=3DA0pm, "sebas" > ><tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote: > >> Hi, > > >> Sorry if I'm posting a little bit out of topic here but I'm kinda > confuse=3D > >d. > >> I read about the PCIe protocol, I read the Xilinx documentation about > the=3D > >ir > >> PCIe EP and I have a quesstion: I understand that the CPU, through the > RC=3D > >, > >> controls the transfer (issuing a read or write command) but how does > the > >> processor know when to issue the read command? I mean if I have a > memory, > >> on the EP side, that is updated every lets say 3 sec with new data how > do=3D > > I > >> read the new data: does the software on the CPU side have to make read > >> requests every 3 sec or does the EP signal an interrupt every time new > da=3D > >ta > >> is available, or...? > > >> Thanks, > >> Sebastian =3DA0 =3DA0 =3DA0 =3DA0 =3DA0 > > >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 > >> Posted throughhttp://www.FPGARelated.com > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comArticle: 150668
"aleksa" <aleksazr@gmail.com> wrote in message news:99e0701d-1068-4416-b18a-a19ed7aa5166@x5g2000prf.googlegroups.com... > Thanks everyone Just to close up, the res is probably only needed on the TCK to avoid "ringing" wich may be detected as multiple clocks at the edges. It is caused by bad impedance match on the transmission line. The problem the res can add is lower max programming speed because of slower rise/fall times, but usually the speed is not near the problem area on such parallel devices.Article: 150669
Why not use SystemC? Install Visual C++ Express 2010, compile the OSCI reference simulator and you have a great development environment. Just a thought, Hans www.ht-lab.com >wrote in message >news:963669a5-c3e3-4c80-86b6-b43d2af29437@u4g2000yqi.googlegroups.com... > >I am interested in bit-accurate C / C++ modeling of hardware. I have >only found two open source projects: Signal Processing Using C++ >(http://spuc.sourceforge.net/) and C4Hardware (http://sigpromu.org/ >c4hardware/). > >Does anyone have experience with either of these, or other, projects? > >Thanks in advance. > >StephenArticle: 150670
Hello everybody, I got on Friday a new board, with brand new FPGAs soldered rightly (it seem= s). Now I test my non-working FW and the 3 boards that I have behaves equally, = so I have only two possibility: a_ the synthesis tool is failing, bu I tried the same FW on a different mac= hine with a brand new copy of ISE 12.4 installed and it behaves the same in= each and every board. b_ my coding style is somehow wrong. I checked the Xilinx's seminar on the = web at this address and I watched all the basic HDL and Spartan 3 FPGA spec= ific seminars. Ok, my code is not perfectly written but not with huge error= s (for example everything is synchronous the reset path is correctly done, = but I use nested if and case that are not the right thing (this is what Xil= inx says)=20 For example, the reset code pointed out by Mike here https://groups.google.= com/d/msg/comp.arch.fpga/eQ5EeHECOQw/rO5YroyQhaUJ is, in Xilinx's opinion, not the best choice. Now I decided to rewrite the whole project following Xilinx's advices but b= efore, please, focus on these two questions and only on these two: 1_ since I have constrained the clock period and offset in and out, with on= ly one clock domain in the entire FPGA( in other words everything is clocke= d by the same source) and all the constraints are met must I trust the cloc= k report? Even if the design does not behave as expected? I mean, with the = same code and constraints, only changing a synthesis parameters (from AUTO = to one-hot encoding, for example) the constraints are always met and the ti= ming report does not show any setup/hold violation, how is it possible that= the FPGA behaves differently, if not for a synthesis error/mistake or an H= W failure? 2_ If this is normal: if, changing the code style, or the used resources, t= he behaviour changes even with all the constraints met, how am I supposed t= o use a debugger like CHIPSCOPE, which uses the internal FPGA resources? In= other words, if introducing a CHIPSCOPE debugger the used resources change= and subsequently is expected that the behaviour changes, how is possible t= o debug correctly? Only doing errors is possible to learn, but without understanding them is n= ot possible to learn at all. Many thanks, Emanuele P.S. I am using the ISE tool for my projects, have you got advices for a di= fferent/surely-better tool for synthesis, translate, map and PAR with also = a spread availability of IPs?Article: 150671
Ok, I understand. The interrupt that has to pe generated is it a MSI generated at TLP level and I have to generate it through the user interface or is it a different "interrupt" automatically generated on a different layer and I don't have to worry about it. The reason I'm asking is because I haven't found any reference to this issue in the Xlinix' EP User Guide. >The read method is not efficient because often the processor takes in >the data and then writes it out to memory so 2 data movement actions. >That mechanism does vary a little with motherboard architecture and >that might be offloaded to a peripheral. If it's a small amount of >data it is fine to do it this way. For large amounts of data the card >end doing the initiation is much better and faster. It's a single >transfer and much less affected by other tasks that a CPU might be >running. > >John Adair >Enterpoint Ltd. > >On Feb 1, 11:11=A0pm, "andreiseb" ><andrei.jacota@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: >> Hey, >> >> Thanks for the reply. What do you mean by not efficient? I only have few >> bytes to transmit (why I use PCIe it's a long story, let's just not get >> into in to it :) ) so I think the two situations described by you are the >> same in this case. Am I right or didn't I understand your post? >> >> Thanks >> >> >> >> >> >> >In PCIe data transfers either reads or writes can be initiated from >> >either the main processor end or the card end. Interrupts unlike >> >conevntional PCI use an in-band message (data transfer) to signal an >> >interrupt on or off. >> >> >This gives you 2 principal options. The first is for a memory pointer >> >to written and stored on the card so it can move data directly to >> >memory. It might then use an interrupt to get the processor to process >> >the data. >> >> >The second, less efficient, way is to store data at the card end and >> >interrupt the processor to read the data and then move it to memory. >> >> >John Adair >> >Enterpoint Ltd - Home of Raggedstone2. The Spartan-6 PCIe Development >> >Board. >> >> >On Feb 1, 4:31=3DA0pm, "sebas" >> ><tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote: >> >> Hi, >> >> >> Sorry if I'm posting a little bit out of topic here but I'm kinda >> confuse=3D >> >d. >> >> I read about the PCIe protocol, I read the Xilinx documentation about >> the=3D >> >ir >> >> PCIe EP and I have a quesstion: I understand that the CPU, through the >> RC=3D >> >, >> >> controls the transfer (issuing a read or write command) but how does >> the >> >> processor know when to issue the read command? I mean if I have a >> memory, >> >> on the EP side, that is updated every lets say 3 sec with new data how >> do=3D >> > I >> >> read the new data: does the software on the CPU side have to make read >> >> requests every 3 sec or does the EP signal an interrupt every time new >> da=3D >> >ta >> >> is available, or...? >> >> >> Thanks, >> >> Sebastian =3DA0 =3DA0 =3DA0 =3DA0 =3DA0 >> >> >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 >> >> Posted throughhttp://www.FPGARelated.com >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150672
>Hi, > >Sorry if I'm posting a little bit out of topic here but I'm kinda confused. >I read about the PCIe protocol, I read the Xilinx documentation about their >PCIe EP and I have a quesstion: I understand that the CPU, through the RC, >controls the transfer (issuing a read or write command) but how does the >processor know when to issue the read command? I mean if I have a memory, >on the EP side, that is updated every lets say 3 sec with new data how do I >read the new data: does the software on the CPU side have to make read >requests every 3 sec or does the EP signal an interrupt every time new data >is available, or...? > >Thanks, >Sebastian > >--------------------------------------- >Posted through http://www.FPGARelated.com > You might get useful answers posting on the Xilinx Support Forum: http://forums.xilinx.com/t5/PCI-Express/bd-p/PCIe --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150673
On Feb 2, 8:56=A0am, Emanuele Carraro <emanuele83katam...@googlemail.com> wrote: > Hello everybody, > I got on Friday a new board, with brand new FPGAs soldered rightly (it se= ems). > Now I test my non-working FW and the 3 boards that I have behaves equally= , so I have only two possibility: > > a_ the synthesis tool is failing, bu I tried the same FW on a different m= achine with a brand new copy of ISE 12.4 installed and it behaves the same = in each and every board. > > b_ my coding style is somehow wrong. I checked the Xilinx's seminar on th= e web at this address and I watched all the basic HDL and Spartan 3 FPGA sp= ecific seminars. Ok, my code is not perfectly written but not with huge err= ors (for example everything is synchronous the reset path is correctly done= , but I use nested if and case that are not the right thing (this is what X= ilinx says) > For example, the reset code pointed out by Mike herehttps://groups.google= .com/d/msg/comp.arch.fpga/eQ5EeHECOQw/rO5YroyQhaUJ > is, in Xilinx's opinion, not the best choice. > > Now I decided to rewrite the whole project following Xilinx's advices but= before, please, focus on these two questions and only on these two: > > 1_ since I have constrained the clock period and offset in and out, with = only one clock domain in the entire FPGA( in other words everything is cloc= ked by the same source) and all the constraints are met must I trust the cl= ock report? Even if the design does not behave as expected? I mean, with th= e same code and constraints, only changing a synthesis parameters (from AUT= O to one-hot encoding, for example) the constraints are always met and the = timing report does not show any setup/hold violation, how is it possible th= at the FPGA behaves differently, if not for a synthesis error/mistake or an= HW failure? > > 2_ If this is normal: if, changing the code style, or the used resources,= the behaviour changes even with all the constraints met, how am I supposed= to use a debugger like CHIPSCOPE, which uses the internal FPGA resources? = In other words, if introducing a CHIPSCOPE debugger the used resources chan= ge and subsequently is expected that the behaviour changes, how is possible= to debug correctly? > > Only doing errors is possible to learn, but without understanding them is= not possible to learn at all. > > Many thanks, > Emanuele > > P.S. I am using the ISE tool for my projects, have you got advices for a = different/surely-better tool for synthesis, translate, map and PAR with als= o a spread availability of IPs? It is an interesting problem for sure. To answer your questions: a) I really doubt the synth tool is producing incorrect logic. Imagine the millions of different HDL projects that are synthesized, if there was a fundamental RTL to logic translation flaw, it would be a big deal. Just in case, it would be best to use all the default settings on the synth tool (if you have changed them). The defaults would naturally be what 99% of people use, so have had the most exercising in reality. b) This is possible too - It is still possible to use perfect syntax, and style, but still write something that is somehow asynchronous, or crosses clock domains incorrectly. Unfortunately coding guidelines can never prevent those kinds of mistakes. Lint tools can help find some structures that could cause trouble, as well as CDC tools (clock domain crossing). 1) Having one clock domain simplifies things, as well as the fact that you have constrained the inputs. but a few questions - - do you use any PLL/DLL/MMCM logic. Have you ensured everything is setup correctly here and any skews are being accounted for? - in follow on to the above - you say there is one clock domain - but is it actually the very same NET going to each piece of code, or are there somehow different nets of the same frequency that are driving different blocks. Because even though a clock may be the same frequency, and come from the same source point - if there are not the same net, there can be phase/skew differences that would have to be handled carefully - have you accounted for all inputs? are they all constrained? can any of them glitch or be otherwise asynchronous? - do you have proper reset synchonizers to release the reset? 2) Chipscope has helped me countless times, it really is a great tool. I do see the dilemma here where you are concerned that adding it will change the utilization, and as a result change the behavior again. So the only suggestions i have here are: - turn on design preservation. This should retain the synthesis and placement/routing of unchanged parts of the design, and should fit chipscope blocks into 'free' space. Of course some of the design may have to be moved, but the tools do all they can to prevent that. If the place and route are preserved, then so should design behaviour - if inserting chipscope does cause the design to start functioning - then I would keep iterating and making small tweaks until the design is failing once more, but this time with chipscope in. Once you get that, setting up chipscope to monitor the design won't affect its running so you should be able to zero in on where the problem first occurs. - try to think up front how to partition your design so you can determine what points to probe so failures can be detected by chipscope. As for alternative tools - on the synth side there are a number of choices, but for map/par, I believe you have to use the ISE versions. you could try plan-ahead, while it still uses the ISE tools under the hood, it does allow you to easily floor-plan your design. It won't fix this issue, but it should make working with / iterating / probing signals with chipscope easier.Article: 150674
The Xilinx EP guide gives details about generating interrupts. You just set the appropriate signals on the core and an interrupt is generated. Jon --------------------------------------- Posted through http://www.FPGARelated.com
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