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Threads Starting Mar 2009

138584: 09/03/01: dracosilv: New person to CPLD programming
    138586: 09/03/01: Rich Webb: Re: New person to CPLD programming
        138587: 09/03/01: dracosilv: Re: New person to CPLD programming
            138589: 09/03/01: dracosilv: Re: New person to CPLD programming
                138591: 09/03/01: doug: Re: New person to CPLD programming
                    138593: 09/03/01: dracosilv: Re: New person to CPLD programming
                        138596: 09/03/01: doug: Re: New person to CPLD programming
                            138597: 09/03/01: Glen Herrmannsfeldt: Re: New person to CPLD programming
                                138598: 09/03/01: doug: Re: New person to CPLD programming
                                    138600: 09/03/01: Glen Herrmannsfeldt: Re: New person to CPLD programming
            138590: 09/03/01: doug: Re: New person to CPLD programming
                138592: 09/03/01: dracosilv: Re: New person to CPLD programming
                    138594: 09/03/01: doug: Re: New person to CPLD programming
        138588: 09/03/01: Antti.Lukats@googlemail.com: Re: New person to CPLD programming
        138595: 09/03/01: Antti.Lukats@googlemail.com: Re: New person to CPLD programming
    138599: 09/03/01: -jg: Re: New person to CPLD programming
        138605: 09/03/01: dracosilv: Re: New person to CPLD programming
            138616: 09/03/02: Alex Freed: Re: New person to CPLD programming
                138721: 09/03/05: dracosilv: Re: New person to CPLD programming
                138737: 09/03/06: Mike Treseler: Re: New person to CPLD programming
                    138741: 09/03/06: Jonathan Bromley: Re: New person to CPLD programming
    138629: 09/03/02: Rob Gaddi: Re: New person to CPLD programming
    138630: 09/03/02: Rob Gaddi: Re: New person to CPLD programming
        138719: 09/03/05: Alex Freed: Re: New person to CPLD programming
            138725: 09/03/06: Jonathan Bromley: Re: New person to CPLD programming
138585: 09/03/01: Antti: Antti-Brain issue 6 released
    138620: 09/03/02: <goouse@twinmail.de>: Re: Antti-Brain issue 6 released
    138624: 09/03/02: M.Randelzhofer: Re: Antti-Brain issue 6 released
    138631: 09/03/02: rickman: Re: Antti-Brain issue 6 released
    138632: 09/03/02: Antti.Lukats@googlemail.com: Re: Antti-Brain issue 6 released
    138638: 09/03/02: rickman: Re: Antti-Brain issue 6 released
138601: 09/03/01: Vesh: Character generator ROM and VGA controller for Spartan 3E
    138602: 09/03/01: Glen Herrmannsfeldt: Re: Character generator ROM and VGA controller for Spartan 3E
        138609: 09/03/01: Glen Herrmannsfeldt: Re: Character generator ROM and VGA controller for Spartan 3E
            138612: 09/03/02: Hal Murray: Re: Character generator ROM and VGA controller for Spartan 3E
                138614: 09/03/02: Glen Herrmannsfeldt: Re: Character generator ROM and VGA controller for Spartan 3E
        138645: 09/03/02: Chris Abele: Re: Character generator ROM and VGA controller for Spartan 3E
    138607: 09/03/01: Antti.Lukats@googlemail.com: Re: Character generator ROM and VGA controller for Spartan 3E
    138619: 09/03/02: Symon: Re: Character generator ROM and VGA controller for Spartan 3E
    138644: 09/03/03: Mark McDougall: Re: Character generator ROM and VGA controller for Spartan 3E
        138647: 09/03/02: Glen Herrmannsfeldt: Re: Character generator ROM and VGA controller for Spartan 3E
            138748: 09/03/07: james: Re: Character generator ROM and VGA controller for Spartan 3E
    138646: 09/03/02: Vesh: Re: Character generator ROM and VGA controller for Spartan 3E
138603: 09/03/01: randy: timequest error
    138615: 09/03/02: Alan Fitch: Re: timequest error
138618: 09/03/02: knight: ODDR output to use internally
    138621: 09/03/02: Symon: Re: ODDR output to use internally
    138623: 09/03/02: knight: Re: ODDR output to use internally
    138627: 09/03/02: Nathan Bialke: Re: ODDR output to use internally
    138650: 09/03/02: <goouse@twinmail.de>: Re: ODDR output to use internally
138622: 09/03/02: <chenyong20000@gmail.com>: PCIE with Avalon I/F
    138634: 09/03/02: LittleAlex: Re: PCIE with Avalon I/F
138625: 09/03/02: bjzhangwn@gmail.com: how to communicate with NiosII
    138635: 09/03/02: LittleAlex: Re: how to communicate with NiosII
138637: 09/03/02: John Adair: New Boards
    138639: 09/03/02: rickman: Re: New Boards
    138641: 09/03/02: John Adair: Re: New Boards
    138642: 09/03/02: John Adair: Re: New Boards
    138643: 09/03/02: John Adair: Re: New Boards
138651: 09/03/03: Zorjak: XILINX sysgen cordic divider
    138664: 09/03/03: Nicholas Paul Collin Gloucester: Re: XILINX sysgen cordic divider
138652: 09/03/03: Andreas Ehliar: Re: Re-synthesizing with minor changes
    138661: 09/03/03: Glen Herrmannsfeldt: Re: Re-synthesizing with minor changes
    138663: 09/03/03: Glen Herrmannsfeldt: Re: Re-synthesizing with minor changes
138653: 09/03/03: Essy: Re-synthesizing with minor changes
    138654: 09/03/03: Alan Fitch: Re: Re-synthesizing with minor changes
    138655: 09/03/03: KJ: Re: Re-synthesizing with minor changes
        138662: 09/03/03: Sean Durkin: Re: Re-synthesizing with minor changes
    138656: 09/03/03: Essy: Re: Re-synthesizing with minor changes
    138658: 09/03/03: Mike Treseler: Re: Re-synthesizing with minor changes
    138660: 09/03/03: KJ: Re: Re-synthesizing with minor changes
    138691: 09/03/04: rickman: Re: Re-synthesizing with minor changes
138657: 09/03/03: S. Bernstein: Virtex6 Virtex4 FPGA compatibility
    138668: 09/03/03: Barry: Re: Virtex6 Virtex4 FPGA compatibility
    138669: 09/03/03: Sean Durkin: Re: Virtex6 Virtex4 FPGA compatibility
        138693: 09/03/05: Martin Thompson: Spartan 6 3.3V (was Re: Virtex6 Virtex4 FPGA compatibility)
            138709: 09/03/05: Glen Herrmannsfeldt: Re: Spartan 6 3.3V (was Re: Virtex6 Virtex4 FPGA compatibility)
            138729: 09/03/06: Martin Thompson: Re: Spartan 6 3.3V
            138756: 09/03/09: Kim Enkovaara: Re: Spartan 6 3.3V (was Re: Virtex6 Virtex4 FPGA compatibility)
                138759: 09/03/09: Uwe Bonnes: Re: Spartan 6 3.3V (was Re: Virtex6 Virtex4 FPGA compatibility)
    138692: 09/03/04: rickman: Re: Virtex6 Virtex4 FPGA compatibility
    138700: 09/03/05: rickman: Re: Spartan 6 3.3V (was Re: Virtex6 Virtex4 FPGA compatibility)
    138705: 09/03/05: <cs_posting@hotmail.com>: Re: Spartan 6 3.3V (was Re: Virtex6 Virtex4 FPGA compatibility)
    138706: 09/03/05: austin: Re: Spartan 6 3.3V (was Re: Virtex6 Virtex4 FPGA compatibility)
    138722: 09/03/05: rickman: Re: Spartan 6 3.3V (was Re: Virtex6 Virtex4 FPGA compatibility)
138665: 09/03/03: John Adair: New Boards
138666: 09/03/03: John Adair: New Boards
138667: 09/03/03: John Adair: Craignell2 and Mulldonnoch2
    138738: 09/03/06: Antti.Lukats@googlemail.com: Re: Craignell2 and Mulldonnoch2
138671: 09/03/03: Muzaffer Kal: 32x32 -> 64 multiplier in virtex-5
    138681: 09/03/04: <newman5382@yahoo.com>: Re: 32x32 -> 64 multiplier in virtex-5
        138685: 09/03/04: Glen Herrmannsfeldt: Re: 32x32 -> 64 multiplier in virtex-5
            138687: 09/03/04: Muzaffer Kal: Re: 32x32 -> 64 multiplier in virtex-5
        138686: 09/03/04: <newman5382@yahoo.com>: Re: 32x32 -> 64 multiplier in virtex-5
        138688: 09/03/04: <newman5382@yahoo.com>: Re: 32x32 -> 64 multiplier in virtex-5
    138742: 09/03/06: Eric Smith: Re: 32x32 -> 64 multiplier in virtex-5
138675: 09/03/04: Andreas Ehliar: Re: writing current date to a register
138676: 09/03/04: <oktem@su.sabanciuniv.edu>: writing current date to a register
    138677: 09/03/04: <jprovidenza@yahoo.com>: Re: writing current date to a register
    138683: 09/03/04: Nico Coesel: Re: writing current date to a register
    138694: 09/03/05: Martin Thompson: Re: writing current date to a register
        138703: 09/03/05: Mike Treseler: Re: writing current date to a register
            138708: 09/03/05: Glen Herrmannsfeldt: Re: writing current date to a register
                138710: 09/03/05: Mike Treseler: Re: writing current date to a register
                    138711: 09/03/05: Glen Herrmannsfeldt: Re: writing current date to a register
                        138715: 09/03/05: Hal Murray: Re: writing current date to a register
    138695: 09/03/05: <oktem@su.sabanciuniv.edu>: Re: writing current date to a register
138678: 09/03/04: John Adair: Warning Search Engine Links
    138682: 09/03/04: Gavin Scott: Re: Warning Search Engine Links
        138689: 09/03/04: Hal Murray: Re: Warning Search Engine Links
            138690: 09/03/04: Gavin Scott: Re: Warning Search Engine Links
    138684: 09/03/04: John Adair: Re: Warning Search Engine Links
    138696: 09/03/05: John Adair: Re: Warning Search Engine Links
138697: 09/03/05: <igalkogan@gmail.com>: Spartan 3AN wake up problem
    138701: 09/03/05: gabor: Re: Spartan 3AN wake up problem
138698: 09/03/05: deep: synchronization problem
    138699: 09/03/05: <goouse@twinmail.de>: Re: synchronization problem
    138801: 09/03/11: bish: Re: synchronization problem
    138820: 09/03/11: bish: Re: synchronization problem
    138822: 09/03/11: rickman: Re: synchronization problem
138704: 09/03/05: <justforpretend@gmail.com>: Want to buy: FPGA T-Shirt $$
    138726: 09/03/06: wolahr: Re: Want to buy: FPGA T-Shirt $$
        138749: 09/03/07: <'use_real_email'>: Re: Want to buy: FPGA T-Shirt $$
    138772: 09/03/09: rickman: Re: Want to buy: FPGA T-Shirt $$
        138843: 09/03/12: Ed McGettigan: Re: Want to buy: FPGA T-Shirt $$
138707: 09/03/05: Vesh: NGDBuild 604 Error while implementing the character generator design
    138727: 09/03/06: Alan Fitch: Re: NGDBuild 604 Error while implementing the character generator
138712: 09/03/05: Mike Treseler: make ise take ngc as source
    138717: 09/03/05: Muzaffer Kal: Re: make ise take ngc as source
        138735: 09/03/06: Mike Treseler: Re: make ise take ngc as source
            138739: 09/03/06: Muzaffer Kal: Re: make ise take ngc as source
    138724: 09/03/06: Jan Pech: Re: make ise take ngc as source
        138734: 09/03/06: Mike Treseler: Re: make ise take ngc as source
    138733: 09/03/06: gabor: Re: make ise take ngc as source
        138736: 09/03/06: Mike Treseler: Re: make ise take ngc as source
138713: 09/03/05: Keith M: DDR access on Spartan 3E 500 Starter Kit
    138714: 09/03/05: Glen Herrmannsfeldt: Re: DDR access on Spartan 3E 500 Starter Kit
        138720: 09/03/05: Glen Herrmannsfeldt: Re: DDR access on Spartan 3E 500 Starter Kit
            138731: 09/03/06: Martin Thompson: Re: DDR access on Spartan 3E 500 Starter Kit
    138716: 09/03/05: Keith M: Re: DDR access on Spartan 3E 500 Starter Kit
    138888: 09/03/13: <vinayaksanthosh@gmail.com>: Re: DDR access on Spartan 3E 500 Starter Kit
    138903: 09/03/13: Bryan: Re: DDR access on Spartan 3E 500 Starter Kit
138730: 09/03/06: <hassen.karray@gmail.com>: 2 Modules working independently but not together on FPGA
    138732: 09/03/06: KJ: Re: 2 Modules working independently but not together on FPGA
138743: 09/03/06: Andrew W. Hill: Making static C libraries in Xilinx EDK
    138745: 09/03/06: Antti.Lukats@googlemail.com: Re: Making static C libraries in Xilinx EDK
138746: 09/03/07: Antti: Embedded World 2009: Antti Brain special issue
138747: 09/03/07: HT-Lab: lunch time videos
138750: 09/03/08: bish: Xst:1710 warning problem
138751: 09/03/08: Mad I.D.: Dual port RAM on Spartan
    138752: 09/03/08: Mad I.D.: Re: Dual port RAM on Spartan
        138754: 09/03/08: Thomas Womack: Re: Dual port RAM on Spartan
    138753: 09/03/08: Peter Alfke: Re: Dual port RAM on Spartan
138755: 09/03/08: JSreeniv: Regarding to the "change in duty Cycle"
    138757: 09/03/09: <goouse@twinmail.de>: Re: Regarding to the "change in duty Cycle"
138758: 09/03/09: murlary@gmail.com: PATA-SATA simulation model
138761: 09/03/09: maxascent: FPGA IO Routing
    138767: 09/03/09: Kolja: Re: FPGA IO Routing
        138770: 09/03/09: maxascent: Re: FPGA IO Routing
138762: 09/03/09: Pritha Ghoshal: Image loading into FPGA - from computer
    138769: 09/03/09: glen herrmannsfeldt: Re: Image loading into FPGA - from computer
        138773: 09/03/09: glen herrmannsfeldt: Re: Image loading into FPGA - from computer
    138771: 09/03/09: Pritha Ghoshal: Re: Image loading into FPGA - from computer
    138774: 09/03/09: <jaxato@gmail.com>: Re: Image loading into FPGA - from computer
138763: 09/03/09: <longbrmb@gmail.com>: Timing requirements for generating off-chip clock with DDR register
    138764: 09/03/09: Mike Treseler: Re: Timing requirements for generating off-chip clock with DDR register
    138765: 09/03/09: <jprovidenza@yahoo.com>: Re: Timing requirements for generating off-chip clock with DDR
    138766: 09/03/09: KJ: Re: Timing requirements for generating off-chip clock with DDR
    138768: 09/03/09: <longbrmb@gmail.com>: Re: Timing requirements for generating off-chip clock with DDR
    138775: 09/03/09: John Eaton: Re: Timing requirements for generating off-chip clock with DDR register
        138786: 09/03/10: John Eaton: Re: Timing requirements for generating off-chip clock with DDR register
    138782: 09/03/10: <longbrmb@gmail.com>: Re: Timing requirements for generating off-chip clock with DDR
138776: 09/03/10: bobrics: Verify failed between adress... problem
138777: 09/03/10: jag9624: Finding aligned clock transitions with state machine
    138778: 09/03/10: furia: Re: Finding aligned clock transitions with state machine
        138779: 09/03/10: jag9624: Re: Finding aligned clock transitions with state machine
    138783: 09/03/10: Rob Gaddi: Re: Finding aligned clock transitions with state machine
    138788: 09/03/10: Andy Peters: Re: Finding aligned clock transitions with state machine
    138789: 09/03/10: <newman5382@yahoo.com>: Re: Finding aligned clock transitions with state machine
        138796: 09/03/11: jag9624: Re: Finding aligned clock transitions with state machine
        138810: 09/03/11: jag9624: Re: Finding aligned clock transitions with state machine
    138803: 09/03/11: Andy Peters: Re: Finding aligned clock transitions with state machine
    138819: 09/03/11: <newman5382@yahoo.com>: Re: Finding aligned clock transitions with state machine
138780: 09/03/10: Jan Decaluwe: Integer arithmetic in HDLs
    138781: 09/03/10: Jacko: Re: Integer arithmetic in HDLs
    138787: 09/03/10: Andy Peters: Re: Integer arithmetic in HDLs
        138841: 09/03/12: Andy: Re: Integer arithmetic in HDLs
138784: 09/03/10: Svenn Are Bjerkem: Checking HDL syntax on command line with xilinx tools
    138785: 09/03/10: Mike Treseler: Re: Checking HDL syntax on command line with xilinx tools
        138797: 09/03/11: Nial Stewart: Re: Checking HDL syntax on command line with xilinx tools
    138793: 09/03/11: Alan Fitch: Re: Checking HDL syntax on command line with xilinx tools
    138800: 09/03/11: Petter Gustad: Re: Checking HDL syntax on command line with xilinx tools
138790: 09/03/10: knight: Xilinx TEMAC Core
    138791: 09/03/10: Antti.Lukats@googlemail.com: Re: Xilinx TEMAC Core
138792: 09/03/11: Antti: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
    138794: 09/03/11: Symon: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
    138795: 09/03/11: jag9624: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
    138815: 09/03/11: doug: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
        138818: 09/03/12: Symon: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
            138840: 09/03/12: Brian Drummond: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
            138848: 09/03/12: doug: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
    138826: 09/03/12: Antti.Lukats@googlemail.com: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
    138844: 09/03/12: <newsgroup@johnhandwork.com>: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
        138858: 09/03/12: Stef: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
            138860: 09/03/12: Stef: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
        138870: 09/03/12: Hal Murray: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
    138846: 09/03/12: Antti.Lukats@googlemail.com: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
    138859: 09/03/12: Antti.Lukats@googlemail.com: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
138798: 09/03/11: Martin Schoeberl: What happens at opencores.org?
    138877: 09/03/13: Jeremy Bennett: Re: What happens at opencores.org?
        138895: 09/03/14: Martin Schoeberl: Re: What happens at opencores.org?
        138896: 09/03/14: Martin Schoeberl: Re: What happens at opencores.org?
            139082: 09/03/20: Andreas Ehliar: Re: What happens at opencores.org?
    138879: 09/03/13: <marcus.erlandsson@gmail.com>: Re: What happens at opencores.org?
    138886: 09/03/13: Antti.Lukats@googlemail.com: Re: What happens at opencores.org?
    138887: 09/03/13: <marcus.erlandsson@gmail.com>: Re: What happens at opencores.org?
    138902: 09/03/13: rickman: Re: What happens at opencores.org?
    139090: 09/03/20: rickman: Re: What happens at opencores.org?
138799: 09/03/11: jacko: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138802: 09/03/11: Antti.Lukats@googlemail.com: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138804: 09/03/11: Jacko: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138806: 09/03/11: Niklas Holsti: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138867: 09/03/12: Hal Murray: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138873: 09/03/12: rickman: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138805: 09/03/11: Antti.Lukats@googlemail.com: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138891: 09/03/13: Jonathan Bromley: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138894: 09/03/13: Jacko: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138807: 09/03/11: <VAX9000@gmail.com>: Best way to write to LUT based CPLD from slow CPU?
    138808: 09/03/11: Jonathan Bromley: Re: Best way to write to LUT based CPLD from slow CPU?
    138811: 09/03/11: <VAX9000@gmail.com>: Re: Best way to write to LUT based CPLD from slow CPU?
    138829: 09/03/12: rickman: Re: Best way to write to LUT based CPLD from slow CPU?
138809: 09/03/11: <VAX9000@gmail.com>: asynchronous preloading a counter
    138814: 09/03/11: Andy Peters: Re: asynchronous preloading a counter
138812: 09/03/11: Steve: Xilinx design flow
138813: 09/03/11: Dirk Koch: A Builder for Component-based and Partial Runtime Reconfigurable
    138824: 09/03/11: Antti.Lukats@googlemail.com: Re: A Builder for Component-based and Partial Runtime Reconfigurable
138816: 09/03/11: Jacko: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138817: 09/03/11: Jacko: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138821: 09/03/11: rickman: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138823: 09/03/11: Digi Suji: I2C EEPROM
    138827: 09/03/12: <goouse@twinmail.de>: Re: I2C EEPROM
    138832: 09/03/12: gabor: Re: I2C EEPROM
    138878: 09/03/13: David Fejes: Re: I2C EEPROM
    138952: 09/03/16: gabor: Re: I2C EEPROM
    139602: 09/04/06: Digi Suji: Re: I2C EEPROM
138825: 09/03/11: Antti.Lukats@googlemail.com: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138828: 09/03/12: rickman: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138830: 09/03/12: -jg: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138831: 09/03/12: SUMAN: speeding hough tranformation in microblaze
    138835: 09/03/12: David Brown: Re: speeding hough tranformation in microblaze
    138857: 09/03/12: Benjamin Couillard: Re: speeding hough tranformation in microblaze
    138872: 09/03/12: Kolja: Re: speeding hough tranformation in microblaze
    138939: 09/03/15: SUMAN: Re: speeding hough tranformation in microblaze
138833: 09/03/12: SUMAN: DDR2 MEMORY INTERFACING INTERFACING WITH HARWARE CORE AND MICROBLAZE
    138834: 09/03/12: Antti.Lukats@googlemail.com: Re: DDR2 MEMORY INTERFACING INTERFACING WITH HARWARE CORE AND
138836: 09/03/12: Jacko: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138837: 09/03/12: Jacko: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138838: 09/03/12: <cpandya@yahoo.com>: How to initialize the Xilinx FIFO with predetermined value on
    138845: 09/03/12: <newsgroup@johnhandwork.com>: Re: How to initialize the Xilinx FIFO with predetermined value on
    138855: 09/03/12: <no_spa2005@yahoo.fr>: Re: How to initialize the Xilinx FIFO with predetermined value on
138839: 09/03/12: Antti.Lukats@googlemail.com: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138842: 09/03/12: Jacko: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138847: 09/03/12: Jacko: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138849: 09/03/12: Antti.Lukats@googlemail.com: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138850: 09/03/12: LittleAlex: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138851: 09/03/12: -jg: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138852: 09/03/12: Antti.Lukats@googlemail.com: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138853: 09/03/12: Jacko: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138854: 09/03/12: Antti.Lukats@googlemail.com: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138856: 09/03/12: Walter Banks: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138861: 09/03/12: Antti.Lukats@googlemail.com: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138862: 09/03/12: rickman: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138863: 09/03/12: rickman: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138864: 09/03/12: rickman: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138865: 09/03/12: rickman: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138866: 09/03/12: Antti.Lukats@googlemail.com: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138868: 09/03/12: MM: Hidden debug print in ISE ( XIL_PROJNAV_FLOW_DEBUG_LEVEL)
138869: 09/03/12: Walter Banks: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138871: 09/03/12: -jg: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138874: 09/03/12: Jacko: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138875: 09/03/12: StYm: libxdh_PartAnno.dll
    138961: 09/03/17: =?ISO-8859-1?Q?Jaime_Andr=E9s_Aranguren_Cardona?=: Re: libxdh_PartAnno.dll
138876: 09/03/13: Antti: DMCA and Google Groups
    138892: 09/03/13: Kolja: Re: DMCA and Google Groups
        138907: 09/03/14: Symon: OT Re: DMCA and Google Groups
    138908: 09/03/14: Antti.Lukats@googlemail.com: Re: OT Re: DMCA and Google Groups
138880: 09/03/13: Antti.Lukats@googlemail.com: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138881: 09/03/13: Herbert Kleebauer: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138883: 09/03/13: Jacko: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138884: 09/03/13: Jacko: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138885: 09/03/13: Walter Banks: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138889: 09/03/13: Herbert Kleebauer: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138890: 09/03/13: Antti.Lukats@googlemail.com: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138893: 09/03/13: Walter Banks: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138897: 09/03/13: Mad I.D.: XST: Unconnected output pins
    138898: 09/03/13: <newman5382@yahoo.com>: Re: XST: Unconnected output pins
    138899: 09/03/13: <newman5382@yahoo.com>: Re: XST: Unconnected output pins
138900: 09/03/13: rickman: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138901: 09/03/13: rickman: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138904: 09/03/14: Antti.Lukats@googlemail.com: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138909: 09/03/14: maxascent: Virtex 5 LVDS
    138911: 09/03/14: Andrew Holme: Re: Virtex 5 LVDS
        138922: 09/03/14: maxascent: Re: Virtex 5 LVDS
            138932: 09/03/15: maxascent: Re: Virtex 5 LVDS
                138933: 09/03/15: Nico Coesel: Re: Virtex 5 LVDS
                    138935: 09/03/15: maxascent: Re: Virtex 5 LVDS
                        138938: 09/03/15: Nico Coesel: Re: Virtex 5 LVDS
        138923: 09/03/14: Nathan Bialke: Re: Virtex 5 LVDS
        138937: 09/03/15: Antti.Lukats@googlemail.com: Re: Virtex 5 LVDS
138910: 09/03/14: Herbert Kleebauer: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138912: 09/03/14: Jacko: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138913: 09/03/14: Antti.Lukats@googlemail.com: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138914: 09/03/14: aleksa: Spartan 2: unused GCLK pins
138915: 09/03/14: Jacko: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138916: 09/03/14: <'use_real_email'>: Digital division scale
    138917: 09/03/14: <'use_real_email'>: Re: Digital division scale
        138926: 09/03/14: Jonathan Bromley: Re: Digital division scale
138918: 09/03/14: rickman: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138919: 09/03/14: rickman: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138920: 09/03/14: Antti.Lukats@googlemail.com: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138921: 09/03/14: Samuel Thomas Kerr: Getting started with FPGA
    138929: 09/03/14: rickman: Re: Getting started with FPGA
    138931: 09/03/15: -jg: Re: Getting started with FPGA
    138941: 09/03/15: Jeff Cunningham: Re: Getting started with FPGA
    138946: 09/03/16: John Adair: Re: Getting started with FPGA
    138948: 09/03/16: Antti.Lukats@googlemail.com: Re: Getting started with FPGA
    138951: 09/03/16: John Adair: Re: Getting started with FPGA
138924: 09/03/14: Walter Banks: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138925: 09/03/14: Jacko: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138927: 09/03/15: Herbert Kleebauer: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138928: 09/03/14: rickman: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138930: 09/03/14: Antti.Lukats@googlemail.com: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138934: 09/03/15: denish: inout pins use in fpga
    138942: 09/03/15: glen herrmannsfeldt: Re: inout pins use in fpga
    138950: 09/03/16: Rob Gaddi: Re: inout pins use in fpga
138936: 09/03/15: rickman: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138940: 09/03/15: rickman: Well Known? Phase Accumulator Trick
    138943: 09/03/16: Jonathan Bromley: Re: Well Known? Phase Accumulator Trick
138947: 09/03/16: Vesh: SPI controller for FPGA
    138953: 09/03/16: Nicolas Matringe: Re: SPI controller for FPGA
    138954: 09/03/16: Nico Coesel: Re: SPI controller for FPGA
    138955: 09/03/16: Kolja: Re: SPI controller for FPGA
138956: 09/03/16: rickman: Zero operand CPUs
    138957: 09/03/16: Muzaffer Kal: Re: Zero operand CPUs
    138962: 09/03/17: Jonathan Bromley: Re: Zero operand CPUs
        138963: 09/03/17: Hal Murray: Re: Zero operand CPUs
            138964: 09/03/17: Jonathan Bromley: Re: Zero operand CPUs
                138981: 09/03/17: Hal Murray: Re: Zero operand CPUs
                    139034: 09/03/18: Eric Smith: Re: Zero operand CPUs
                138995: 09/03/18: Jonathan Bromley: Re: Zero operand CPUs
                138996: 09/03/18: Albert van der Horst: Re: Zero operand CPUs
                    138999: 09/03/18: Andrew Haley: Re: Zero operand CPUs
                        139052: 09/03/19: Albert van der Horst: Re: Zero operand CPUs
            138968: 09/03/17: glen herrmannsfeldt: Re: Zero operand CPUs
    138969: 09/03/17: Jacko: Re: Zero operand CPUs
        138972: 09/03/17: David Brown: Re: Zero operand CPUs
            138974: 09/03/17: Rich Webb: Re: Zero operand CPUs
            139030: 09/03/19: Steve at fivetrees: Re: Zero operand CPUs
            139035: 09/03/19: Chris Burrows: Re: Zero operand CPUs - debugging
        138975: 09/03/17: Jonathan Bromley: Re: Zero operand CPUs
            138978: 09/03/17: Hal Murray: Re: Zero operand CPUs
                138994: 09/03/18: Petter Gustad: Re: Zero operand CPUs
            138983: 09/03/17: Elizabeth D Rather: Re: Zero operand CPUs
            139002: 09/03/18: Paul Urbanus: Re: Zero operand CPUs
        138980: 09/03/17: Hal Murray: Re: Zero operand CPUs
            138993: 09/03/18: Paul Urbanus: Re: Zero operand CPUs
        138988: 09/03/17: Bit Farmer: Re: Zero operand CPUs
    138970: 09/03/17: Antti.Lukats@googlemail.com: Re: Zero operand CPUs
        138997: 09/03/18: Albert van der Horst: Re: Zero operand CPUs
    138971: 09/03/17: rickman: Re: Zero operand CPUs
    138973: 09/03/17: Antti.Lukats@googlemail.com: Re: Zero operand CPUs
    138976: 09/03/17: Antti.Lukats@googlemail.com: Re: Zero operand CPUs
    138977: 09/03/17: Jeff Fox: Re: Zero operand CPUs
    138979: 09/03/17: Antti.Lukats@googlemail.com: Re: Zero operand CPUs
    138982: 09/03/17: Goran_Bilski: Re: Zero operand CPUs
    138984: 09/03/17: Jacko: Re: Zero operand CPUs
    138986: 09/03/17: Jacko: Re: Zero operand CPUs
    138989: 09/03/17: -jg: Re: Zero operand CPUs
    138990: 09/03/17: rickman: Re: Zero operand CPUs
    138998: 09/03/18: Antti.Lukats@googlemail.com: Re: Zero operand CPUs
    139001: 09/03/18: Jacko: Re: Zero operand CPUs
    139003: 09/03/18: Antti.Lukats@googlemail.com: Re: Zero operand CPUs
    139004: 09/03/18: Helmar: Bullshit! - Re: Zero operand CPUs
        139028: 09/03/18: Dombo: Re: Bullshit! - Re: Zero operand CPUs
            139031: 09/03/19: Steve at fivetrees: Re: Bullshit! - Re: Zero operand CPUs
        139046: 09/03/19: Hal Murray: Re: Bullshit! - Re: Zero operand CPUs
    139005: 09/03/18: Antti.Lukats@googlemail.com: Re: Zero operand CPUs
    139009: 09/03/18: Jacko: Re: Zero operand CPUs
    139010: 09/03/18: Jeff Fox: Re: Bullshit! - Re: Zero operand CPUs
    139012: 09/03/18: Antti.Lukats@googlemail.com: Re: Zero operand CPUs
    139013: 09/03/18: Helmar: Re: Bullshit! - Re: Zero operand CPUs
    139014: 09/03/18: Antti.Lukats@googlemail.com: Re: Bullshit! - Re: Zero operand CPUs
    139015: 09/03/18: <zwsdotcom@gmail.com>: Re: Bullshit! - Re: Zero operand CPUs
    139016: 09/03/18: rickman: Re: Zero operand CPUs
    139017: 09/03/18: Helmar: Re: Bullshit! - Re: Zero operand CPUs
    139019: 09/03/18: rickman: Re: Bullshit! - Re: Zero operand CPUs
    139021: 09/03/18: Helmar: Re: Bullshit! - Re: Zero operand CPUs
    139022: 09/03/18: Jacko: Re: Zero operand CPUs
    139023: 09/03/18: Helmar: Re: Bullshit! - Re: Zero operand CPUs
    139024: 09/03/18: Antti.Lukats@googlemail.com: Re: Zero operand CPUs
    139025: 09/03/18: Helmar: Re: Zero operand CPUs
    139026: 09/03/18: Antti.Lukats@googlemail.com: Re: Zero operand CPUs
    139027: 09/03/18: Herbert Kleebauer: Re: Bullshit! - Re: Zero operand CPUs
    139032: 09/03/18: rickman: Re: Zero operand CPUs
    139033: 09/03/18: rickman: Re: Bullshit! - Re: Zero operand CPUs
    139037: 09/03/18: Jeff Fox: Re: Bullshit! - Re: Zero operand CPUs
    139038: 09/03/18: Jeff Fox: Re: Bullshit! - Re: Zero operand CPUs
    139042: 09/03/19: rickman: Re: Bullshit! - Re: Zero operand CPUs
    139057: 09/03/19: Jacko: Re: Zero operand CPUs
    139059: 09/03/19: Antti.Lukats@googlemail.com: Re: Zero operand CPUs
    139061: 09/03/19: rickman: Re: Bullshit! - Re: Zero operand CPUs
    139062: 09/03/19: rickman: Re: Zero operand CPUs
    139063: 09/03/19: Jacko: Re: Zero operand CPUs
    139064: 09/03/19: rickman: Re: Zero operand CPUs
    139065: 09/03/19: Antti.Lukats@googlemail.com: Re: Zero operand CPUs
    139067: 09/03/19: Jacko: Re: Zero operand CPUs
    139074: 09/03/19: Jacko: Re: Zero operand CPUs
        139078: 09/03/20: Albert van der Horst: Re: Zero operand CPUs
        139104: 09/03/20: <AliBama@gmail.com>: Re Zero operand CPUs
            139171: 09/03/22: Elizabeth D Rather: Re: Re Zero operand CPUs
        139106: 09/03/20: Jacko: Re: Re Zero operand CPUs
        139109: 09/03/20: rickman: Re: Re Zero operand CPUs
        139111: 09/03/20: Jacko: Re: Re Zero operand CPUs
        139117: 09/03/21: rickman: Re: Re Zero operand CPUs
        139128: 09/03/21: Jacko: Re: Re Zero operand CPUs
        139133: 09/03/21: rickman: Re: Re Zero operand CPUs
        139159: 09/03/22: Jacko: Re: Re Zero operand CPUs
        139172: 09/03/22: rickman: Re: Re Zero operand CPUs
        139173: 09/03/22: rickman: Re: Re Zero operand CPUs
        139179: 09/03/22: Jacko: Re: Re Zero operand CPUs
    139079: 09/03/19: rickman: Re: Zero operand CPUs
    139101: 09/03/20: Jacko: Re: Zero operand CPUs
138965: 09/03/17: mopra: How to load an image onto system ace compact flash embedded on virtex
    138966: 09/03/17: Antti.Lukats@googlemail.com: Re: How to load an image onto system ace compact flash embedded on
    138967: 09/03/17: mopra: Re: How to load an image onto system ace compact flash embedded on
    138987: 09/03/17: <newman5382@yahoo.com>: Re: How to load an image onto system ace compact flash embedded on
    139055: 09/03/19: Dirk Koch: Re: How to load an image onto system ace compact flash embedded on
138985: 09/03/17: <reganireland@gmail.com>: uB and external CPU communications
    138992: 09/03/18: wolahr: Re: uB and external CPU communications
    139000: 09/03/18: Koorndyk: Re: uB and external CPU communications
138991: 09/03/18: randy: PLL inclk error
139006: 09/03/18: Jonathan Bromley: Documenting a simple CPU
    139007: 09/03/18: Antti.Lukats@googlemail.com: Re: Documenting a simple CPU
    139020: 09/03/18: <jon@beniston.com>: Re: Documenting a simple CPU
    139044: 09/03/19: rickman: Re: Documenting a simple CPU
        139048: 09/03/19: Jonathan Bromley: Re: Documenting a simple CPU
            139053: 09/03/19: Symon: Re: Documenting a simple CPU
        139071: 09/03/19: Jecel: Re: Documenting a simple CPU
        139075: 09/03/19: -jg: Re: Documenting a simple CPU
    139045: 09/03/19: -jg: Re: Documenting a simple CPU
        139047: 09/03/19: Jonathan Bromley: Re: Documenting a simple CPU
            139050: 09/03/19: Jonathan Bromley: Re: Documenting a simple CPU
            139066: 09/03/19: Jonathan Bromley: Re: Documenting a simple CPU
        139049: 09/03/19: -jg: Re: Documenting a simple CPU
        139060: 09/03/19: rickman: Re: Documenting a simple CPU
        139076: 09/03/19: -jg: Re: Documenting a simple CPU
        139080: 09/03/19: rickman: Re: Documenting a simple CPU
        139083: 09/03/20: Goran_Bilski: Re: Documenting a simple CPU
        139085: 09/03/20: Antti.Lukats@googlemail.com: Re: Documenting a simple CPU
        139087: 09/03/20: Goran_Bilski: Re: Documenting a simple CPU
        139092: 09/03/20: rickman: Re: Documenting a simple CPU
139008: 09/03/18: axr0284: false path assignment for clock boundary crossing.
    139011: 09/03/18: KJ: Re: false path assignment for clock boundary crossing.
139018: 09/03/18: Weng Tianxiang: Xilinx XAPP052 LFSR and its understanding
    139029: 09/03/18: glen herrmannsfeldt: Re: Xilinx XAPP052 LFSR and its understanding
    139036: 09/03/18: Peter Alfke: Re: Xilinx XAPP052 LFSR and its understanding
        139040: 09/03/19: Hal Murray: Re: Xilinx XAPP052 LFSR and its understanding
        139043: 09/03/19: glen herrmannsfeldt: Re: Xilinx XAPP052 LFSR and its understanding
            139070: 09/03/19: glen herrmannsfeldt: Re: Xilinx XAPP052 LFSR and its understanding
            139072: 09/03/19: glen herrmannsfeldt: Re: Xilinx XAPP052 LFSR and its understanding
        139077: 09/03/19: KJ: Re: Xilinx XAPP052 LFSR and its understanding
        139266: 09/03/24: Nico Coesel: Re: Xilinx XAPP052 LFSR and its understanding
    139039: 09/03/18: Weng Tianxiang: Re: Xilinx XAPP052 LFSR and its understanding
    139056: 09/03/19: gabor: Re: Xilinx XAPP052 LFSR and its understanding
    139068: 09/03/19: Weng Tianxiang: Re: Xilinx XAPP052 LFSR and its understanding
    139069: 09/03/19: Weng Tianxiang: Re: Xilinx XAPP052 LFSR and its understanding
    139073: 09/03/19: Weng Tianxiang: Re: Xilinx XAPP052 LFSR and its understanding
    139081: 09/03/19: Weng Tianxiang: Re: Xilinx XAPP052 LFSR and its understanding
    139137: 09/03/21: Prevailing over Technology: Re: Xilinx XAPP052 LFSR and its understanding
    139141: 09/03/21: Peter Alfke: Re: Xilinx XAPP052 LFSR and its understanding
        139162: 09/03/22: kadhiem_ayob: Re: Xilinx XAPP052 LFSR and its understanding
            139166: 09/03/22: kadhiem_ayob: Re: Xilinx XAPP052 LFSR and its understanding
                139180: 09/03/22: kadhiem_ayob: Re: Xilinx XAPP052 LFSR and its understanding
                    139192: 09/03/23: kadhiem_ayob: Re: Xilinx XAPP052 LFSR and its understanding
                        139240: 09/03/24: glen herrmannsfeldt: Re: Xilinx XAPP052 LFSR and its understanding
    139160: 09/03/22: Weng Tianxiang: Re: Xilinx XAPP052 LFSR and its understanding
    139164: 09/03/22: Weng Tianxiang: Re: Xilinx XAPP052 LFSR and its understanding
    139168: 09/03/22: Peter Alfke: Re: Xilinx XAPP052 LFSR and its understanding
    139169: 09/03/22: Weng Tianxiang: Re: Xilinx XAPP052 LFSR and its understanding
    139177: 09/03/22: Peter Alfke: Re: Xilinx XAPP052 LFSR and its understanding
    139191: 09/03/22: Weng Tianxiang: Re: Xilinx XAPP052 LFSR and its understanding
    139197: 09/03/23: gabor: Re: Xilinx XAPP052 LFSR and its understanding
    139198: 09/03/23: gabor: Re: Xilinx XAPP052 LFSR and its understanding
    139238: 09/03/23: Weng Tianxiang: Re: Xilinx XAPP052 LFSR and its understanding
    139245: 09/03/24: Allan Herriman: Re: Xilinx XAPP052 LFSR and its understanding
    139267: 09/03/24: Weng Tianxiang: Re: Xilinx XAPP052 LFSR and its understanding
139041: 09/03/19: JPS Nagi: Groundhog 2009 ...
139051: 09/03/19: SUMAN: camera module microblaze and sdram
    139144: 09/03/22: Antti.Lukats@googlemail.com: Re: camera module microblaze and sdram
139054: 09/03/19: Potxoka: Update code in board
139058: 09/03/19: Moazzam: Exporting AccelDSP generated Fixed Point C-Code to MicroSoft Visual
    139280: 09/03/24: Moazzam: Re: Exporting AccelDSP generated Fixed Point C-Code to MicroSoft
139084: 09/03/20: Antti: Silicon Blue Warm-Boot not working properly
    139136: 09/03/21: Prevailing over Technology: Re: Silicon Blue Warm-Boot not working properly
    139142: 09/03/22: Antti.Lukats@googlemail.com: Re: Silicon Blue Warm-Boot not working properly
    139143: 09/03/22: Antti.Lukats@googlemail.com: Re: Silicon Blue Warm-Boot not working properly
    139260: 09/03/24: Antti.Lukats@googlemail.com: Re: Silicon Blue Warm-Boot not working properly
    139446: 09/03/30: Antti.Lukats@googlemail.com: Re: Silicon Blue Warm-Boot not working properly
    139475: 09/03/31: Prevailing over Technology: Re: Silicon Blue Warm-Boot not working properly
    139491: 09/04/01: Antti.Lukats@googlemail.com: Re: Silicon Blue Warm-Boot not working properly
139086: 09/03/20: Mike Harrison: R/A FX2 connectors for S3A board - anyone have a couple spare?
    139088: 09/03/20: StoneThrower: Re: R/A FX2 connectors for S3A board - anyone have a couple spare?
        139089: 09/03/20: Mike Harrison: Re: R/A FX2 connectors for S3A board - anyone have a couple spare?
            139132: 09/03/21: Mike Harrison: Re: R/A FX2 connectors for S3A board - anyone have a couple spare?
        139120: 09/03/21: John Adair: Re: R/A FX2 connectors for S3A board - anyone have a couple spare?
    139315: 09/03/26: <ales.gorkic@gmail.com>: Re: R/A FX2 connectors for S3A board - anyone have a couple spare?
139091: 09/03/20: <VAX9000@gmail.com>: FPGA users, Please take a few seconds to report SPAM
    139093: 09/03/20: <jprovidenza@yahoo.com>: Re: FPGA users, Please take a few seconds to report SPAM
    139094: 09/03/20: gabor: Re: FPGA users, Please take a few seconds to report SPAM
    139096: 09/03/20: Antti.Lukats@googlemail.com: Re: FPGA users, Please take a few seconds to report SPAM
    139105: 09/03/20: James Harris: Re: FPGA users, Please take a few seconds to report SPAM
    139320: 09/03/26: <VAX9000@gmail.com>: Re: FPGA users, Please take a few seconds to report SPAM
    139332: 09/03/26: rickman: Re: FPGA users, Please take a few seconds to report SPAM
139095: 09/03/20: jleslie48: How big is my vhdl and am I approaching some size limitation on the
    139097: 09/03/20: Mike Treseler: Re: How big is my vhdl and am I approaching some size limitation
        139100: 09/03/20: Jonathan Bromley: Re: How big is my vhdl and am I approaching some size limitation on the chip.
            139103: 09/03/20: glen herrmannsfeldt: Re: How big is my vhdl and am I approaching some size limitation on the chip.
                139112: 09/03/21: Jonathan Bromley: Re: How big is my vhdl and am I approaching some size limitation on the chip.
                139115: 09/03/21: Brian Drummond: Re: How big is my vhdl and am I approaching some size limitation on the chip.
                    139138: 09/03/22: Brian Drummond: Re: How big is my vhdl and am I approaching some size limitation on the chip.
                        139156: 09/03/22: Brian Drummond: Re: How big is my vhdl and am I approaching some size limitation on the chip.
                        139167: 09/03/22: Hal Murray: Re: How big is my vhdl and am I approaching some size limitation on the chip.
                139174: 09/03/22: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
                139183: 09/03/22: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
            139178: 09/03/22: djj08230: Re: How big is my vhdl and am I approaching some size limitation on
                139182: 09/03/22: glen herrmannsfeldt: Re: How big is my vhdl and am I approaching some size limitation on ?the chip.
                    139186: 09/03/22: Jonathan Bromley: Re: How big is my vhdl and am I approaching some size limitation on ?the chip.
        139102: 09/03/20: Mike Treseler: Re: How big is my vhdl and am I approaching some size limitation
        139139: 09/03/21: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
        139146: 09/03/22: djj08230: Re: How big is my vhdl and am I approaching some size limitation on
        139147: 09/03/22: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
        139148: 09/03/22: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
            139184: 09/03/22: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
        139150: 09/03/22: djj08230: Re: How big is my vhdl and am I approaching some size limitation on
            139188: 09/03/22: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
        139154: 09/03/22: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
        139170: 09/03/22: djj08230: Re: How big is my vhdl and am I approaching some size limitation on
        139176: 09/03/22: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
    139098: 09/03/20: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
    139099: 09/03/20: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
        139158: 09/03/22: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
        139175: 09/03/22: John Adair: Re: How big is my vhdl and am I approaching some size limitation on
        139181: 09/03/22: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
        139185: 09/03/22: John Adair: Re: How big is my vhdl and am I approaching some size limitation on
    139107: 09/03/20: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
    139108: 09/03/20: rickman: Re: How big is my vhdl and am I approaching some size limitation on
    139110: 09/03/20: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
    139118: 09/03/21: John Adair: Re: How big is my vhdl and am I approaching some size limitation on
    139119: 09/03/21: rickman: Re: How big is my vhdl and am I approaching some size limitation on
    139121: 09/03/21: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
    139123: 09/03/21: rickman: Re: How big is my vhdl and am I approaching some size limitation on
    139125: 09/03/21: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
    139126: 09/03/21: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
    139127: 09/03/21: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
    139129: 09/03/21: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
    139134: 09/03/21: rickman: Re: How big is my vhdl and am I approaching some size limitation on
    139135: 09/03/21: rickman: Re: How big is my vhdl and am I approaching some size limitation on
    139140: 09/03/21: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
    139155: 09/03/22: rickman: Re: How big is my vhdl and am I approaching some size limitation on
    139157: 09/03/22: jleslie48: Re: How big is my vhdl and am I approaching some size limitation on
    139165: 09/03/22: John Adair: Re: How big is my vhdl and am I approaching some size limitation on
    139193: 09/03/23: Martin Thompson: Re: How big is my vhdl and am I approaching some size limitation on the chip.
    139194: 09/03/23: colin_toogood@yahoo.com: Re: How big is my vhdl and am I approaching some size limitation on
    139195: 09/03/23: Antti.Lukats@googlemail.com: Re: How big is my vhdl and am I approaching some size limitation on
    139202: 09/03/23: rickman: Re: How big is my vhdl and am I approaching some size limitation on
    139203: 09/03/23: Antti.Lukats@googlemail.com: Re: How big is my vhdl and am I approaching some size limitation on
139113: 09/03/21: Kristian Klaus: plb_emc with flash and datawidth matching
    139114: 09/03/21: Kristian Klaus: Re: plb_emc with flash and datawidth matching
        139124: 09/03/21: Antti.Lukats@googlemail.com: Re: plb_emc with flash and datawidth matching
            139130: 09/03/21: Kristian Klaus: Re: plb_emc with flash and datawidth matching
        139131: 09/03/21: Antti.Lukats@googlemail.com: Re: plb_emc with flash and datawidth matching
139116: 09/03/21: Mawafugo: DVI in FPGA
    139122: 09/03/21: Antti.Lukats@googlemail.com: Re: DVI in FPGA
    139151: 09/03/22: halong: Re: DVI in FPGA
    139153: 09/03/22: Antti.Lukats@googlemail.com: Re: DVI in FPGA
    139163: 09/03/22: David Fejes: Re: DVI in FPGA
139145: 09/03/22: Antti: Silicon Blue last datesheet correct URL
    139199: 09/03/23: Stephen Craven: Re: Silicon Blue last datesheet correct URL
        139210: 09/03/23: glen herrmannsfeldt: Re: Silicon Blue last datesheet correct URL
        139244: 09/03/24: Martin Thompson: FPGAs in automotive apps (was Re: Silicon Blue last datesheet correct URL)
            139270: 09/03/24: glen herrmannsfeldt: Re: FPGAs in automotive apps (was Re: Silicon Blue last datesheet ?correct URL)
            139289: 09/03/25: Martin Thompson: Re: FPGAs in automotive apps
                139305: 09/03/25: KJ: Re: FPGAs in automotive apps
                    139308: 09/03/25: KJ: Re: FPGAs in automotive apps
                        139319: 09/03/26: whygee: Re: FPGAs in automotive apps
                139316: 09/03/26: Martin Thompson: Re: FPGAs in automotive apps
                    139342: 09/03/27: Martin Thompson: Re: FPGAs in automotive apps
    139201: 09/03/23: Antti.Lukats@googlemail.com: Re: Silicon Blue last datesheet correct URL
    139205: 09/03/23: rickman: Re: Silicon Blue last datesheet correct URL
        139239: 09/03/24: Hal Murray: Re: Silicon Blue last datesheet correct URL
            139241: 09/03/24: glen herrmannsfeldt: Re: Silicon Blue last datesheet correct URL
                139248: 09/03/24: glen herrmannsfeldt: Re: Silicon Blue last datesheet correct URL
    139206: 09/03/23: rickman: Re: Silicon Blue last datesheet correct URL
    139207: 09/03/23: Antti.Lukats@googlemail.com: Re: Silicon Blue last datesheet correct URL
    139219: 09/03/23: -jg: Re: Silicon Blue last datesheet correct URL
    139220: 09/03/23: -jg: Re: Silicon Blue last datesheet correct URL
    139221: 09/03/23: Antti.Lukats@googlemail.com: Re: Silicon Blue last datesheet correct URL
    139222: 09/03/23: rickman: Re: Silicon Blue last datesheet correct URL
    139223: 09/03/23: rickman: Re: Silicon Blue last datesheet correct URL
    139226: 09/03/23: -jg: Re: Silicon Blue last datesheet correct URL
    139227: 09/03/23: -jg: Re: Silicon Blue last datesheet correct URL
    139228: 09/03/23: -jg: Re: Silicon Blue last datesheet correct URL
    139229: 09/03/23: rickman: Re: Silicon Blue last datesheet correct URL
    139231: 09/03/23: rickman: Re: Silicon Blue last datesheet correct URL
    139232: 09/03/23: rickman: Re: Silicon Blue last datesheet correct URL
    139242: 09/03/24: rickman: Re: Silicon Blue last datesheet correct URL
    139247: 09/03/24: -jg: Re: Silicon Blue last datesheet correct URL
    139252: 09/03/24: rickman: Re: Silicon Blue last datesheet correct URL
    139255: 09/03/24: rickman: Re: FPGAs in automotive apps (was Re: Silicon Blue last datesheet
    139258: 09/03/24: rickman: Re: Silicon Blue last datesheet correct URL
    139261: 09/03/24: Prevailing over Technology: Re: Silicon Blue last datesheet correct URL
    139263: 09/03/24: Prevailing over Technology: Re: Silicon Blue last datesheet correct URL
    139264: 09/03/24: Antti.Lukats@googlemail.com: Re: Silicon Blue last datesheet correct URL
    139269: 09/03/24: -jg: Re: FPGAs in automotive apps (was Re: Silicon Blue last datesheet
    139275: 09/03/24: rickman: Re: Silicon Blue last datesheet correct URL
    139276: 09/03/24: rickman: Re: Silicon Blue last datesheet correct URL
    139277: 09/03/24: Antti.Lukats@googlemail.com: Re: Silicon Blue last datesheet correct URL
    139282: 09/03/25: rickman: Re: Silicon Blue last datesheet correct URL
    139291: 09/03/25: rickman: Re: FPGAs in automotive apps
    139307: 09/03/25: rickman: Re: FPGAs in automotive apps
    139310: 09/03/25: rickman: Re: FPGAs in automotive apps
    139330: 09/03/26: rickman: Re: FPGAs in automotive apps
    139331: 09/03/26: rickman: Re: FPGAs in automotive apps
139149: 09/03/22: Guy_FPGA: Cross talk in Altera
    139187: 09/03/22: Jonathan Bromley: Re: Cross talk in Altera
139152: 09/03/22: Andrew Holme: Spartan 3 LVDS
    139161: 09/03/22: Andrew Holme: Re: Spartan 3 LVDS
    139189: 09/03/22: BobW: Re: Spartan 3 LVDS
139190: 09/03/22: Johnson L: Looking for a low-cost development kit
    139209: 09/03/23: John Adair: Re: Looking for a low-cost development kit
        139213: 09/03/23: Johnson L: Re: Looking for a low-cost development kit
            139233: 09/03/23: Johnson L: Re: Looking for a low-cost development kit
            139301: 09/03/25: News123: Re: Looking for a low-cost development kit
        139214: 09/03/23: John Adair: Re: Looking for a low-cost development kit
        139224: 09/03/23: LittleAlex: Re: Looking for a low-cost development kit
        139340: 09/03/26: LittleAlex: Re: Looking for a low-cost development kit
    139225: 09/03/23: Chris Abele: Re: Looking for a low-cost development kit
        139235: 09/03/23: Johnson L: Re: Looking for a low-cost development kit
    139234: 09/03/23: Johnson L: Re: Looking for a low-cost development kit
    139265: 09/03/24: Johnson L: Re: Looking for a low-cost development kit
        139274: 09/03/24: mng: Re: Looking for a low-cost development kit
            139302: 09/03/25: Johnson L: Re: Looking for a low-cost development kit
    139313: 09/03/26: -jg: Re: Looking for a low-cost development kit
        139910: 09/04/18: Johnson L: Re: Looking for a low-cost development kit
139196: 09/03/24: Mark McDougall: Globals in mixed-language projects
139200: 09/03/23: Antti: Altera's free ColdFire v1 IP core anybody used it?
    139204: 09/03/23: Antti.Lukats@googlemail.com: Re: Altera's free ColdFire v1 IP core anybody used it?
    139490: 09/03/31: Antti.Lukats@googlemail.com: Re: Altera's free ColdFire v1 IP core anybody used it?
139208: 09/03/23: Bert: ERROR:Pack:1564 on Virtex 4
    139236: 09/03/24: Hal Murray: Re: ERROR:Pack:1564 on Virtex 4
    139246: 09/03/24: Bert: Re: ERROR:Pack:1564 on Virtex 4
139211: 09/03/23: mopra: Using Floating Point Unit in Virtex 2 pro
    139212: 09/03/23: glen herrmannsfeldt: Re: Using Floating Point Unit in Virtex 2 pro
139215: 09/03/23: <ed.agunos@gmail.com>: low-power, high capacity data queue design ideas
    139216: 09/03/23: Rob Gaddi: Re: low-power, high capacity data queue design ideas
        139217: 09/03/23: Symon: Re: low-power, high capacity data queue design ideas
    139218: 09/03/23: John Adair: Re: low-power, high capacity data queue design ideas
139230: 09/03/23: chakra: cutting down opb_clk cycles while read-write BRAM-DDR in FPGA
139237: 09/03/23: Goli: Using SelectIO LVDS to drive 40 inch backplane trace
    139249: 09/03/24: Nathan Bialke: Re: Using SelectIO LVDS to drive 40 inch backplane trace
    139297: 09/03/25: John Adair: Re: Using SelectIO LVDS to drive 40 inch backplane trace
139243: 09/03/24: Antti: Antti Processor
    139271: 09/03/24: -jg: Re: Antti Processor
    139279: 09/03/24: Antti.Lukats@googlemail.com: Re: Antti Processor
    139281: 09/03/25: <goouse@twinmail.de>: Re: Antti Processor
    139288: 09/03/25: Antti.Lukats@googlemail.com: Re: Antti Processor
139250: 09/03/24: Essy: Flow Control
    139256: 09/03/24: Muzaffer Kal: Re: Flow Control
    139272: 09/03/24: Mike Treseler: Re: Flow Control
139251: 09/03/24: superwolfish: flash controller
    139257: 09/03/24: gabor: Re: flash controller
139253: 09/03/24: guards: chipscope pro 9.2i can't triger immediately !
    139262: 09/03/24: Benjamin Couillard: Re: chipscope pro 9.2i can't triger immediately !
139254: 09/03/24: zhj1985: Can the complex DSP archetecture based on FPGA+DSP be replaced by FPGA
    139259: 09/03/24: Benjamin Couillard: Re: Can the complex DSP archetecture based on FPGA+DSP be replaced by
    140269: 09/05/07: <stillwaters.zhj@gmail.com>: Re: Can the complex DSP archetecture based on FPGA+DSP be replaced by
        140318: 09/05/08: glen herrmannsfeldt: Re: Can the complex DSP archetecture based on FPGA+DSP be replaced by ?FPGA
    140311: 09/05/08: Flemming@Sundance: Re: Can the complex DSP archetecture based on FPGA+DSP be replaced by
    140326: 09/05/08: -jg: Re: Can the complex DSP archetecture based on FPGA+DSP be replaced by
        140327: 09/05/08: Al Clark: Re: Can the complex DSP archetecture based on FPGA+DSP be replaced by FPGA
139268: 09/03/24: Weng Tianxiang: Xilinx ISE 10.1 Error reporting
139273: 09/03/24: Mike Harrison: Which ISE Webpack version for S3A..?
    139278: 09/03/24: Antti.Lukats@googlemail.com: Re: Which ISE Webpack version for S3A..?
        139287: 09/03/25: gabor: Re: Which ISE Webpack version for S3A..?
        139293: 09/03/25: Antti.Lukats@googlemail.com: Re: Which ISE Webpack version for S3A..?
            139296: 09/03/25: Mike Harrison: Re: Which ISE Webpack version for S3A..?
    139292: 09/03/25: Rob Gaddi: Re: Which ISE Webpack version for S3A..?
139283: 09/03/25: Heiner Litz: Transmit data with clock capable pins on Virtex5 ??
139284: 09/03/25: Antti: SiliconBlue on Wikipedia
    139469: 09/03/31: Jeremy Bennett: Re: SiliconBlue on Wikipedia
    139470: 09/03/31: Antti.Lukats@googlemail.com: Re: SiliconBlue on Wikipedia
    139471: 09/03/31: Antti.Lukats@googlemail.com: Re: SiliconBlue on Wikipedia
139294: 09/03/25: <bhavanireddy@gmail.com>: USB PHY
    139295: 09/03/25: Antti.Lukats@googlemail.com: Re: USB PHY
    139298: 09/03/25: <bhavanireddy@gmail.com>: Re: USB PHY
    139299: 09/03/25: Muzaffer Kal: Re: USB PHY
    139300: 09/03/25: Antti.Lukats@googlemail.com: Re: USB PHY
    139303: 09/03/25: leevv: Re: USB PHY
    139306: 09/03/25: Antti.Lukats@googlemail.com: Re: USB PHY
139304: 09/03/25: samece: Dynamic reconfiguration in Spartan 3
    139311: 09/03/25: Moazzam: Re: Dynamic reconfiguration in Spartan 3
    139326: 09/03/26: Jecel: Re: Dynamic reconfiguration in Spartan 3
    139337: 09/03/26: austin: Re: Dynamic reconfiguration in Spartan 3
    139344: 09/03/27: Dirk Koch: Re: Dynamic reconfiguration in Spartan 3
        139503: 09/04/01: Dirk Koch: Re: Dynamic reconfiguration in Spartan 3
    139345: 09/03/27: Antti.Lukats@googlemail.com: Re: Dynamic reconfiguration in Spartan 3
    139352: 09/03/27: austin: Re: Dynamic reconfiguration in Spartan 3
    139356: 09/03/27: Antti.Lukats@googlemail.com: Re: Dynamic reconfiguration in Spartan 3
139309: 09/03/25: <AliBama@gmail.com>: some nibz decoding ?
    139323: 09/03/26: Jacko: Re: some nibz decoding ?
139312: 09/03/25: iovanalex: Avnet FX12 module, OLED example / problem
139314: 09/03/26: Muzaffer Kal: virtex-5 lvds termination issue?
    139317: 09/03/26: Sean Durkin: Re: virtex-5 lvds termination issue?
    139318: 09/03/26: Symon: Re: virtex-5 lvds termination issue?
        139321: 09/03/26: Muzaffer Kal: Re: virtex-5 lvds termination issue?
            139324: 09/03/26: Symon: Re: virtex-5 lvds termination issue?
            139325: 09/03/26: Symon: Re: virtex-5 lvds termination issue?
    139341: 09/03/26: Brian Davis: Re: virtex-5 lvds termination issue?
139327: 09/03/26: mopra: Sysace_fread syntax probleme
    139328: 09/03/26: Alan Fitch: Re: Sysace_fread syntax probleme
139329: 09/03/26: <hassen.karray@gmail.com>: Best way to export Xilinx EDK project in ISE and how to initialize
    139343: 09/03/27: Martin Thompson: Re: Best way to export Xilinx EDK project in ISE and how to initialize Brams ?
    139346: 09/03/27: gabor: Re: Best way to export Xilinx EDK project in ISE and how to
    139364: 09/03/27: <hassen.karray@gmail.com>: Re: Best way to export Xilinx EDK project in ISE and how to
    139367: 09/03/27: Antti.Lukats@googlemail.com: Re: Best way to export Xilinx EDK project in ISE and how to
    139472: 09/03/31: <hassen.karray@gmail.com>: Re: Best way to export Xilinx EDK project in ISE and how to
139334: 09/03/26: mopra: Accessing data from flash memory
139347: 09/03/27: jfh: PLL in Actel Igloo part
    139348: 09/03/27: gabor: Re: PLL in Actel Igloo part
    139358: 09/03/27: Antti.Lukats@googlemail.com: Re: PLL in Actel Igloo part
    139360: 09/03/27: jfh: Re: PLL in Actel Igloo part
    139362: 09/03/27: rickman: Re: PLL in Actel Igloo part
    139365: 09/03/27: jfh: Re: PLL in Actel Igloo part
    139369: 09/03/27: Andrew Holme: Re: PLL in Actel Igloo part
139349: 09/03/27: Antti: best soft core(s) that have C compiler support
    139368: 09/03/27: Kolja: Re: best soft core(s) that have C compiler support
    139370: 09/03/27: Tommy Thorn: Re: best soft core(s) that have C compiler support
    139371: 09/03/27: -jg: Re: best soft core(s) that have C compiler support
    139373: 09/03/27: Antti.Lukats@googlemail.com: Re: best soft core(s) that have C compiler support
    139379: 09/03/27: Tommy Thorn: Re: best soft core(s) that have C compiler support
    139384: 09/03/27: -jg: Re: best soft core(s) that have C compiler support
    139387: 09/03/27: Antti.Lukats@googlemail.com: Re: best soft core(s) that have C compiler support
    139388: 09/03/27: -jg: Re: best soft core(s) that have C compiler support
    139389: 09/03/27: Antti.Lukats@googlemail.com: Re: best soft core(s) that have C compiler support
    139390: 09/03/28: -jg: Re: best soft core(s) that have C compiler support
    139392: 09/03/28: rickman: Re: best soft core(s) that have C compiler support
    139393: 09/03/28: rickman: Re: best soft core(s) that have C compiler support
    139396: 09/03/28: Antti.Lukats@googlemail.com: Re: best soft core(s) that have C compiler support
    139397: 09/03/28: Antti.Lukats@googlemail.com: Re: best soft core(s) that have C compiler support
    139398: 09/03/28: Antti.Lukats@googlemail.com: Re: best soft core(s) that have C compiler support
    139399: 09/03/28: Kolja: Re: best soft core(s) that have C compiler support
    139426: 09/03/29: Antti.Lukats@googlemail.com: Re: best soft core(s) that have C compiler support
    139435: 09/03/29: Tommy Thorn: Re: best soft core(s) that have C compiler support
    139436: 09/03/29: Tommy Thorn: Re: best soft core(s) that have C compiler support
    139437: 09/03/29: -jg: Re: best soft core(s) that have C compiler support
    139438: 09/03/29: Tommy Thorn: Re: best soft core(s) that have C compiler support
    139439: 09/03/29: Tommy Thorn: Re: best soft core(s) that have C compiler support
    139477: 09/03/31: Andy Peters: Re: best soft core(s) that have C compiler support
    139864: 09/04/17: Antti.Lukats@googlemail.com: Re: best soft core(s) that have C compiler support
    140119: 09/04/29: Tommy Thorn: Re: best soft core(s) that have C compiler support
    140136: 09/04/29: Antti.Lukats@googlemail.com: Re: best soft core(s) that have C compiler support
    140195: 09/05/02: rickman: Re: best soft core(s) that have C compiler support
    140196: 09/05/02: rickman: Re: best soft core(s) that have C compiler support
    140197: 09/05/02: rickman: Re: best soft core(s) that have C compiler support
    140198: 09/05/02: Antti.Lukats@googlemail.com: Re: best soft core(s) that have C compiler support
139350: 09/03/27: PGS: Using LVDS in Lattice ECP3
    139353: 09/03/27: Antti.Lukats@googlemail.com: Re: Using LVDS in Lattice ECP3
    139357: 09/03/27: gabor: Re: Using LVDS in Lattice ECP3
    139359: 09/03/27: gabor: Re: Using LVDS in Lattice ECP3
139351: 09/03/27: rickman: FIFO controlled loop, PLL, FLL or something else?
    139354: 09/03/27: John: Re: FIFO controlled loop, PLL, FLL or something else?
        139366: 09/03/27: Eric Jacobsen: Re: FIFO controlled loop, PLL, FLL or something else?
            139381: 09/03/27: Eric Jacobsen: Re: FIFO controlled loop, PLL, FLL or something else?
                139408: 09/03/28: Eric Jacobsen: Re: FIFO controlled loop, PLL, FLL or something else?
        139412: 09/03/28: rickman: Re: FIFO controlled loop, PLL, FLL or something else?
    139355: 09/03/27: Vladimir Vassilevsky: Re: FIFO controlled loop, PLL, FLL or something else?
    139361: 09/03/27: <filter001@desinformation.de>: Re: FIFO controlled loop, PLL, FLL or something else?
        139372: 09/03/27: Jon Elson: Re: FIFO controlled loop, PLL, FLL or something else?
    139363: 09/03/27: Rob Gaddi: Re: FIFO controlled loop, PLL, FLL or something else?
    139375: 09/03/27: rickman: Re: FIFO controlled loop, PLL, FLL or something else?
    139376: 09/03/27: rickman: Re: FIFO controlled loop, PLL, FLL or something else?
    139377: 09/03/27: John: Re: FIFO controlled loop, PLL, FLL or something else?
    139382: 09/03/27: Tim Wescott: Re: FIFO controlled loop, PLL, FLL or something else?
    139383: 09/03/27: Tim Wescott: Re: FIFO controlled loop, PLL, FLL or something else?
    139385: 09/03/28: Allan Herriman: Re: FIFO controlled loop, PLL, FLL or something else?
    139391: 09/03/28: rickman: Re: FIFO controlled loop, PLL, FLL or something else?
    139400: 09/03/28: Robert Adams: Re: FIFO controlled loop, PLL, FLL or something else?
    139404: 09/03/28: rickman: Re: FIFO controlled loop, PLL, FLL or something else?
139374: 09/03/27: <thomas.schatz@hotmail.fr>: Where to find a xc6200 xilinx fpga?
    139386: 09/03/27: Antti.Lukats@googlemail.com: Re: Where to find a xc6200 xilinx fpga?
    139394: 09/03/28: rickman: Re: Where to find a xc6200 xilinx fpga?
        139403: 09/03/28: ACD: Re: Where to find a xc6200 xilinx fpga?
139378: 09/03/27: Tommy Thorn: What does Xilinx mean by "Real 6-input look-up (LUT) technology"?
    139380: 09/03/28: Symon: Re: What does Xilinx mean by "Real 6-input look-up (LUT) technology"?
    139395: 09/03/28: rickman: Re: What does Xilinx mean by "Real 6-input look-up (LUT) technology"?
        139425: 09/03/29: whygee: Re: What does Xilinx mean by "Real 6-input look-up (LUT) technology"?
    139409: 09/03/28: -jg: Re: What does Xilinx mean by "Real 6-input look-up (LUT) technology"?
    139411: 09/03/28: rickman: Re: What does Xilinx mean by "Real 6-input look-up (LUT) technology"?
139401: 09/03/28: Mike Harrison: VHDL : how to make a bunch of arbitary signals into a vector?
    139405: 09/03/28: rickman: Re: VHDL : how to make a bunch of arbitary signals into a vector?
    139407: 09/03/28: Mike Treseler: Re: VHDL : how to make a bunch of arbitary signals into a vector?
139402: 09/03/28: ACD: partitions and incremental design with xilinx ISE
    139421: 09/03/29: Brian Drummond: Re: partitions and incremental design with xilinx ISE
139406: 09/03/28: nike: XST segmentation fault on top level synthesis
139413: 09/03/28: nike: Xilinx options (synthesis and map) in Synplify Pro
139419: 09/03/28: Muzaffer Kal: Re: USB port on FPGA - How is data transmitted?
    139449: 09/03/30: dts4theworld: Re: USB port on FPGA - How is data transmitted?
        139453: 09/03/30: Muzaffer Kal: Re: USB port on FPGA - How is data transmitted?
139431: 09/03/29: cpfpga: doubts regarding fpga spartan3E kit use.
139432: 09/03/29: dts4theworld: USB port on FPGA - How is data transmitted?
139442: 09/03/30: bobrics: Problems with include paths in Eclipse, Nios2, Altera
139443: 09/03/30: Bert_Paris: RS232, UART & Igloo nano Kit
139448: 09/03/30: Oliver Faust: Fiber optics protocols for mid range speed
    139450: 09/03/30: Antti.Lukats@googlemail.com: Re: Fiber optics protocols for mid range speed
    139451: 09/03/30: Oliver Faust: Re: Fiber optics protocols for mid range speed
    139454: 09/03/30: Tommy Thorn: Re: Fiber optics protocols for mid range speed
        139487: 09/04/01: Marty Ryba: Re: Fiber optics protocols for mid range speed
    139459: 09/03/30: czam: Re: Fiber optics protocols for mid range speed
    139468: 09/03/31: Oliver Faust: Re: Fiber optics protocols for mid range speed
    139473: 09/03/31: Oliver Faust: Re: Fiber optics protocols for mid range speed
    139478: 09/03/31: czam: Re: Fiber optics protocols for mid range speed
139457: 09/03/30: <mitrusc1980-newsgroup@yahoo.com.br>: Toolchain for programming Mach211SP PLD.
    139458: 09/03/30: Rainer Buchty: Re: Toolchain for programming Mach211SP PLD.
139461: 09/03/30: alonzo: initialize BRAM contents
    139462: 09/03/30: LittleAlex: Re: initialize BRAM contents
    139464: 09/03/30: alonzo: Re: initialize BRAM contents
    139465: 09/03/30: Antti.Lukats@googlemail.com: Re: initialize BRAM contents
    139474: 09/03/31: <hassen.karray@gmail.com>: Re: initialize BRAM contents
    139476: 09/03/31: Antti.Lukats@googlemail.com: Re: initialize BRAM contents
    139956: 09/04/20: alonzo: Re: initialize BRAM contents
139463: 09/03/30: Andy Ross: Programming Digilent Nexys 2 from Linux
    139485: 09/03/31: emeb: Re: Programming Digilent Nexys 2 from Linux
    139506: 09/04/01: =?ISO-8859-1?Q?Ronan_Paix=E3o?=: Re: Programming Digilent Nexys 2 from Linux
    139508: 09/04/01: Andy Ross: Re: Programming Digilent Nexys 2 from Linux
    139514: 09/04/01: John Eaton: Re: Programming Digilent Nexys 2 from Linux
        139537: 09/04/02: Uwe Bonnes: Re: Programming Digilent Nexys 2 from Linux
            139544: 09/04/02: Uwe Bonnes: Re: Programming Digilent Nexys 2 from Linux
    139515: 09/04/01: emeb: Re: Programming Digilent Nexys 2 from Linux
    139536: 09/04/02: Andy Ross: Re: Programming Digilent Nexys 2 from Linux
    139541: 09/04/02: Andy Ross: Re: Programming Digilent Nexys 2 from Linux
    139547: 09/04/02: emeb: Re: Programming Digilent Nexys 2 from Linux
    139730: 09/04/10: John Eaton: Re: Programming Digilent Nexys 2 from Linux
        139750: 09/04/11: John Eaton: Re: Programming Digilent Nexys 2 from Linux
            139765: 09/04/12: Muzaffer Kal: Re: Programming Digilent Nexys 2 from Linux
    139745: 09/04/11: Andy Ross: Re: Programming Digilent Nexys 2 from Linux
    140497: 09/05/15: jmiles@pop.net: Re: FPGA+FX2 API for Digilent Nexys 2 (was Programming... from Linux)
    140529: 09/05/15: Brian Davis: Re: FPGA+FX2 API for Digilent Nexys 2 (was Programming... from Linux)
139466: 09/03/31: palvarez: clock distribution on VITA 57 (FMC)
    139489: 09/04/01: Marty Ryba: Re: clock distribution on VITA 57 (FMC)
    139492: 09/04/01: Antti.Lukats@googlemail.com: Re: clock distribution on VITA 57 (FMC)
139467: 09/03/31: mamu: Dedicated clock routes in Xilinx FPGA
139479: 09/03/31: MM: XST removes duplicate logic no matter what
    139480: 09/03/31: gabor: Re: XST removes duplicate logic no matter what
        139483: 09/03/31: MM: Re: XST removes duplicate logic no matter what
    139481: 09/03/31: Mike Treseler: Re: XST removes duplicate logic no matter what
        139482: 09/03/31: MM: Re: XST removes duplicate logic no matter what
139486: 09/03/31: <wondering.gnome@gmail.com>: Digital design references for timing, etc.
    139498: 09/04/01: Koorndyk: Re: Digital design references for timing, etc.
    139500: 09/04/01: <wondering.gnome@gmail.com>: Re: Digital design references for timing, etc.
    139510: 09/04/01: mng: Re: Digital design references for timing, etc.
139488: 09/03/31: stephen.craven@gmail.com: Xilinx partitions vs. smartguide
    139516: 09/04/01: Mike Treseler: Re: Xilinx partitions vs. smartguide


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