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"Tommy Thorn" <tommy.thorn@gmail.com> wrote in message news:4d9cae4e-e4d8-4c62-8448-8a029071cebb@s1g2000prd.googlegroups.com... On May 6, 8:55 am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > http://members.at.infoseek.co.jp/x1resource/xilinx/ip/mr16/mr16.html As brilliant as this may be, everything is in japaneese, the pdfs can't be accessed and the project appears completely unmaintained. Still, in the interest of gauging how hard it would be to compile for, I would like to see an overview of the ISA. =============== http://translate.google.com/translate?sourceid=navclient&hl=en&u=http%3a%2f%2fmembers%2eat%2einfoseek%2eco%2ejp%2fx1resource%2fxilinx%2fip%2fmr16%2fmr16%2ehtml There's a 'Translate page' button on the Google Bar.Article: 140526
<'use_real_email'> wrote in message news:pini_1234.3s8qh5@noemail.example.com... > Have you considered LEON. > I used for some self learing projects: > Improving The LEON2-XST PCI Interface > 'VHDL, verilog, design, verification, scripts, ...' > (http://bknpk.no-ip.biz/LEON/leon_1.html) You must be color blind in a different way than I am. :D Uggh! My eyes are squirting blood, and I still couldn't read the links.Article: 140527
On May 14, 1:24=A0am, halong <cco...@netscape.net> wrote: > On May 11, 2:26=A0am, hamze60 <hamz...@gmail.com> wrote: > > > I want to design a space system and don't want to use airspace > > expensive fpga. considering space radiation I want to make this system > > fault tolerant. ACTEL is flash-based but in program lost condition > > ( even with low probability ) it should be reprogrammed so a > > programing circuit is also needed. Xilinx or Altera are RAMbased but > > they have very small size EPROMs to store both hardware configuration > > and software, so using multiple of EPROMs is possible for redundancy. > > can anybody suggest better solution or even a new idea? > > Sorry to ask, how expensive is that the airspace FPGA in comparison to > the other high end devices? we asked for ACTEL ProASIC3E-3000, its industrial part is around 400$ as I can remember but its airspace is around 40,000 $ !!!Article: 140528
The code for the SLAVE SDIO is entirely free. While the code is far from being complete a lot can be learned and benefited from using it. 1. The code is simple and it can be easily improved and maintained. 2. The code is synthesized friendly, tested on XILINX XST. 3. The code is updated from time to time. A release history, including waveform in VCD format, is available on site. 'VHDL, verilog, design, verification, scripts, ...' (http://bknpk.no-ip.biz/SDIO/sdio_1.html) -- pini_1234 ------------------------------------------------------------------------ pini_1234's Profile: http://www.fpgacentral.com/group/member.php?userid=86 View this thread: http://www.fpgacentral.com/group/showthread.php?t=90147Article: 140529
John, Not a detailed answer ( I don't have a NEXSYS2 board ), but perhaps some clues you haven't found yet, in these old posts summarizing similar JTAG vs. mode pin vs. PROM conflicts: JTAG/mode/PROM configuration problems: http://groups.google.com/group/comp.arch.fpga/msg/5b79a99163d5282e http://groups.google.com/group/comp.arch.fpga/msg/b06ca9faf716c347 Digilent Spartan3 ( original, non-E ) JTAG download issues: http://groups.google.com/group/comp.arch.fpga/msg/8b2144041295cd24 http://groups.google.com/group/comp.arch.fpga/msg/63162b2622926fa9 Random Thoughts: > > If you set JP9 to JTAG and use -StartupClk:JtagClk, the .bit upload fails, > and the DONE light never comes on. > Try doing an extra JTAG operation after config ( e.g. read the PROM ID ) Does JTAG configuration work properly when using : - Digilent's Adept suite through the USB config port ? - an external Xilinx ( USB/parallel ) JTAG cable through IMPACT ? > > 1) Regardless of the M2:M0 bits resulting from a given JP9 setting, > I'm still considered to be using "JTAG configuration" as long as I'm > sending the .bit image via the JTAG TAP state machine, correct? > As mentioned in the above links, there are longstanding (and regularly recurring ) issues involving dueling configuration modes interrupting one another and fouling up the configuration and/or FPGA startup process. Is there a spare I/O bit on the micro to force the FPGA mode pins to JTAG during a JTAG download ? > > why does -StartupClk:CClk work OK for JTAG configurations if, > and only if, M2:M0 are set for Master Serial mode (000)? > Master mode is the only one that normally generates CCLK from the FPGA; CCLK might be turning back on after the JTAG config completes, giving the FPGA the extra clocks it needs to finish startup. > > The JSTART thing bugs me because of how flaky its documentation is. > Have you searched the Answer Records for JSTART and JPROGRAM ? Xilinx search engine tips: > > - Go to the Xilinx webpage > - click the "advanced search" link (below the search button) > - enter your search terms > - check what to search ( answer records, archive, etc. ) > > Note that although the search terms are filled in again > on the results page, that is just the plain-old-search, > not the advanced one; you have to back up to the advanced > search page again to properly modify your search terms. > have fun, BrianArticle: 140530
I have a couple of Altera dev boards - a Terasic DE2, and an old Stratix "SmartPack"; and I really want to play with an Ethernet MAC core. The trouble is, the DE2 has a full-blown Ethernet controller - and the SmartPack has nothing. I'm essentially looking for a board that has MII/GMII on one side, and an RJ-45 connector on the other. These exist, but cost hundreds of dollars. (the EVB-LAN8700 would be perfect, if it wasn't nearly $300!) Does anyone know of a cheap (~$50) board that essentially does the above? 10/100 would be fine. If I can't find one, and have to roll one, would there be any interest in it?Article: 140531
I would like to share a script, which can be used as a base for a net-list conversion tool. The methodology for normal digital design is well known. Specification, block diagram of the data path, timing of the control, RTL coding, simulation, synthesis, post synthesis and post layout simulation and static timing analysis. While this is the right way of doing things, when it comes to complex digital ASIC designs, there are small number of cases where this methodology is not required. I have been asked by friend to convert a post layout verilog net-list from one vendor to another. The design runs very slow, around 10 MHz, which is very slow. The design was also small in terms of gate count. So another approach has to be considered in order to make this project profitable. .. 'VHDL, verilog, design, verification, scripts, ...' (http://bknpk.no-ip.biz/netlistConversion/netlistConversion.html) -- pini_1234 ------------------------------------------------------------------------ pini_1234's Profile: http://www.fpgacentral.com/group/member.php?userid=86 View this thread: http://www.fpgacentral.com/group/showthread.php?t=90149Article: 140532
On May 16, 7:53=A0am, 'use_real_email' wrote: > The code for the SLAVE SDIO is entirely free. While the code is far from > being complete a lot can be learned and benefited from using it. > > 1. The code is simple and it can be easily improved and maintained. > 2. The code is synthesized friendly, tested on XILINX XST. > 3. The code is updated from time to time. A release history, > including waveform in VCD format, is available on site. > > 'VHDL, verilog, design, verification, scripts, ...' > (http://bknpk.no-ip.biz/SDIO/sdio_1.html) > > -- > pini_1234 > ------------------------------------------------------------------------ > pini_1234's Profile:http://www.fpgacentral.com/group/member.php?userid=3D= 86 > View this thread:http://www.fpgacentral.com/group/showthread.php?t=3D9014= 7 you dont mention what testing do you need? AnttiArticle: 140533
On May 15, 7:39=A0pm, Tommy Thorn <tommy.th...@gmail.com> wrote: > On May 6, 8:55=A0am, "Antti.Luk...@googlemail.com" > > <Antti.Luk...@googlemail.com> wrote: > >http://members.at.infoseek.co.jp/x1resource/xilinx/ip/mr16/mr16.html > > As brilliant as this may be, everything is in japaneese, the pdfs > can't be accessed and the project appears completely unmaintained. > > Still, in the interest of gauging how hard it would be to compile for, > I would like to see an overview of the ISA. > > Tommy eh, i usually dont care if it is japanese or not, as long as there are links to downloadable hdl code the mr16 is used in one japanese RETRO project where it does some system peripheral emulation that project is maintained i think eh, i just found POC(tm) Pascal On Chip IP core it does execute the old pascal-s pseudo codes in hardware only 145 slices :) - without the console opcodes AnttiArticle: 140534
On May 16, 6:09=A0am, radarman <jsham...@gmail.com> wrote: > I have a couple of Altera dev boards - a Terasic DE2, and an old > Stratix "SmartPack"; and I really want to play with an Ethernet MAC > core. The trouble is, the DE2 has a full-blown Ethernet controller - > and the SmartPack has nothing. > > I'm essentially looking for a board that has MII/GMII on one side, and > an RJ-45 connector on the other. These exist, but cost hundreds of > dollars. (the EVB-LAN8700 would be perfect, if it wasn't nearly $300!) > Does anyone know of a cheap (~$50) board that essentially does the > above? 10/100 would be fine. > > If I can't find one, and have to roll one, would there be any interest > in it? Have you checked Xilinx EVMS? They have a starter kit that may be of your insterest : www.xilinx.com/s3estarterkit (~$150). - SebastienArticle: 140535
I would like it to be timed to 350MHz. I guess I just need a better way to transfer from the clk0 domain to the clk90 domain so that Synplify doesnt try to time it to 4 x 350MHz. JonArticle: 140536
There is a DP83848 based module in our product range that might do what you want. It will probably need physical adaption. There isn't much info on our website on this but contact our sales team for more details. Details on our website www.enterpoint.co.uk. Price on this module approximately $40 + carraige and we do appear to have stock. John Adair Enterpoint Ltd. On 16 May, 06:09, radarman <jsham...@gmail.com> wrote: > I have a couple of Altera dev boards - a Terasic DE2, and an old > Stratix "SmartPack"; and I really want to play with an Ethernet MAC > core. The trouble is, the DE2 has a full-blown Ethernet controller - > and the SmartPack has nothing. > > I'm essentially looking for a board that has MII/GMII on one side, and > an RJ-45 connector on the other. These exist, but cost hundreds of > dollars. (the EVB-LAN8700 would be perfect, if it wasn't nearly $300!) > Does anyone know of a cheap (~$50) board that essentially does the > above? 10/100 would be fine. > > If I can't find one, and have to roll one, would there be any interest > in it?Article: 140537
radarman <jshamlet@gmail.com> wrote: (snip) > I'm essentially looking for a board that has MII/GMII on one side, and > an RJ-45 connector on the other. These exist, but cost hundreds of > dollars. (the EVB-LAN8700 would be perfect, if it wasn't nearly $300!) > Does anyone know of a cheap (~$50) board that essentially does the > above? 10/100 would be fine. The Spartan3E board has built in 10/100 PHY, supply your own MAC. That is $150, so more than $50, less than $300. -- glenArticle: 140538
On 15 mei, 22:48, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > "MikeWhy" <boat042-nos...@yahoo.com> wrote in message > > news:NqkPl.26630$c45.6895@nlpi065.nbdc.sbc.com... > > > > > "gert1999" <ggd...@gmail.com> wrote in message > >news:88ff57c2-b9e8-4a34-8e56-6a7afd698641@e20g2000vbc.googlegroups.com..= . > >> Hi all, > > >> I have a problem with Coolrunner II pld (http://www.xilinx.com/ > >> products/devkits/SK-CRII-L-G.htm). > >> I have written a program similar to the project counter given in the > >> Xilinx handbook example. > >> Full code is available onhttp://webs.hogent.be/~a00027gd/teller.txt > >> In ISE the code compiles correctly except for one warning message. > >> The handbook example gives the same error message so this cannot be > >> the problem. =A0I used PACE to assign pins and created the .jed-file a= s > >> usual > > > I didn't look in any detail. How does it look in simulation? Is it > > counting? If it is, check the UCF for pin assignments, pull-up/-down > > attributes. Look especially at the reset line. If it doesn't count in > > simulation, check the reset sense, 1 or 0. Check the clock. ... ... ... > > [PS] Check the digit select, common cathode or anode on the 7-segment. Is= it > driven correctly? I didn't see that in the ports. Hello Thanks for helping: you gave some usefull tips, however the board is still dead :-( I've added some files on the same link First you got the reset line correct: it should be driven low instead of high (if reset=3D'0') Second I added the common driving kathode pins. In the manual they indicate they should all be driven low if not multiplexing. I've done so, this could also be derived from the schematic as the are pnp transistors. However I can't find any code in the handbook example: how do they drive them low if there is no code written ? Setting attributes might be the key ?? . A new version of the source is the file teller_update1.txt I placed screenshots of pinmapping, low level simulation of the counter, and top level simulation of the whole design As one can see: the counter counts, but the LEDs are not being driven ?? They just stay low resulting in a dead board What exactly do you mean by pull down atributes ? I only specified clock_ext DATA_GATE as they did so in the manual Hope we can bring the board to life ... Thanks GertArticle: 140539
Hi, I need to use the standard BSCAN_SPARTAN3 or BSCAN_VIRTEX4 component to access user logic in an embedded system, which hopefully is able to run the libusb-driver, but will not run the Xilinx libraries used e.g. by the standard tcljtag.tcl script. Additionally the access is needed from thy Python language, not from the Tcl. Has anybody succeeded to access the BSCAN_xxxx components from the raw JTAG library (libusb-driver, or OpenOCD, or openwince), which in turn may be used by the Python software? -- TIA & Regards, WojtekArticle: 140540
On May 16, 5:32=A0pm, wzab <w...@ise.pw.edu.pl> wrote: > Hi, > > I need to use the standard BSCAN_SPARTAN3 or BSCAN_VIRTEX4 component > to access user logic in an embedded system, which hopefully is able > to run the libusb-driver, but will not run the Xilinx libraries used > e.g. by the standard tcljtag.tcl script. > > Additionally the access is needed from thy Python language, not from the > Tcl. > > Has anybody succeeded to access the BSCAN_xxxx components from the raw > JTAG library (libusb-driver, or OpenOCD, or openwince), which in turn > may be used by the Python software? > -- > TIA & Regards, > Wojtek sure we use in our own software all the time but you can not use xilinx usb cables, as the protocol is not public AnttiArticle: 140541
Dnia 16.05.2009 Antti.Lukats@googlemail.com <Antti.Lukats@googlemail.com> wrote: > > sure we use in our own software all the time > > but you can not use xilinx usb cables, as the protocol is not public > I may be wrong, but it seems to me, that the libusb-driver allows to access the Xilinx cable as well. Certainly I need to make some experiments, but it seems, that the libusb-driver allows to access also the Xilinx cable... And the DEBUG version option allows to trace the protocol fully, so I don't think it is a big problem. I know it can be done, but I'd like to know if anybody has already done it and may/want to share the results... -- Thanks, WojtekArticle: 140542
On May 16, 6:32=A0pm, wzab <w...@wzab.nasz.dom> wrote: > Dnia 16.05.2009 Antti.Luk...@googlemail.com <Antti.Luk...@googlemail.com> > wrote: > > > sure we use in our own software all the time > > > but you can not use xilinx usb cables, as the protocol is not public > > I may be wrong, but it seems to me, that the libusb-driver allows to acce= ss > the Xilinx cable as well. > Certainly I need to make some experiments, but it seems, that the > libusb-driver allows to access also the Xilinx cable... > > And the DEBUG version option allows to trace the protocol fully, so I don= 't > think it is a big problem. > > I know it can be done, but I'd like to know if anybody has already done i= t > and may/want to share the results... > -- > Thanks, > Wojtek well you CAN of connect to xilinx usb cable, but you need to RE the protocol AnttiArticle: 140543
"gert1999" <ggddbb@gmail.com> wrote in message news:95580829-2b4b-4981-acb5-9489958899bd@v4g2000vba.googlegroups.com... I've added some files on the same link First you got the reset line correct: it should be driven low instead of high (if reset='0') Second I added the common driving kathode pins. In the manual they indicate they should all be driven low if not multiplexing. I've done so, this could also be derived from the schematic as the are pnp transistors. However I can't find any code in the handbook example: how do they drive them low if there is no code written ? Setting attributes might be the key ?? . A new version of the source is the file teller_update1.txt I placed screenshots of pinmapping, low level simulation of the counter, and top level simulation of the whole design As one can see: the counter counts, but the LEDs are not being driven ?? They just stay low resulting in a dead board What exactly do you mean by pull down atributes ? I only specified clock_ext DATA_GATE as they did so in the manual ======== You're now looking in the right places, and asking the right questions. The next step is to answer them yourself. ;) Pullup and pulldown apply more to reading switches; don't let me confuse you with my confusion. Data-gate is related to power save modes. Try disabling it removing the attribute, or make sure its driven correctly. Try driving a constant '0' on the common cathode. Failing that, physically tie it to ground on the board. Try probing with a meter and look for voltages you would expect. The LED pins should read somewhat less than half the high state voltage. Check that the display cathode is grounded, not just floating. Check that the data-gate pin reads whatever means not power save. Good luck.Article: 140544
On May 16, 7:53=A0am, 'use_real_email' wrote: > The code for the SLAVE SDIO is entirely free. While the code is far from > being complete a lot can be learned and benefited from using it. > > 1. The code is simple and it can be easily improved and maintained. > 2. The code is synthesized friendly, tested on XILINX XST. > 3. The code is updated from time to time. A release history, > including waveform in VCD format, is available on site. > > 'VHDL, verilog, design, verification, scripts, ...' > (http://bknpk.no-ip.biz/SDIO/sdio_1.html) > > -- > pini_1234 > ------------------------------------------------------------------------ > pini_1234's Profile:http://www.fpgacentral.com/group/member.php?userid=3D= 86 > View this thread:http://www.fpgacentral.com/group/showthread.php?t=3D9014= 7 test report: ERROR:HDLCompilers:26 - "../hdl/sd_slv_reg.v" line 8 Could not find verilog include file 'sd_slv_CSD_constants.v' Analysis of file <"sd_slv_top.prj"> failed. --> some files are missing from your tarball :( AnttiArticle: 140545
I would like someone to test it on an FPGA device. I'll put a new tarball. Any how you can mail me what files are missing. -- pini_1234 ------------------------------------------------------------------------ pini_1234's Profile: http://www.fpgacentral.com/group/member.php?userid=86 View this thread: http://www.fpgacentral.com/group/showthread.php?t=90147Article: 140546
On 16 mei, 19:08, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > "gert1999" <ggd...@gmail.com> wrote in message > > news:95580829-2b4b-4981-acb5-9489958899bd@v4g2000vba.googlegroups.com... > I've added some files on the same link > First you got the reset line correct: it should be driven low instead > of high (if reset=3D'0') > Second I added the common driving kathode pins. =A0 In the manual they > indicate they should all be driven low if not multiplexing. =A0I've done > so, this could also be derived from the schematic as the are pnp > transistors. =A0However I can't find any code in the handbook example: > how do they drive them low if there is no code written ? =A0Setting > attributes might be the key ?? > . > A new version of the source is the file teller_update1.txt > I placed screenshots of pinmapping, low level simulation of the > counter, and top level simulation of the whole design > > As one can see: the counter counts, but the LEDs are not being > driven ?? They just stay low resulting in a dead board > What exactly do you mean by pull down atributes ? =A0I only specified > clock_ext DATA_GATE as they did so in the manual > > =3D=3D=3D=3D=3D=3D=3D=3D > You're now looking in the right places, and asking the right questions. T= he > next step is to answer them yourself. ;) > > Pullup and pulldown apply more to reading switches; don't let me confuse = you > with my confusion. Data-gate is related to power save modes. Try disablin= g > it removing the attribute, or make sure its driven correctly. Try driving= a > constant '0' on the common cathode. Failing that, physically tie it to > ground on the board. Try probing with a meter and look for voltages you > would expect. The LED pins should read somewhat less than half the high > state voltage. Check that the display cathode is grounded, not just > floating. Check that the data-gate pin reads whatever means not power sav= e. > > Good luck. =3D=3D=3D=3D Thank's a lot for helping. I know about pullup and pulldown in simpel logic (active / passive pull up and that kind of things) I have been trying to answer the questions for several days and decided to ask help :-) I'll see what to do with it There are so many questions and Xilinx manuals are not very helpfull (they make it look so simple .. ) If it ever works I wil leave a mesage here (if the article will still be avaiilable in the newsgroup :-) ) Thanks again GertArticle: 140547
"gert1999" <ggddbb@gmail.com> wrote in message news:af6b611f-0775-41ad-a664-ab6605364e88@o14g2000vbo.googlegroups.com... On 16 mei, 19:08, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > "gert1999" <ggd...@gmail.com> wrote in message > > news:95580829-2b4b-4981-acb5-9489958899bd@v4g2000vba.googlegroups.com... > I've added some files on the same link > First you got the reset line correct: it should be driven low instead > of high (if reset='0') > Second I added the common driving kathode pins. In the manual they > indicate they should all be driven low if not multiplexing. I've done > so, this could also be derived from the schematic as the are pnp > transistors. However I can't find any code in the handbook example: > how do they drive them low if there is no code written ? Setting > attributes might be the key ?? > . > A new version of the source is the file teller_update1.txt > I placed screenshots of pinmapping, low level simulation of the > counter, and top level simulation of the whole design > > As one can see: the counter counts, but the LEDs are not being > driven ?? They just stay low resulting in a dead board > What exactly do you mean by pull down atributes ? I only specified > clock_ext DATA_GATE as they did so in the manual > > ======== > You're now looking in the right places, and asking the right questions. > The > next step is to answer them yourself. ;) > > Pullup and pulldown apply more to reading switches; don't let me confuse > you > with my confusion. Data-gate is related to power save modes. Try disabling > it removing the attribute, or make sure its driven correctly. Try driving > a > constant '0' on the common cathode. Failing that, physically tie it to > ground on the board. Try probing with a meter and look for voltages you > would expect. The LED pins should read somewhat less than half the high > state voltage. Check that the display cathode is grounded, not just > floating. Check that the data-gate pin reads whatever means not power > save. > > Good luck. ==== Thank's a lot for helping. I know about pullup and pulldown in simpel logic (active / passive pull up and that kind of things) I have been trying to answer the questions for several days and decided to ask help :-) I'll see what to do with it There are so many questions and Xilinx manuals are not very helpfull (they make it look so simple .. ) If it ever works I wil leave a mesage here (if the article will still be avaiilable in the newsgroup :-) ) ======= Double check that reset pin. The testbench likely just needed a simple stimulus to take it out of reset, something like rst <= '0', while the code was actually fine. Read the schematic and be sure you have the right pullup/down sense on that pin. Same with data-gate. Probe the logic levels with a meter. If you have an I/O header available, route the signals to the header to make probing easier and somewhat safer. It is a lot to swallow all at once, but it sounds like you have a fair grasp of the tools. At this point, it's less a matter of the Xilinx docs than it is assumptions about the board. Take out the reset at the top level and set it to constant '1' in your code. Check the pin locations in the ucf. Take out the data-gate until you have it working. I didn't see an led_enable pin at the top level entity. Check the schematic and see that it is wired to ground rather than a pin.Article: 140548
On Sat, 16 May 2009 04:02:54 -0500, "maxascent" <maxascent@yahoo.co.uk> wrote: >I would like it to be timed to 350MHz. I guess I just need a better way to >transfer from the clk0 domain to the clk90 domain so that Synplify doesnt >try to time it to 4 x 350MHz. It is not just Synplify which times it at 4x350 MHz, it's real life. There is really only <715 ps of time between clk0 and clk90 edges and if you have one register with clk0 and one register with clk90 connected to their clock pins respectively, 715ps is the time you have; there is no way getting around it. Nevertheless, if you're just copying from clk0 to clk90, the time you need is only clk to output delay of one flop and with minimal routing you should be able to meeting timing; you just can't put any logic between those two flops. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 140549
On May 16, 6:47=A0pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > eh, i just found POC(tm) Pascal On Chip IP core > > it does execute the old pascal-s pseudo codes in hardware > only 145 slices :) - without the console opcodes Any links for that POC ? Is it a HW version of this ? http://en.wikipedia.org/wiki/P-code_machine#Example_machine or can it run this ? http://www.moorecad.com/standardpascal/pascals.html -jg
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