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hi all ,
My objective is to connect the XILINX S3A FPGA Board with PC
using Ethernet .that is i want to send and receive data to/from the PC.
and after that i have to control other h/w of the board by
sending data through ethernet as selected in GUI.
but for this purpose i dont want to implement TCP/IP .i just simply
want to
send and receive MAC Packets i.e preamble+Destination Address+source
address
+type+data+FCS
i am using EDK and emaclite to implement the MAC.
my questions are :
1) how can i read and send the packets from PC .
2) is any s/w available to do so.
3) is there any s/w language which supports direct reading/writing of
MAC port of PC (e.g we can read/write the com port)
4) does any body has the code for the same.
Article: 140426On May 13, 9:54=A0am, "raghu" <raghunandan...@gmail.com> wrote: > Hi, Please help in connecting two bidirectional pins (A,B)of an FPGA. > The data lines should connect A to B when write enable is low. > The data lines should connect B to A when read enable is low. > > let me know your inputs. In VHDL: B <=3D A when write_en =3D '0' else (others =3D> 'Z'); A <=3D B when read_en =3D '0' else (others =3D> 'Z'); -Dave PollumArticle: 140427
On May 13, 1:10=A0am, mng <michael.jh.ng@gmail.com> wrote: > On May 13, 12:47=A0am, mng <michael.jh...@gmail.com> wrote: > > > > > On May 12, 1:34=A0pm, Dave <dhsch...@gmail.com> wrote: > > > > I have an ML403 devkit and am attempting to program the XCF32P by bit= - > > > banging the JTAG interface from a microcontroller devboard. My proble= m > > > is that the FPGA does not want to configure with from the PROM when I > > > load it this way. I have tried to troubleshoot the issue and found th= e > > > following: > > > > 1. If I program the flash using iMPACT, erase Revision 0 (the only on= e > > > I'm using), and then program Revision 0 from the microcontroller, the > > > FPGA will configure successfully. When performing this test, I do > > > verify that Revision 0 was successfully erased before I re-program it= . > > > > 2. If I erase the entire flash, program the relevant registers (DATA- > > > BTC, DATA-CCB, DATA-SUCR, and DONE), and then program Revision 0, the > > > FPGA will NOT configure successfully. I have read out the > > > configuration data as well as the non-data registers to verify they > > > are identical to what is programmed via iMPACT. > > > > I can use iMPACT in my development environment but the final system > > > will not have external access to the JTAG pins and so I need to find = a > > > way to program the flash from an initially blank state. Does anyone > > > have any ideas why Method 2 is not working or other troubleshooting > > > measures I can take? Is there a specific instruction sequence or > > > timing restriction that must be adhered to even though all the > > > registers and data seem correct? > > > I suggest you try writing DONE after writing the PROM data. You may > > also want to generate an SVF using iMPACT and compare the command > > sequences. > > > Good luck, > > Mike > > Actually, I take that back. How do you generate a file to program the > PROM? I don't use the ML403, but have board with XCF08P and XCF32P > which are programmed with emulated JTAG. I use the dialog to generate > an MCS _using revisioning_, even though only rev 0 is used. > > Cheers, > Mike We're using the .bit file, minus the header (basically, the .bin file). We do write DONE after writing the data to the Flash, and we've gone through the SVF file to look for something that we're not doing. The SVF file is pretty repetitive, and does things like read out the IDCODE, which we don't do for simplicity's sake. The problem seems to be not in how we program the data blocks, since we can re-program a data area and it configures fine, but something to do with the register setup. However, we don't see a discrepancy in any register values. Is there maybe some issue with the order in which the registers are written?Article: 140428
On May 13, 12:10=A0am, Rob Gaddi <rga...@technologyhighland.com> wrote: > On Tue, 12 May 2009 07:54:52 -0700 (PDT) > > > > > > vcar <hi...@163.com> wrote: > > I want to capture data from an ADC and send to PC though PCI-E. I > > prefer using the Virtex5 XC5VLX20T-FF323 to implement the PCI-E Lane > > X4 interface. I need real time data capturing, and the input data rate > > is about 500Mbytes per second. Although the PCI-E X4 could provide a > > data channel of about 800Mbytes per second (based on the Xilinx ML555 > > PCI-E X4 experiment data), I am afraid that if the host PC has other > > PCI-E devices(say video card or another data capture card), and the > > data transfer performance would be affected. Therefore I need proper > > data buffering: > > > A. Use Block RAM to buffer captured data. The buffer is quite > > small, I could use twenty 36kBRAM at most, equivalent to 20X2Kbytes =3D > > 40Kbytes. I do not know whether this buffering depth is enough or > > not. If the PCI-E bus is very busy or other device is occupying for a > > long time, the buffer will overflow. > > > B. Use external DDR2 memory to buffer captured data. The > > buffer depth is not a problem, but I need to implement an 32bit DDR2 > > interface, and the free user I/O of FF323 package is not enough. I > > have to choose XC5VLX30T-FF665, which will increase the cost largely. > > > Now I am eager to prove that 20~40Kbytes buffer depth is enough for my > > application. However I check the PCI-E v1.1 spec for several days, > > this is not such conclusion or experiment data. > > > Please give me some suggestions. Thanks a lot! > > PCIe is a point-to-point link, not a shared bus. =A0You own the four > lanes coming up to your board entirely, no time sharing. > > The problem is that you don't know whether those lines go directly back > to your northbridge/RAM controller or whether they're going through a > PCIe-PCIe switch that you're sharing with other devices. =A0But that's > not anything you'll be able to find in the PCIe documentation, that's > specific to the actual motherboard you're plugged into. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order- Hide quoted text - > > - Show quoted text - Thank you. Since there are always some uncertainties in real world, and I could not assume that north bridge is always free for capturing data. The FPGA BRAM buffering may be not sufficient enough. And the best safe method is to add the DDR2 for buffering. Is this right?Article: 140429
I would consider the Igloo nano. The Max II doesn't have embedded Ram. BertArticle: 140430
tpsooraj <sooraj.tp@nestgroup.net> wrote: < I used VIRTEX-5 DSP48E slice in order to implement a high speed logic < design which involves 3 parallel multiply-add logic.I need to operate the < design in to about 500MHz. When using single multiply-add unit, i got the < required frequency. But the issue is when using multiple multiply-add unit. The solution is usually pipelining. That is how they build fast general-purpose processors and, given the availability of flip-flops in FPGAs, especially convenient. < Also when i gave inputs directly without using I/O pads(ie hard coding < input values), i got maximum operating frequency as 500 MHz.So any one < please suggest an idea to avoid this issue and to get maximum operating < frequency. Not knowing anything about your design, be sure to have registers in the I/O pads for both input and output. -- glenArticle: 140431
jayantbala <jayantbala@gmail.com> wrote: (snip) < but for this purpose i dont want to implement TCP/IP < .i just simply want to send and receive MAC Packets i.e < preamble+Destination Address+source address+type+data+FCS For type X'0800' that will be hard on many systems. If you don't need or want TCP, can you use UDP? It is a very simple header to add and then send it out. Receivers can ignore the header, if that is easier, though they should probably verify the IP address. -- glenArticle: 140432
On Wed, 13 May 2009 01:31:31 -0700 (PDT) aitezaz.abd@gmail.com wrote: > On May 13, 11:31=A0am, Sandro <sdro...@netscape.net> wrote: > > On May 13, 7:46=A0am, aitezaz....@gmail.com wrote: > > > > > Hi, > > > I want to implement 100 Mbps ethernet MAC with a 1000/100/10 PHY > > > capable PHY that is by default set to 1000Mbps. I have connected > > > the RGMII interface and MDIO interface but i dont know how to put > > > this PHY into auto negotiation mode or force it to run on 100 > > > Mbps. Please guide in this regard. i.e. (which MDIO register i > > > should write to control this thing). > > > > > Aitezaz > > > > Aitezaz, > > What about reading the datasheet of your phy? > > Anyway, for the 100/10 Phy the clause 22 of the 802.3 standard > > does require the register 0 > > =A0 bit 13 set the speed, (10 or 100) > > =A0 bit 12 enable/disable autonegotiation > > =A0 bit 8 set the duplex mode > > For your 1000/100/10 phy but please read the datasheet > > > > Sandro >=20 > Thanks Sandro for help. The board is using BCM5464SR (on NETFPGA) > whose datasheet doesn't tell anything about it. But as you written the > standard name, I have found the registers in the standard. > Thank you again >=20 > Aitezaz What, a Broadcom PHY with bad/nonexistant/unavailable documentation? Such a thing has never before in all of history occurred. --=20 Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 140433
On Wed, 13 May 2009 11:23:00 +0100 Mike Harrison <mike@whitewing.co.uk> wrote: > I'm looking at a possible application and trying to figure the > relative costs of FPGA/CPLD versus MCU. > I can do it with a microcontroller, but the only MCUs with the > hardware I need (TFT LCD controller) tend to come with lots of other > stuff (ethernet, large flash, USB etc.) which I don't need. > > As it can be hard to get 'real' prices of FPGAs without talking to > all the distis etc. I wonder if anyone can suggest parts to look at . > > Rough reqiurement is : > > Cheapest in 100x qtys for total solution inc. config and power supply > ( from 3.3v supply), below about GBP5(US$7.5) > Not BGA > Readly available : ex-stock or sensible leadtimes (2 weeks) > A couple of RAM blocks, around 1K byte each > about 60 IOs, all 3.3v > 30MHz clock > Logic equivalent to around 100 CPLD macrocells > Free or low cost (<$500) design software > > The Xilinx S3A/AN-50 is the cheapest I've found so far, but is a a > bit over-specced. CPLDs seem to get expensive above 72 cells and > don't tend to have RAM > > When I did some pricing pusharounds on the 3As, I came to the conclusion that it was cheaper to get the 3A and an external SPI flash than to get the 3AN. It also allows you more choices in the FPGA packaging. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 140434
On May 13, 5:26=A0pm, Dave <dhsch...@gmail.com> wrote: > On May 13, 1:10=A0am, mng <michael.jh...@gmail.com> wrote: > > > > > On May 13, 12:47=A0am, mng <michael.jh...@gmail.com> wrote: > > > > On May 12, 1:34=A0pm, Dave <dhsch...@gmail.com> wrote: > > > > > I have an ML403 devkit and am attempting to program the XCF32P by b= it- > > > > banging the JTAG interface from a microcontroller devboard. My prob= lem > > > > is that the FPGA does not want to configure with from the PROM when= I > > > > load it this way. I have tried to troubleshoot the issue and found = the > > > > following: > > > > > 1. If I program the flash using iMPACT, erase Revision 0 (the only = one > > > > I'm using), and then program Revision 0 from the microcontroller, t= he > > > > FPGA will configure successfully. When performing this test, I do > > > > verify that Revision 0 was successfully erased before I re-program = it. > > > > > 2. If I erase the entire flash, program the relevant registers (DAT= A- > > > > BTC, DATA-CCB, DATA-SUCR, and DONE), and then program Revision 0, t= he > > > > FPGA will NOT configure successfully. I have read out the > > > > configuration data as well as the non-data registers to verify they > > > > are identical to what is programmed via iMPACT. > > > > > I can use iMPACT in my development environment but the final system > > > > will not have external access to the JTAG pins and so I need to fin= d a > > > > way to program the flash from an initially blank state. Does anyone > > > > have any ideas why Method 2 is not working or other troubleshooting > > > > measures I can take? Is there a specific instruction sequence or > > > > timing restriction that must be adhered to even though all the > > > > registers and data seem correct? > > > > I suggest you try writing DONE after writing the PROM data. You may > > > also want to generate an SVF using iMPACT and compare the command > > > sequences. > > > > Good luck, > > > Mike > > > Actually, I take that back. How do you generate a file to program the > > PROM? I don't use the ML403, but have board with XCF08P and XCF32P > > which are programmed with emulated JTAG. I use the dialog to generate > > an MCS _using revisioning_, even though only rev 0 is used. > > > Cheers, > > Mike > > We're using the .bit file, minus the header (basically, the .bin > file). We do write DONE after writing the data to the Flash, and we've > gone through the SVF file to look for something that we're not doing. > The SVF file is pretty repetitive, and does things like read out the > IDCODE, which we don't do for simplicity's sake. The problem seems to > be not in how we program the data blocks, since we can re-program a > data area and it configures fine, but something to do with the > register setup. However, we don't see a discrepancy in any register > values. Is there maybe some issue with the order in which the > registers are written? i wish i would remember what it was, i had exact same thing looked the SVF file like crazy did all the same compared and read back and not worked i may dig out old known working code, but not sure if that would help AnttiArticle: 140435
On May 13, 4:50=A0pm, smith...@gmail.com wrote: > On May 13, 6:23=A0am, Mike Harrison <m...@whitewing.co.uk> wrote: > > > The Xilinx S3A/AN-50 is the cheapest I've found so far, but is a a bit = over-specced. > > CPLDs seem to get expensive above 72 cells and don't tend to have RAM > > You might want to take a look at the following devices: > > Lattice Semi - MachXO devices with embedded RAM too expensive > Lattice Semi - Lattice XP / XP2 I already suggested, but even XP3-vq100 is too expensive with standard pricing > Altera - Cyclone II / III way too expensive for target budget > Xilinx - Spartan 3A/AN nothing in stock? AN too expensive, A, maybe > Silicon Blue - iCE 65 also too expensive for the volume/target price > > The MachXO looks to be exactly what you are after, although I don't > know what they cost. =A0The Lattice tools come with an Synplify OEM > bundled, but I don't know what they cost or if older versions are > available for free. Hope that helps .Article: 140436
On Wed, 13 May 2009 03:58:40 -0700 (PDT), "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com> wrote: >On May 13, 1:23 pm, Mike Harrison <m...@whitewing.co.uk> wrote: >> I'm looking at a possible application and trying to figure the relative costs of FPGA/CPLD versus >> MCU. >> I can do it with a microcontroller, but the only MCUs with the hardware I need (TFT LCD controller) >> tend to come with lots of other stuff (ethernet, large flash, USB etc.) which I don't need. >> >> As it can be hard to get 'real' prices of FPGAs without talking to all the distis etc. I wonder if >> anyone can suggest parts to look at . >> >> Rough reqiurement is : >> >> Cheapest in 100x qtys for total solution inc. config and power supply ( from 3.3v supply), below >> about GBP5(US$7.5) >> Not BGA >> Readly available : ex-stock or sensible leadtimes (2 weeks) >> A couple of RAM blocks, around 1K byte each >> about 60 IOs, all 3.3v >> 30MHz clock >> Logic equivalent to around 100 CPLD macrocells >> Free or low cost (<$500) design software >> >> The Xilinx S3A/AN-50 is the cheapest I've found so far, but is a a bit over-specced. >> CPLDs seem to get expensive above 72 cells and don't tend to have RAM > >the IC you need is always the one that doesnt exist ;) > >S3-50AN prices do go below 4$ but not at 100x qty. >in 100x qty, it proabably more than your target price 7.5 (depend how >good you deal..) > >Xilinx disties say: leadtime 12 weeks, call for order >Digikey has 4 pcs in stock > >if you can deal with 2 KB RAM, then lattice EC1 is 6.1$ online price >available in stock, need spi flash, but it still cheap total price > >but here XC3S50A would be better at about same price > >Lattice XP3 is too expensive with online pricing.. $10, stock YES, >this is the IC that needs NO Externals, no flash, no LDO, just 3.3V ! > >Actel A3P060, is cheap, but again 2K RAM only > >all the above have free tools >Altera doesnt seem to have devices that come to your desired price >range > >hm.. call lattice disti, say you would like XP3-VQ100, but your BOM >limit is 7.5$ see what they say !! > >if price doesnt come down, place xc3s50a-vq100 order on digikey, to >secure your devices before those are gone too (disties have no stock. >leadt=12w) > >Antti Thanks for the suggestions - the Lattice EC1 looks a pretty good fit on all counts - RAM is 'only just' enough, but means I'm not paying for stuff I don't need. I even found a cheap eval board for it : http://www.msc-toolguide.com/latticeec-low-cost-evaluation-board.htmlArticle: 140437
On May 13, 1:00=A0pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > i wish i would remember what it was, i had exact same thing > looked the SVF file like crazy > did all the same > compared and read back > and not worked > > i may dig out old known working code, but not sure if that would help > > Antti Glad to know I'm not the only one, at least. I really wish the documentation were better on this. I also wish the iMPACT SVF player were faster - it takes hours (no exaggeration) to play out an svf file for a XC4VLX25! DaveArticle: 140438
On Wed, 13 May 2009 00:17:32 -0700 (PDT), Marteno Rodia <marteno_rodia@o2.pl> wrote: >On May 12, 5:21 pm, Muzaffer Kal <k...@dspia.com> wrote: >> By looking at your name of the pad (and assuming there is a clk200_p) >> I'm assuming you want differential IO. If that's the case you need to >> add a property to your UCF file marking them so ie LVPECL etc. > >All, thank you for your answers. Yes, I'm using differential clock >signals. I've checked also the pins once more, they're correct. I >incline to thinking that there's an important constraint in the UCF >file missing. The problem is I don't know the constraint which needs >to be added (I'm not very familiar with Xilinx yet). >In the UCF file I have specified the NET-LOC constraints as well as >IOSTANDARD definition. For clock inputs I used LVPECL_25: > >NET "clk200_n" IOSTANDARD = LVPECL_25; > >Then, I added DIFF_TERM (please, don't ask why, I've found in Google): > >NET "clk200_n" IOSTANDARD = LVPECL_25 | DIFF_TERM = TRUE; > >The result is the same as before (identical error message). If it can >help, the Target Device is xc5vsx95t (Virtex-5 family). > >MR :/ Which device are you using and which IOs are you trying to use? Also how are you instantiating the IO pad(s) (and the associated BUFG)? Please show those 2/3 lines here.Article: 140439
On Wed, 13 May 2009 08:54:25 -0500, "tpsooraj" <sooraj.tp@nestgroup.net> wrote: >Hi, > >I used VIRTEX-5 DSP48E slice in order to implement a high speed logic >design which involves 3 parallel multiply-add logic.I need to operate the >design in to about 500MHz. When using single multiply-add unit, i got the >required frequency. But the issue is when using multiple multiply-add unit. >Also when i gave inputs directly without using I/O pads(ie hard coding >input values), i got maximum operating frequency as 500 MHz.So any one >please suggest an idea to avoid this issue and to get maximum operating >frequency. > Register your inputs after the IO and before they go into the DSP blocks. DSP48E has an internal accumulator which can add the output of another DSP48E to the output of its own multiplier but this path is quite slow. Your best option might be to use 3 multipliers, register the outputs and add the result in the fabric. If the 3 input adder takes too long, you can pipeline it to 2 2-input adders. >Thanxs in advance If you use an 'x' you don't need an 's'. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 140440
"jayantbala" <jayantbala@gmail.com> wrote:
>hi all ,
> My objective is to connect the XILINX S3A FPGA Board with PC
>using Ethernet .that is i want to send and receive data to/from the PC.
> and after that i have to control other h/w of the board by
>sending data through ethernet as selected in GUI.
>
>
> but for this purpose i dont want to implement TCP/IP .i just simply
>want to
> send and receive MAC Packets i.e preamble+Destination Address+source
>address
> +type+data+FCS
>
> i am using EDK and emaclite to implement the MAC.
>
> my questions are :
> 1) how can i read and send the packets from PC .
> 2) is any s/w available to do so.
> 3) is there any s/w language which supports direct reading/writing of
>MAC port of PC (e.g we can read/write the com port)
> 4) does any body has the code for the same.
Look for libpcap at http://www.tcpdump.org/
With libpcap you can receive and send raw data from and to your
ethernet adapter.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 140441On May 12, 8:06=A0am, Marteno Rodia <marteno_ro...@o2.pl> wrote: > I got used to Altera, but now I have to launch a big project in Xilinx > Virtex. > > My problem which I encountered today is that message: > > ERROR:Pack:1107 - Unable to combine the following symbols into a > single IOB > =A0 =A0component: > =A0 =A0 =A0 =A0 PAD symbol "clk200_n" (Pad Signal =3D clk200_n) > =A0 =A0 =A0 =A0 SlaveBuffer symbol "u_infrastructure/u_ibufg_clk200/ > SLAVEBUF.DIFFIN" (Output > =A0 =A0Signal =3D u_infrastructure/u_ibufg_clk200/SLAVEBUF.DIFFIN) > =A0 =A0An IO component of type IOB was chosen because the IO contains > symbols and/or > =A0 =A0properties consistent with input, output, or bi-directional usage > and > =A0 =A0contains no other symbols or properties that require a more > specific IO > =A0 =A0component type. > =A0 =A0Each of the following constraints specifies an illegal physical > site for a > =A0 =A0component of type IOB: > =A0 =A0 =A0 =A0 Symbol "clk200_n" (LOC=3DC8 [Physical Site Type =3D IPAD]= ) > =A0 =A0The component type is determined by the types of logic and the > properties and > =A0 =A0configuration of the logic it contains. Please double check that > the types of > =A0 =A0logic elements and all of their relevant properties and > configuration options > =A0 =A0are compatible with the physical site type of the constraint. > =A0 =A0Please correct the constraints accordingly. > > More or less, I understand the problem. Some important information is > missing in my UCF file, which I prepared, but incorrectly. Please help > me. What should I do to "correct the constraints accordingly"? Please explain how you understand the problem as you mentioned aboveArticle: 140442
On Wed, 13 May 2009 08:40:07 +0200, Matthias Alles <REMOVEallesCAPITALS@NOeit.SPAMuni-kl.de> wrote: >Hi! > >Anyone here worked with these asynchronous FPGAs already? I wonder what >the prices are. I was quoted around $15k for a development kit (tools, dev board). That was outside our budget for familiarization with a new non-mainstream technology, so we haven't yet pursued it. >It doesn't look like the tool-flow will be for free, >since they use Synplify Pro or Precision for synthesis. But I'd love to >see the performance of one of our designs on the their FPGAs.. > >If only have of the promises are true this would be really great! Yes, they look very interesting indeed. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 140443
On May 13, 1:45=A0pm, Mike Harrison <m...@whitewing.co.uk> wrote: > On Wed, 13 May 2009 03:58:40 -0700 (PDT), "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > >On May 13, 1:23=A0pm, Mike Harrison <m...@whitewing.co.uk> wrote: > >> I'm looking at a possible application and trying to figure the relativ= e costs of FPGA/CPLD versus > >> MCU. > >> I can do it with a microcontroller, but the only MCUs with the hardwar= e I need (TFT LCD controller) > >> tend to come with lots of other stuff (ethernet, large flash, USB etc.= ) which I don't need. > > >> As it can be hard to get 'real' prices of FPGAs without talking to all= the distis etc. I =A0wonder if > >> anyone can suggest parts to look at . > > >> Rough reqiurement is : > > >> Cheapest in 100x qtys for total solution inc. config and power supply = ( from 3.3v supply), below > >> about GBP5(US$7.5) > >> Not BGA > >> Readly available : ex-stock or sensible leadtimes (2 weeks) > >> A couple of RAM blocks, around 1K byte each > >> about 60 IOs, all 3.3v > >> 30MHz clock > >> Logic equivalent to around 100 CPLD macrocells > >> Free or low cost (<$500) design software > > >> The Xilinx S3A/AN-50 is the cheapest I've found so far, but is a a bit= over-specced. > >> CPLDs seem to get expensive above 72 cells and don't tend to have RAM > > >the IC you need is always the one that doesnt exist ;) > > >S3-50AN prices do go below 4$ but not at 100x qty. > >in 100x qty, it proabably more than your target price 7.5 (depend how > >good you deal..) > > >Xilinx disties say: leadtime 12 weeks, call for order > >Digikey has 4 pcs in stock > > >if you can deal with 2 KB RAM, then lattice EC1 is 6.1$ online price > >available in stock, need spi flash, but it still cheap total price > > >but here XC3S50A would be better at about same price > > >Lattice XP3 is too expensive with online pricing.. $10, stock YES, > >this is the IC that needs NO Externals, no flash, no LDO, just 3.3V ! > > >Actel A3P060, is cheap, but again 2K RAM only > > >all the above have free tools > >Altera doesnt seem to have devices that come to your desired price > >range > > >hm.. call lattice disti, say you would like XP3-VQ100, but your BOM > >limit is 7.5$ see what they say !! > > >if price doesnt come down, place xc3s50a-vq100 order on digikey, to > >secure your devices before those are gone too (disties have no stock. > >leadt=3D12w) > > >Antti > > Thanks for the suggestions - the Lattice EC1 looks a pretty good fit on a= ll counts - RAM is 'only > just' enough, but means I'm not paying for stuff I don't need. > > I even found a cheap eval board for it :http://www.msc-toolguide.com/latt= iceec-low-cost-evaluation-board.html I had to do this same search last year and I found very little that would suit my needs... in fact, I found exactly one part that really was suited to the job. The problem you will find with most parts is not actually the price of the part itself, but rather the price of the package. The FPGA vendors will attest to the fact that the pricing of these parts at the low end is mostly governed by testing which is in tern dominated by the cost of testing the I/Os. So the lower the pin count, the cheaper the part. I also has space constraints which in the end led me to the Lattice XP in the 100 pin QFP package. It is about $10 (or maybe a squeak less) at qty 100 and was the only comparable part in this price range. Remember that the XP has internal Flash and the ram parts do not. I remember that some ram based FPGA vendors would jump up and down and insist that ram was the only way to go when considering the advantages of die size and how it would impact the cost. I guess that really is not the whole picture is it? I am using the LFXP3C-3TN100C which is 3.3 volt only power with 63 or 64 I/Os, IIRC, commercial temp and the slowest speed grade. If you sweet talk you local disti or Lattice rep, I bet you can get them for $9. I am actually using contract turnkey assembly, so I don't know exactly what they are paying, but my local guy has quoted me $9.50 for preprogrammed parts. The only issue may be availability, but then I have never found *any* FPGA that they maintain significant amounts of stock at all times. Mouser sells Lattice, but the inventory is mostly at Lattice and is drop shipped. I did not find one other part that was better in any regard and I don't recall finding any others that met all these constraints... but then it was a year ago... RickArticle: 140444
Marteno Rodia skrev: > I got used to Altera, but now I have to launch a big project in Xilinx > Virtex. > > My problem which I encountered today is that message: > > ERROR:Pack:1107 - Unable to combine the following symbols into a > single IOB > component: > PAD symbol "clk200_n" (Pad Signal = clk200_n) > SlaveBuffer symbol "u_infrastructure/u_ibufg_clk200/ > SLAVEBUF.DIFFIN" (Output > Signal = u_infrastructure/u_ibufg_clk200/SLAVEBUF.DIFFIN) > An IO component of type IOB was chosen because the IO contains > symbols and/or > properties consistent with input, output, or bi-directional usage > and > contains no other symbols or properties that require a more > specific IO > component type. > Each of the following constraints specifies an illegal physical > site for a > component of type IOB: > Symbol "clk200_n" (LOC=C8 [Physical Site Type = IPAD]) > The component type is determined by the types of logic and the > properties and > configuration of the logic it contains. Please double check that > the types of > logic elements and all of their relevant properties and > configuration options > are compatible with the physical site type of the constraint. > Please correct the constraints accordingly. > > More or less, I understand the problem. Some important information is > missing in my UCF file, which I prepared, but incorrectly. Please help > me. What should I do to "correct the constraints accordingly"? It sound to mee that one fo the followig could be the reason for the trouble: 1. clk200_n and clk200_p are not placed at _N and _P type pins check pinout table for you package 2. The logic standard is not supported in bank where the pins are located, check that the VCCIO voltage support the standards you use in that bank 3. An identical pin location is already used elsewhere 4. More deeper placement trouble.. ?? Yes there's a lot of details to know about when using FPGAs, but it's nothing different from Altera or other FPGA companies.. So just keep reading the datasheets and user guides... Good luck Finn Nielsen www.morphologic.dkArticle: 140445
Dear All: I am thinking about my system, the picture is here: http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/ I want to transfer the raw/processed image sensor data to USB 2.0 or dpram. Two choices: 1. ADC -> DSP, this means parallel ADC, then DSP processed data -> USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA- >DPRAM 2. ADC -> FPGA, this means serial ADC or whatever, then FPGA<---- EMIF---->DSP processed data, data feedbacked from DSP to FPGA -> USB, DSP works as a coprocessor. In choice 2, the USB could also connect from DSP but this will accelerate processed data transfer, decelerate the raw data transfer. Other questions: I also need to store raw data, thus the data saving path will be different: Choice 1: the raw data will be from ADC -> DSP -> FLASH Choice 2: the raw data will be from ADC -> FLASH -> DSP It will meet the same question when I save processed data on board. The last question is FIFO vs. DPRAM, FIFO could be implemented in FPGA, could DPRAM be implemented in FPGA? the DPRAM has more flexibility for sure. Thanks!Article: 140446
On May 13, 10:26=A0am, Dave <dhsch...@gmail.com> wrote: > On May 13, 1:10=A0am, mng <michael.jh...@gmail.com> wrote: > > > > > On May 13, 12:47=A0am, mng <michael.jh...@gmail.com> wrote: > > > > On May 12, 1:34=A0pm, Dave <dhsch...@gmail.com> wrote: > > > > > I have an ML403 devkit and am attempting to program the XCF32P by b= it- > > > > banging the JTAG interface from a microcontroller devboard. My prob= lem > > > > is that the FPGA does not want to configure with from the PROM when= I > > > > load it this way. I have tried to troubleshoot the issue and found = the > > > > following: > > > > > 1. If I program the flash using iMPACT, erase Revision 0 (the only = one > > > > I'm using), and then program Revision 0 from the microcontroller, t= he > > > > FPGA will configure successfully. When performing this test, I do > > > > verify that Revision 0 was successfully erased before I re-program = it. > > > > > 2. If I erase the entire flash, program the relevant registers (DAT= A- > > > > BTC, DATA-CCB, DATA-SUCR, and DONE), and then program Revision 0, t= he > > > > FPGA will NOT configure successfully. I have read out the > > > > configuration data as well as the non-data registers to verify they > > > > are identical to what is programmed via iMPACT. > > > > > I can use iMPACT in my development environment but the final system > > > > will not have external access to the JTAG pins and so I need to fin= d a > > > > way to program the flash from an initially blank state. Does anyone > > > > have any ideas why Method 2 is not working or other troubleshooting > > > > measures I can take? Is there a specific instruction sequence or > > > > timing restriction that must be adhered to even though all the > > > > registers and data seem correct? > > > > I suggest you try writing DONE after writing the PROM data. You may > > > also want to generate an SVF using iMPACT and compare the command > > > sequences. > > > > Good luck, > > > Mike > > > Actually, I take that back. How do you generate a file to program the > > PROM? I don't use the ML403, but have board with XCF08P and XCF32P > > which are programmed with emulated JTAG. I use the dialog to generate > > an MCS _using revisioning_, even though only rev 0 is used. > > > Cheers, > > Mike > > We're using the .bit file, minus the header (basically, the .bin > file). We do write DONE after writing the data to the Flash, and we've > gone through the SVF file to look for something that we're not doing. > The SVF file is pretty repetitive, and does things like read out the > IDCODE, which we don't do for simplicity's sake. The problem seems to > be not in how we program the data blocks, since we can re-program a > data area and it configures fine, but something to do with the > register setup. However, we don't see a discrepancy in any register > values. Is there maybe some issue with the order in which the > registers are written? That could be it. For reference, my program (actually, written by a colleague) writes DATA_BTC, then the PROM data, then DATA_SUCR and DATA_CCB and DATA_DONE.Article: 140447
On May 13, 1:54=A0pm, ligu...@gmail.com wrote: > Dear All: > > I am thinking about my system, the picture is here: > > http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/ > > I want to transfer the raw/processed image sensor data to USB 2.0 or > dpram. > > Two choices: > > 1. ADC -> DSP, this means parallel ADC, then DSP processed data -> > USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA- > > >DPRAM > > 2. ADC -> FPGA, this means serial ADC or whatever, then FPGA<---- > EMIF---->DSP processed data, data feedbacked from DSP to FPGA -> USB, > DSP works as a coprocessor. > In choice 2, the USB could also connect from DSP but this will > accelerate processed data transfer, decelerate the raw data transfer. > > Other questions: > > I also need to store raw data, thus the data saving path will be > different: > Choice 1: the raw data will be from ADC -> DSP -> FLASH > Choice 2: the raw data will be from ADC -> FLASH -> DSP =20 ~~~~FPGA->FLASH > It will meet the same question when I save processed data on board. > > The last question is FIFO vs. DPRAM, FIFO could be implemented in > FPGA, could DPRAM be implemented in FPGA? the DPRAM has more > flexibility for sure. > > Thanks!Article: 140448
Dear All: I am thinking about my system, the picture is here: http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/ I want to transfer the raw/processed image sensor data to USB 2.0 or dpram. Two choices: 1. ADC -> DSP, this means parallel ADC, then DSP processed data -> USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA- >DPRAM 2. ADC -> FPGA, this means serial ADC or whatever, then FPGA<---- EMIF---->DSP processed data, data feedbacked from DSP to FPGA -> USB, DSP works as a coprocessor. In choice 2, the USB could also connect from DSP but this will accelerate processed data transfer, decelerate the raw data transfer. Other questions: I also need to store raw data, thus the data saving path will be different: Choice 1: the raw data will be from ADC -> DSP -> FLASH Choice 2: the raw data will be from ADC -> FPGA -> FLASH (Is Flash good for fast data saving, or use EEPROM instead?) It will meet the same question when I save processed data on board. The last question is FIFO vs. DPRAM, FIFO could be implemented in FPGA, could DPRAM be implemented in FPGA? the DPRAM has more flexibility for sure. Thanks!Article: 140449
On May 11, 2:26=A0am, hamze60 <hamz...@gmail.com> wrote: > I want to design a space system and don't want to use airspace > expensive fpga. considering space radiation I want to make this system > fault tolerant. ACTEL is flash-based but in program lost condition > ( even with low probability ) it should be reprogrammed so a > programing circuit is also needed. Xilinx or Altera are RAMbased but > they have very small size EPROMs to store both hardware configuration > and software, so using multiple of EPROMs is possible for redundancy. > can anybody suggest better solution or even a new idea? Sorry to ask, how expensive is that the airspace FPGA in comparison to the other high end devices?
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