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On May 28, 12:36=A0am, Jacko <jackokr...@gmail.com> wrote: > Open source microprocessor. BSD.http://nibz.googlecode.comjust in > case you were wondering. no, we are not. no one is. AnttiArticle: 140876
On May 28, 7:16=A0am, radarman <jsham...@gmail.com> wrote: > I've been using Xilinx for a few years now, but my new job is strictly > Altera. Mostly Cyclones, with a few Max parts thrown in here and > there. I figured it wouldn't hurt to compare the latest "cheap" > offerings from Xilinx and Altera - and retrain myself on Quartus at > home. > > I can sort of figure out, based on the definition of an LE vs a CLB > approximately which parts are equivalent, but without actually > compiling designs for both, I'm not sure how the Cyclone III stacks up > against its equivalent Spartan 3 (or in my case 3E) part? > > However, I'd like a sanity check. I'm thinking of using a EP3C16E144 > for my next design. I'd like to steer clear of BGA's, and the 144 pin > QFP has more than enough I/O for the task. What would the equivalent > Spartan 3 series part? It looks like something between a 3E500 and > 3E1200, which if true, would be just about perfect for what I'm trying > to do. it depends what resources you use. Cyclone does not have distributed RAM or SRL16 so if you have design that uses a real lot of them, it would get much larger in Altera if not then you can compare based lut vs LE AnttiArticle: 140877
Hi, I am using a small boot loader to copy an application to SDRAM and it's vectors to address 0x00. While using the Spartan 3an starter kit, I would create a pointer to address 0x00 and write directly into that address. I.E. unsigned char *pointer = 0x00;Article: 140878
# So anyone that knows where to get an Altera LP6 Logic Programming card # please let me know. I'm willing to purchase it if the price is reasonable. An alternative could be to look for a Universal Pgmr on EBAY, that supports EPM7128's ? Or ask Altera for the Algorithm, hoping that someone still works there from this era ;) -jgArticle: 140879
Nad a formulé la demande : > Hi, > I didn't find any information concerning cyclone3 device and other serial > flash connection thant the Altera ones. > I would like to implement a cyclone3 FPGA with an AT45DB serial flash but > find nowhere some explanation on this point. > Does anybody already try to do this? or does anybody have a paper on > this? > > THanks in advance > > Nad Hi Nad, I suggest you carefully compare your Atmel Flash commands vs Altera's EPCS that are described at : http://www.altera.com/literature/hb/cfg/cyc_c51014.pdf I know by experience that many serial flash devices (ST, Numonics...) are "quite compatible". It's not had to be compatible enough to be used to hold the bitstream & load the FPGA at powerup. If you want to use the standard Altera programming tools, you need to check more commands beyond the simple read operations (you'll need erase and write, indeed). Update incompatibility can be overcome by using other tools, including remote update through the FPGA (we have implemented this remote programming option in our Ethernet kit). Hope this helps, BertArticle: 140880
On May 28, 1:51=A0am, "hvo" <hai...@synrad.com> wrote: > Hi, > > I am using a small boot loader to copy an application to SDRAM and it's > vectors to address 0x00. =A0While using the Spartan 3an starter kit, I wo= uld > create a pointer to address 0x00 and write directly into that address. I.= E. > > unsigned char *pointer =3D 0x00; To avoid warnings, you may want to write something like: unsigned char *pointer =3D (unsigned char *)0x00; Otherwise I don't see why this shouldn't work. I presume you're using a MicroBlaze? Regards, GaborArticle: 140881
On May 27, 1:10=A0pm, "PrAsHaNtH@IIT" <prashaena...@gmail.com> wrote:
> hi
>
> I know $memreadh, $memreadb are used to read data from a text file. I
> have used a memory file for reading data.
>
> reg [0:7] mem[1:500];
> initial
> $memreadh("input.mem", mem);
>
> In this case, .mem file is created in Xilinx ISE only. But, if I want
> to use .txt or .dat files, what is the syntax.
> I mean, we should give any path to a file whre it is stored. If so,
> tell me whre the file should be saved. I am usign Xilinx Ise. So,
> should it be saved in xilinx ise installation files??
>
> Similarly, what is the verilog command for writing data to a text
> file.
>
> what is the difference between fread and $memreadh??
>
> Will the module programs with $memreadh, $memreadb, fread, fwrite
> tasks be synthesized??
>
> Please let me know these anss.
>
> Thanks
I think you mean $readmemh and $readmemb?
You can put files anywhere, but if you don't specify the
full path, your current directory will be the project
directory (for XST). You can specify relative paths
like "../source/memory.hex" (note the UNIX-style forward
slashes).
I would suggest finding a good Verilog reference book.
I use the Verilog Golden Reference Guide from Doulos.
Generally system functions (starting with "$") are
not synthesizable with the exception of those like
$readmemh and $readmemb when used to initialize memory.
Generally speaking the synthesized project has no "system"
to provide these functions, so only those that run during
synthesis will be synthesizable. Anything that might
run in the synthesized project after synthesis, like
writing a file from data collected while running the
project, will not be synthesized.
Regards,
Gabor
Article: 140882Hi, I don't like to print download version of many documents. The download prints are huge and not easy to keep them in order. So that I bought Virtex-4 FPGA Handbook for $10 years ago, and I want to buy Virtex-5 FPGA Handbook too, but cannot find the related information. I also want to buy Altera's Data Handbook. I will appreciate if anyone can pose the website for these books if they are available. Thank you. WengArticle: 140883
>On May 28, 1:51=A0am, "hvo" <hai...@synrad.com> wrote: >> Hi, >> >> I am using a small boot loader to copy an application to SDRAM and it's >> vectors to address 0x00. =A0While using the Spartan 3an starter kit, I wo= >uld >> create a pointer to address 0x00 and write directly into that address. I.= >E. >> >> unsigned char *pointer =3D 0x00; > >To avoid warnings, you may want to write something like: > >unsigned char *pointer =3D (unsigned char *)0x00; > >Otherwise I don't see why this shouldn't work. I presume >you're using a MicroBlaze? > >Regards, >Gabor > Hi Gabor, Yes I am using MicroBlaze. The puzzling thing is that it worked with the starter kit and not the custom board. I am only writing to Block RAM. My code does run the bootload sequence, but I cant write into address 0x00, or any vector addresses. Are there some kind of write protect for the BlockRAM that I am not aware of? Thanks for your reply, Regards hvoArticle: 140884
On May 27, 4:14 pm, jleslie48 <j...@jonathanleslie.com> wrote:
> On May 27, 12:51 pm, Andy Peters <goo...@latke.net> wrote:
>
>
>
> > On May 26, 1:13 pm, jleslie48 <j...@jonathanleslie.com> wrote:
>
> > > > > 23-architecture arch of fifo is
> > > > > 24- type reg_file_type is array (2**W-1 downto 0) of
> > > > > 25- std_logic_vector(B-1 downto 0);
> > > > > 26: signal array_reg: reg_file_type;
> > > > > 27- signal w_ptr_reg, w_ptr_next, w_ptr_succ:
> > > > > 28- std_logic_vector(W-1 downto 0);
> > > > > 29- signal r_ptr_reg, r_ptr_next, r_ptr_succ:
> > > > > --
> > > > > 39- process(clk,reset)
> > > > > 40- begin
> > > > > 41- if (reset='1') then
> > > > > 42: array_reg <= (others=>(others=>'0'));
> > > > > 43- elsif (clk'event and clk='1') then
> > > > > 44- if wr_en='1' then
> > > > > 45: array_reg(to_integer(unsigned(w_ptr_reg)))
> > > > > 46- <= w_data;
> > > > > 47- end if;
> > > > > 48- end if;
> > > > > 49- end process;
> > > > > 50- -- read port
> > > > > 51: r_data <= array_reg(to_integer(unsigned(r_ptr_reg)));
> > > > > 52- -- write enabled only when FIFO is not full
> > > > > 53- wr_en <= wr and (not full_reg);
> > > > > 54-
>
> > > > > Ok, so here's all the code pertaining to array_reg, specifically lines
> > > > > 42, 45, and 51. From what I can understand, it seems that the
> > > > > professionals here are concerned about line 42; the one resulting from
> > > > > the reset signal. What would be the correct way to implement this
> > > > > concept?
>
> > > > Simply delete the asynchronous reset stuff in lines 41 and 42, and
> > > > change the "elsif" on line 43 to a simple "if."
>
> > > > > In C I would of just done a memset(array_reg, 0, sizeof(array_reg))
> > > > > but we ain't in C world any more...
>
> > > > Indeed -- think HARDWARE.
>
> > > > Since you are describing a FIFO, there's no need to reset the memory.
> > > > Simply resetting the read and write pointers effectively clears the
> > > > memory. You will never read from an empty FIFO and a FIFO write
> > > > guarantees that you read valid data.
>
> > > > -a
>
> > > quite right,
>
> > > the other process has:
> > > process(clk,reset)
> > > begin
> > > if (reset='1') then
> > > w_ptr_reg <= (others=>'0');
> > > r_ptr_reg <= (others=>'0');
> > > full_reg <= '0';
> > > empty_reg <= '1';
>
> > > and as my pointers get reset who cares about the data. System
> > > resources went dramatically down as a result of the changes,
>
> > I'm glad the suggestion worked for you!
>
> > > however
> > > two warnings are now being generated that were never there before:
>
> > > WARNING Route - CLK Net:clk_2mhz is being routed on general routing
> > > resources. If you are trying to use local clocking techniques,
> > > evaluate the placement of the clock's source and loads to ensure it
> > > meets the guidelines for local clocking. Otherwise, consider placing
> > > this clock on a dedicated clock routing resource. For more information
> > > on clock routing resources, see the target architecture's user guide.
>
> > > WARNING Route - CLK Net:clk_7812hz is being routed on general routing
> > > resources. If you are trying to use local clocking techniques,
> > > evaluate the placement of the clock's source and loads to ensure it
> > > meets the guidelines for local clocking. Otherwise, consider placing
> > > this clock on a dedicated clock routing resource. For more information
> > > on clock routing resources, see the target architecture's user guide.
>
> > > I can't imagine why these are showing up as a result of "fixing" the
> > > other error.
>
> > Sounds like the clock signals are coming into the FPGA on non-clock
> > pins. You probably didn't see this error before because the original
> > warnings/complaints were issued by XST (the synthesis tool) and you
> > went no further. Now that the source synthesizes, the place and route
> > tools take over, and the warning you get is issued by the router.
>
> > Check your UCF and pin selection.
>
> > -a
>
> H'mmm, I checked the place and route report before and after the
> change in code. the Warnings are definitely not there when the 256
> flip-flop warning is in place.
>
> I'll have to take a look at the UCF and see what can be done with the
> pins I'm using. I'm a bit confused about that, I thought GPIO is
> GPIO, I'm sending in a signal, and that's it, but I know that there is
> a document out there from Xilinx (how they love their documents) that
> says something about the pins... lets me check and see what I can
> find.
OK, so from the UCF I was provided here is the system clock:
---------------------------------
#DRIGMORN PACKAGE IS CP132/CPG132
#
#####################################
#CLOCK
#####################################
NET "SYSTEM_CLOCK" LOC = "M6";
-----------------------------------------------------------------
And from the DS312.pdf, the 'spartan-3E Fpga family: complete data
sheet' document for the spartan 3E I find this:
----------------------------------------------------------------------------------------
Table 132: CP132 Package Pinout (Continued)
XC3S250E
Bank XC3S100E XC3S500E
Pin Name Pin
Name CP132 Ball Type
...
2 IP_L05N_2/M2/GCLK1 IP_L05N_2/M2/GCLK1
N6 DUAL/GCLK
2 IP_L05P_2/RDWR_B/GCLK0 IP_L05P_2/RDWR_B/GCLK0
M6 DUAL/GCLK
...
DS312-4 (v3.7) April 18, 2008 www.xilinx.com
175
Product Specification
----------------------------------------------------------------------------------------
so here is how the system clock is defined in the ucf, no attributes
are assigned to the M6 pin, and
the only attributes at all I see in the whole UCF is:
NET "RXD" LOC = "A7" | PULLUP; #INPUT FROM RS232 CHIP
a PULLUP.
So now I want a 2MHZ "clock" on some other pin, what is the criteria I
should be looking for in a candidate pin?
is that DUAL/GCLK thing significant, or am I supposed to use some
attribute? For that matter what is the full set of
attributes that is available, is it described in any manual? And
Further, am I even on the right track? Is this even the correct
manual to be looking at for this info???
Article: 140885hi, i am working on a project which i would like to simulate end to end using systemc. the project involves several components like CMOS image sensor, RAM, ic2 core, soft processor and software that runs inside this soft processor. For sensor and RAM i can write simulation models in systemC. For i2c and soft processor, my plan is to convert synthesizable code in to systemC and use in simulation. Now the problem is how to integrate the software part in to this simulation so that i can simulate the full system. is it common to do this in practice? if yes, please advice me on how to do it. if this is not the recommended approach, please let me know some better alternatives. Thank you CMOSArticle: 140886
On Thu, 28 May 2009 10:09:21 -0700 (PDT), CMOS <manusha1980@gmail.com> wrote: >hi, >i am working on a project which i would like to simulate end to end >using systemc. the project involves several components like CMOS image >sensor, RAM, ic2 core, soft processor and software that runs inside >this soft processor. For sensor and RAM i can write simulation models >in systemC. For i2c and soft processor, my plan is to convert >synthesizable code in to systemC and use in simulation. Now the >problem is how to integrate the software part in to this simulation so >that i can simulate the full system. >is it common to do this in practice? if yes, please advice me on how >to do it. >if this is not the recommended approach, please let me know some >better alternatives. > >Thank you >CMOS This is certainly something which needs to be done in a full verification flow. Depending on what level of speed and/or accuracy you want there are two main ways. You can either write your software in such a way to mimic the bus transactions it will generate (or add a wrapper layer to do this) and run software within the SystemC kernel or you can run a compiled binary of your software within the SystemC model of the processor if you have it. The latter path will be more accurate of course and you have the possibility of getting cycle accurate results from it but of course there is a large simulation time penalty. It is also possible to do this in stages so that you can start with the first approach early in the design and move to the second one at a much later point in order not to get impacted during early system development. Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 140887
On May 27, 5:43 pm, rickman <gnu...@gmail.com> wrote: > On May 27, 4:10 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > On May 27, 1:33 pm, Muzaffer Kal <k...@dspia.com> wrote: > > > > On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 > > > > <j...@jonathanleslie.com> wrote: > > > >on a spartan 3e, the DCM speaks to havein a high-resolution phase > > > >shifting function, but it goes on and says the DCM has a wide > > > >frequency range of 5MHz to 300MHz. How can I get my 2MHz signal phase > > > >locked? > > > > >The idea is this, I have a 2MHz signal coming in on a pin, and I want > > > >to mimic that signal on an internal std_logic pin with the idea that > > > >if the 2MHz signal on the incoming pin is ever lost, the internal > > > >std_logic pin continues the original timing as if nothing has > > > >happened. > > > > >Any suggestions? > > > > Implement your own NCO. Basically run a high resolution counter with > > > high speed clock and detect at which count the 2MHz signal is toggling > > > (both edges if need be) and generate an internal signal at the same > > > count. Now even if the external signal disappears you have the count > > > (phase) already and you can keep generating the internal signal. You > > > can use this internal signal either as a clock source (ie a divided > > > clock) or as an enable to its downstream logic. > > > -- > > > Muzaffer Kal > > > > DSPIA INC. > > > ASIC/FPGA Design Services > > > >http://www.dspia.com > > > as I've been thinking about this today I also thought to forget the > > DCM and just do it with the regular system clock. The main system > > clock will be anywhere between 25-100MHZ, and for that matter, the > > 25MHz can be 4X with the DCM. so now the issue is on the rising edge > > of the inbound 2MHz clock have the internal 2mhz clock count off 50 > > ticks of the 100MHz clock to do my best "phase lock" > > Hi Jonathan, > > I am currently working on the same sort of design. I don't think an > NCO is the entire job. What you need is a phase locked loop with a > mode of holding the last setting when the input clock is lost. To do > this you need an integrator between the phase detector and the NCO > which will accumulate and hold a value to maintain the output > frequency when the input clock is lost. The trick is this is not a > stable circuit and needs other feedback to stabilize it. If you know > anything about DSP, this is not a hard problem to analyze. The > integrator puts a pole on the unit circle at 1,0 which by itself is > not stable. You can add a proportional feedback element to add a zero > which can be placed very close to the pole which will stabilize it for > frequencies other than near DC. But we don't care about being DC > bounded because the feedback loop will compensate for that. > > Rick Sorry what does NCO stand for?Article: 140888
> Sorry what does NCO stand for? > Numerically Controlled Oscillator /MikhailArticle: 140889
On May 15, 7:31=A0pm, Tommy Thorn <tommy.th...@gmail.com> wrote: > On May 11, 1:02=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > > > it will be only short clip in localTV(estonian, kanal-2) in the DIY > > show, but was still funny to look into the camera with FPGA board in th= e > > hands. > > Is there a way to see this clip for non-estonians? > > Thanks, > > Tommy it was only today, and i didnt even know myself.. did not get notice well i dont have a TV set anyway :) i try arrange to get a copy, want to see myself too AnttiArticle: 140890
On May 28, 3:32 pm, doug <x...@xx.com> wrote: > jleslie48 wrote: > > On May 27, 5:43 pm, rickman <gnu...@gmail.com> wrote: > > >>On May 27, 4:10 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > >>>On May 27, 1:33 pm, Muzaffer Kal <k...@dspia.com> wrote: > > >>>>On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 > > >>>><j...@jonathanleslie.com> wrote: > > >>>>>on a spartan 3e, the DCM speaks to havein a high-resolution phase > >>>>>shifting function, but it goes on and says the DCM has a wide > >>>>>frequency range of 5MHz to 300MHz. How can I get my 2MHz signal phase > >>>>>locked? > > >>>>>The idea is this, I have a 2MHz signal coming in on a pin, and I want > >>>>>to mimic that signal on an internal std_logic pin with the idea that > >>>>>if the 2MHz signal on the incoming pin is ever lost, the internal > >>>>>std_logic pin continues the original timing as if nothing has > >>>>>happened. > > >>>>>Any suggestions? > > >>>>Implement your own NCO. Basically run a high resolution counter with > >>>>high speed clock and detect at which count the 2MHz signal is toggling > >>>>(both edges if need be) and generate an internal signal at the same > >>>>count. Now even if the external signal disappears you have the count > >>>>(phase) already and you can keep generating the internal signal. You > >>>>can use this internal signal either as a clock source (ie a divided > >>>>clock) or as an enable to its downstream logic. > >>>>-- > >>>>Muzaffer Kal > > >>>>DSPIA INC. > >>>>ASIC/FPGA Design Services > > >>>>http://www.dspia.com > > >>>as I've been thinking about this today I also thought to forget the > >>>DCM and just do it with the regular system clock. The main system > >>>clock will be anywhere between 25-100MHZ, and for that matter, the > >>>25MHz can be 4X with the DCM. so now the issue is on the rising edge > >>>of the inbound 2MHz clock have the internal 2mhz clock count off 50 > >>>ticks of the 100MHz clock to do my best "phase lock" > > >>Hi Jonathan, > > >>I am currently working on the same sort of design. I don't think an > >>NCO is the entire job. What you need is a phase locked loop with a > >>mode of holding the last setting when the input clock is lost. To do > >>this you need an integrator between the phase detector and the NCO > >>which will accumulate and hold a value to maintain the output > >>frequency when the input clock is lost. The trick is this is not a > >>stable circuit and needs other feedback to stabilize it. If you know > >>anything about DSP, this is not a hard problem to analyze. The > >>integrator puts a pole on the unit circle at 1,0 which by itself is > >>not stable. You can add a proportional feedback element to add a zero > >>which can be placed very close to the pole which will stabilize it for > >>frequencies other than near DC. But we don't care about being DC > >>bounded because the feedback loop will compensate for that. > > >>Rick > > > Sorry what does NCO stand for? > > It is also called a DDS for Direct Digital Synthesizer. Analog devices > makes a family of them. And they are very nice units. Basically they > are a phase accumulator. The frequency output is equal to the clock > frequency times the phase count divided by the counter full scale. > The big advantage is that the step size is constant and is the > clock frequency divided by the counter size. Thus a 24bit counter > and a 16MHz clock gives a step size of 1Hz. Compare this with a > frequency divider where you get an output of f, f/2, f/3 etc. > The downside is that there is some jitter (up to one clock period) > and that makes it difficult to use in some low noise applications. > The commercial devices have a sin ROM and a D/A to give a nice > sine wave output. They are useful in FPGAs where you can track > moving input clocks. Rick's comments above are quite correct in > that you can make a PLL in the fpga digitally. > >Numerically Controlled Oscillator > >/Mikhail Ahh, thanks again all.Article: 140891
On May 28, 9:43=A0am, jleslie48 <j...@jonathanleslie.com> wrote: > On May 27, 4:14 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > On May 27, 12:51 pm, Andy Peters <goo...@latke.net> wrote: > > > > On May 26, 1:13 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > > > 23-architecture arch of fifo is > > > > > > 24- =A0 type reg_file_type is array (2**W-1 downto 0) of > > > > > > 25- =A0 =A0 =A0 =A0std_logic_vector(B-1 downto 0); > > > > > > 26: =A0 signal array_reg: reg_file_type; > > > > > > 27- =A0 signal w_ptr_reg, w_ptr_next, w_ptr_succ: > > > > > > 28- =A0 =A0 =A0std_logic_vector(W-1 downto 0); > > > > > > 29- =A0 signal r_ptr_reg, r_ptr_next, r_ptr_succ: > > > > > > -- > > > > > > 39- =A0 process(clk,reset) > > > > > > 40- =A0 begin > > > > > > 41- =A0 =A0 if (reset=3D'1') then > > > > > > 42: =A0 =A0 =A0 =A0array_reg <=3D (others=3D>(others=3D>'0')); > > > > > > 43- =A0 =A0 elsif (clk'event and clk=3D'1') then > > > > > > 44- =A0 =A0 =A0 =A0if wr_en=3D'1' then > > > > > > 45: =A0 =A0 =A0 =A0 =A0 array_reg(to_integer(unsigned(w_ptr_reg= ))) > > > > > > 46- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 <=3D w_data; > > > > > > 47- =A0 =A0 =A0 =A0end if; > > > > > > 48- =A0 =A0 end if; > > > > > > 49- =A0 end process; > > > > > > 50- =A0 -- read port > > > > > > 51: =A0 r_data <=3D array_reg(to_integer(unsigned(r_ptr_reg))); > > > > > > 52- =A0 -- write enabled only when FIFO is not full > > > > > > 53- =A0 wr_en <=3D wr and (not full_reg); > > > > > > 54- > > > > > > > Ok, so here's all the code pertaining to array_reg, specificall= y lines > > > > > > 42, 45, and 51. =A0From what I can understand, it seems that th= e > > > > > > professionals here are concerned about line 42; the one resulti= ng from > > > > > > the reset signal. =A0What would be the correct way to implement= this > > > > > > concept? > > > > > > Simply delete the asynchronous reset stuff in lines 41 and 42, an= d > > > > > change the "elsif" on line 43 to a simple "if." > > > > > > > In C I would of just done a memset(array_reg, 0, sizeof(array_r= eg)) > > > > > > but we ain't in C world any more... > > > > > > Indeed -- think HARDWARE. > > > > > > Since you are describing a FIFO, there's no need to reset the mem= ory. > > > > > Simply resetting the read and write pointers effectively clears t= he > > > > > memory. You will never read from an empty FIFO and a FIFO write > > > > > guarantees that you read valid data. > > > > > > -a > > > > > quite right, > > > > > the other process has: > > > > =A0 process(clk,reset) > > > > =A0 =A0begin > > > > =A0 =A0 =A0 if (reset=3D'1') then > > > > =A0 =A0 =A0 =A0 =A0w_ptr_reg <=3D (others=3D>'0'); > > > > =A0 =A0 =A0 =A0 =A0r_ptr_reg <=3D (others=3D>'0'); > > > > =A0 =A0 =A0 =A0 =A0full_reg <=3D '0'; > > > > =A0 =A0 =A0 =A0 =A0empty_reg <=3D '1'; > > > > > and as my pointers get reset who cares about the data. =A0System > > > > resources went dramatically down as a result of the changes, > > > > I'm glad the suggestion worked for you! > > > > > however > > > > two warnings are now being generated that were never there before: > > > > > WARNING Route - CLK Net:clk_2mhz is being routed on general routing > > > > resources. If you are trying to use local clocking techniques, > > > > evaluate the placement of the clock's source and loads to ensure it > > > > meets the guidelines for local clocking. Otherwise, consider placin= g > > > > this clock on a dedicated clock routing resource. For more informat= ion > > > > on clock routing resources, see the target architecture's user guid= e. > > > > > WARNING Route - CLK Net:clk_7812hz is being routed on general routi= ng > > > > resources. If you are trying to use local clocking techniques, > > > > evaluate the placement of the clock's source and loads to ensure it > > > > meets the guidelines for local clocking. Otherwise, consider placin= g > > > > this clock on a dedicated clock routing resource. For more informat= ion > > > > on clock routing resources, see the target architecture's user guid= e. > > > > > I can't imagine why these are showing up as a result of "fixing" th= e > > > > other error. > > > > Sounds like the clock signals are coming into the FPGA on non-clock > > > pins. You probably didn't see this error before because the original > > > warnings/complaints were issued by XST (the synthesis tool) and you > > > went no further. Now that the source synthesizes, the place and route > > > tools take over, and the warning you get is issued by the router. > > > > Check your UCF and pin selection. > > > > -a > > > H'mmm, =A0 I checked the place and route report before and after the > > change in code. =A0the Warnings are definitely not there when the 256 > > flip-flop warning is in place. > > > I'll have to take a look at the UCF and see what can be done with the > > pins I'm using. =A0I'm a bit confused about that, I thought GPIO is > > GPIO, I'm sending in a signal, and that's it, but I know that there is > > a document out there from Xilinx (how they love their documents) that > > says something about the pins... =A0lets me check and see what I can > > find. > > OK, so from the UCF I was provided here is the system clock: > > --------------------------------- > #DRIGMORN PACKAGE IS CP132/CPG132 > # > ##################################### > #CLOCK > ##################################### > NET "SYSTEM_CLOCK" LOC =3D "M6"; > ----------------------------------------------------------------- > > And from the DS312.pdf, the 'spartan-3E Fpga family: complete data > sheet' document for the spartan 3E I find this: > > -------------------------------------------------------------------------= --------------- > Table =A0132: =A0CP132 Package Pinout (Continued) > > XC3S250E > Bank =A0 =A0 =A0XC3S100E =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0XC3S500E > =A0 =A0 =A0 =A0 =A0 =A0 =A0Pin Name =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Pin > Name =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0CP132 Ball =A0 =A0 Type > ... > 2 =A0 =A0IP_L05N_2/M2/GCLK1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 IP_L05N_2/M2/GCLK= 1 > N6 =A0 =A0 =A0 =A0 =A0 =A0 =A0DUAL/GCLK > 2 =A0 =A0IP_L05P_2/RDWR_B/GCLK0 =A0 =A0 IP_L05P_2/RDWR_B/GCLK0 > M6 =A0 =A0 =A0 =A0 =A0 =A0 =A0DUAL/GCLK > ... > > DS312-4 (v3.7) April 18, 2008 =A0 =A0 =A0 =A0 =A0 =A0 =A0www.xilinx.com > 175 > Product Specification > > -------------------------------------------------------------------------= --------------- > > so here is how the system clock is defined in the ucf, no attributes > are assigned to the M6 pin, and OK, this is fine -- M6 is a global clock pin (GCLK) and as such when synthesized, the tools should automatically infer an IBUFG for it. But apparently they don't. Does SYSTEM_CLOCK drive any other non-clock resources? > the only attributes at all I see in the whole UCF is: > > NET "RXD" LOC =3D "A7" =A0 =A0| PULLUP; =A0 #INPUT FROM RS232 CHIP > > a PULLUP. > > So now I want a 2MHZ "clock" on some other pin, what is the criteria I > should be looking for in a candidate pin? > is that DUAL/GCLK thing significant, or am I supposed to use some > attribute? =A0For that matter what is the full set of > attributes that is available, is it described in any manual? =A0And > Further, am I even on the right track? =A0Is this even the correct > manual to be looking at for this info??? The family data sheet tells you which pins are to be used for clock inputs: they are GCLK and in some families LHCLK, RHCLK, or CC. "Dual" simply means that the pins have one function during FPGA configuration and another afterwards. So for Spartan 3E simply choose one of the many GCLK pins. I would avoid the pins that also have a configuration function (I think GCLK1 is like that). -aArticle: 140892
jleslie48 wrote: > On May 27, 5:43 pm, rickman <gnu...@gmail.com> wrote: > >>On May 27, 4:10 pm, jleslie48 <j...@jonathanleslie.com> wrote: >> >> >> >> >>>On May 27, 1:33 pm, Muzaffer Kal <k...@dspia.com> wrote: >> >>>>On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 >> >>>><j...@jonathanleslie.com> wrote: >>>> >>>>>on a spartan 3e, the DCM speaks to havein a high-resolution phase >>>>>shifting function, but it goes on and says the DCM has a wide >>>>>frequency range of 5MHz to 300MHz. How can I get my 2MHz signal phase >>>>>locked? >> >>>>>The idea is this, I have a 2MHz signal coming in on a pin, and I want >>>>>to mimic that signal on an internal std_logic pin with the idea that >>>>>if the 2MHz signal on the incoming pin is ever lost, the internal >>>>>std_logic pin continues the original timing as if nothing has >>>>>happened. >> >>>>>Any suggestions? >> >>>>Implement your own NCO. Basically run a high resolution counter with >>>>high speed clock and detect at which count the 2MHz signal is toggling >>>>(both edges if need be) and generate an internal signal at the same >>>>count. Now even if the external signal disappears you have the count >>>>(phase) already and you can keep generating the internal signal. You >>>>can use this internal signal either as a clock source (ie a divided >>>>clock) or as an enable to its downstream logic. >>>>-- >>>>Muzaffer Kal >> >>>>DSPIA INC. >>>>ASIC/FPGA Design Services >> >>>>http://www.dspia.com >> >>>as I've been thinking about this today I also thought to forget the >>>DCM and just do it with the regular system clock. The main system >>>clock will be anywhere between 25-100MHZ, and for that matter, the >>>25MHz can be 4X with the DCM. so now the issue is on the rising edge >>>of the inbound 2MHz clock have the internal 2mhz clock count off 50 >>>ticks of the 100MHz clock to do my best "phase lock" >> >>Hi Jonathan, >> >>I am currently working on the same sort of design. I don't think an >>NCO is the entire job. What you need is a phase locked loop with a >>mode of holding the last setting when the input clock is lost. To do >>this you need an integrator between the phase detector and the NCO >>which will accumulate and hold a value to maintain the output >>frequency when the input clock is lost. The trick is this is not a >>stable circuit and needs other feedback to stabilize it. If you know >>anything about DSP, this is not a hard problem to analyze. The >>integrator puts a pole on the unit circle at 1,0 which by itself is >>not stable. You can add a proportional feedback element to add a zero >>which can be placed very close to the pole which will stabilize it for >>frequencies other than near DC. But we don't care about being DC >>bounded because the feedback loop will compensate for that. >> >>Rick > > > Sorry what does NCO stand for? > It is also called a DDS for Direct Digital Synthesizer. Analog devices makes a family of them. And they are very nice units. Basically they are a phase accumulator. The frequency output is equal to the clock frequency times the phase count divided by the counter full scale. The big advantage is that the step size is constant and is the clock frequency divided by the counter size. Thus a 24bit counter and a 16MHz clock gives a step size of 1Hz. Compare this with a frequency divider where you get an output of f, f/2, f/3 etc. The downside is that there is some jitter (up to one clock period) and that makes it difficult to use in some low noise applications. The commercial devices have a sin ROM and a D/A to give a nice sine wave output. They are useful in FPGAs where you can track moving input clocks. Rick's comments above are quite correct in that you can make a PLL in the fpga digitally.Article: 140893
http://techanalysttalks.blogspot.com In year 2004, ST announced the GOSPL "Generalized Open source programable logic" with a bang. GOSPL is a standard platform for programmable logic driven by an open source tool chain, a complete paradigm shift from the status quo predicted to become the digital DNA of electronics. It was touted as the people's chip with a community of developers woven around it. A lot of universities in the US, Europe and India participated in the project. ST also organized an international conference in New Delhi inviting the global EDA, IP, semiconductor professionals, academia and venture capitalist community from around the globe. This re-programmable, re-usable, system-on-chip was claimed to benefit all the entities of the semiconductor value chain. It was undoubtebly a breakthrough idea for the semiconductor industry and for FPGA industry in particular. ST contributed few million lines of code to the project and put it into public domain. The idea was to bring the competition in the FPGA industry to FPGA silicon instead of FPGA tools. Xilinx and Altera which have more than 90% of the FPGA market share between them, have erected high industry barriers based on their software expertise and silos of software code which is proprietary to them. Putting the FPGA tool code in the public domain and asking the developer community to contribute to it was a major step in challenging the software capablities of Xilinx or Altera. FPGA industry had always been a tough nut to crack even for industry leaders like Intel, Motorola, IBM, Lucent. To everyone's surprise, within a year of the announcement of the project the project was put on hold. ST said that it was redeploying approximately 1,000 engineers, representing 10 percent of ST=92s R&D workforce, from non-core programs, including FPGA and third-party design services, and from CPE modem and GSM chipset activities There was also a speculation that ST may spin off GOSPL in a management buy out, or sell the operation to an FPGA company. Interestingly ST has been part of the Morpheus collobarative research. It has recently compe up with the first prototypes of the Morpheus chip. Chances are high that ST has transformed GOSPL into Morpheus.Article: 140894
On May 28, 3:06 pm, Andy Peters <goo...@latke.net> wrote: > On May 28, 9:43 am, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > On May 27, 4:14 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > On May 27, 12:51 pm, Andy Peters <goo...@latke.net> wrote: > > > > > On May 26, 1:13 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > > > > 23-architecture arch of fifo is > > > > > > > 24- type reg_file_type is array (2**W-1 downto 0) of > > > > > > > 25- std_logic_vector(B-1 downto 0); > > > > > > > 26: signal array_reg: reg_file_type; > > > > > > > 27- signal w_ptr_reg, w_ptr_next, w_ptr_succ: > > > > > > > 28- std_logic_vector(W-1 downto 0); > > > > > > > 29- signal r_ptr_reg, r_ptr_next, r_ptr_succ: > > > > > > > -- > > > > > > > 39- process(clk,reset) > > > > > > > 40- begin > > > > > > > 41- if (reset='1') then > > > > > > > 42: array_reg <= (others=>(others=>'0')); > > > > > > > 43- elsif (clk'event and clk='1') then > > > > > > > 44- if wr_en='1' then > > > > > > > 45: array_reg(to_integer(unsigned(w_ptr_reg))) > > > > > > > 46- <= w_data; > > > > > > > 47- end if; > > > > > > > 48- end if; > > > > > > > 49- end process; > > > > > > > 50- -- read port > > > > > > > 51: r_data <= array_reg(to_integer(unsigned(r_ptr_reg))); > > > > > > > 52- -- write enabled only when FIFO is not full > > > > > > > 53- wr_en <= wr and (not full_reg); > > > > > > > 54- > > > > > > > > Ok, so here's all the code pertaining to array_reg, specifically lines > > > > > > > 42, 45, and 51. From what I can understand, it seems that the > > > > > > > professionals here are concerned about line 42; the one resulting from > > > > > > > the reset signal. What would be the correct way to implement this > > > > > > > concept? > > > > > > > Simply delete the asynchronous reset stuff in lines 41 and 42, and > > > > > > change the "elsif" on line 43 to a simple "if." > > > > > > > > In C I would of just done a memset(array_reg, 0, sizeof(array_reg)) > > > > > > > but we ain't in C world any more... > > > > > > > Indeed -- think HARDWARE. > > > > > > > Since you are describing a FIFO, there's no need to reset the memory. > > > > > > Simply resetting the read and write pointers effectively clears the > > > > > > memory. You will never read from an empty FIFO and a FIFO write > > > > > > guarantees that you read valid data. > > > > > > > -a > > > > > > quite right, > > > > > > the other process has: > > > > > process(clk,reset) > > > > > begin > > > > > if (reset='1') then > > > > > w_ptr_reg <= (others=>'0'); > > > > > r_ptr_reg <= (others=>'0'); > > > > > full_reg <= '0'; > > > > > empty_reg <= '1'; > > > > > > and as my pointers get reset who cares about the data. System > > > > > resources went dramatically down as a result of the changes, > > > > > I'm glad the suggestion worked for you! > > > > > > however > > > > > two warnings are now being generated that were never there before: > > > > > > WARNING Route - CLK Net:clk_2mhz is being routed on general routing > > > > > resources. If you are trying to use local clocking techniques, > > > > > evaluate the placement of the clock's source and loads to ensure it > > > > > meets the guidelines for local clocking. Otherwise, consider placing > > > > > this clock on a dedicated clock routing resource. For more information > > > > > on clock routing resources, see the target architecture's user guide. > > > > > > WARNING Route - CLK Net:clk_7812hz is being routed on general routing > > > > > resources. If you are trying to use local clocking techniques, > > > > > evaluate the placement of the clock's source and loads to ensure it > > > > > meets the guidelines for local clocking. Otherwise, consider placing > > > > > this clock on a dedicated clock routing resource. For more information > > > > > on clock routing resources, see the target architecture's user guide. > > > > > > I can't imagine why these are showing up as a result of "fixing" the > > > > > other error. > > > > > Sounds like the clock signals are coming into the FPGA on non-clock > > > > pins. You probably didn't see this error before because the original > > > > warnings/complaints were issued by XST (the synthesis tool) and you > > > > went no further. Now that the source synthesizes, the place and route > > > > tools take over, and the warning you get is issued by the router. > > > > > Check your UCF and pin selection. > > > > > -a > > > > H'mmm, I checked the place and route report before and after the > > > change in code. the Warnings are definitely not there when the 256 > > > flip-flop warning is in place. > > > > I'll have to take a look at the UCF and see what can be done with the > > > pins I'm using. I'm a bit confused about that, I thought GPIO is > > > GPIO, I'm sending in a signal, and that's it, but I know that there is > > > a document out there from Xilinx (how they love their documents) that > > > says something about the pins... lets me check and see what I can > > > find. > > > OK, so from the UCF I was provided here is the system clock: > > > --------------------------------- > > #DRIGMORN PACKAGE IS CP132/CPG132 > > # > > ##################################### > > #CLOCK > > ##################################### > > NET "SYSTEM_CLOCK" LOC = "M6"; > > ----------------------------------------------------------------- > > > And from the DS312.pdf, the 'spartan-3E Fpga family: complete data > > sheet' document for the spartan 3E I find this: > > > ---------------------------------------------------------------------------------------- > > Table 132: CP132 Package Pinout (Continued) > > > XC3S250E > > Bank XC3S100E XC3S500E > > Pin Name Pin > > Name CP132 Ball Type > > ... > > 2 IP_L05N_2/M2/GCLK1 IP_L05N_2/M2/GCLK1 > > N6 DUAL/GCLK > > 2 IP_L05P_2/RDWR_B/GCLK0 IP_L05P_2/RDWR_B/GCLK0 > > M6 DUAL/GCLK > > ... > > > DS312-4 (v3.7) April 18, 2008 www.xilinx.com > > 175 > > Product Specification > > > ---------------------------------------------------------------------------------------- > > > so here is how the system clock is defined in the ucf, no attributes > > are assigned to the M6 pin, and > > OK, this is fine -- M6 is a global clock pin (GCLK) and as such when > synthesized, the tools should automatically infer an IBUFG for it. But > apparently they don't. Does SYSTEM_CLOCK drive any other non-clock > resources? > > > the only attributes at all I see in the whole UCF is: > > > NET "RXD" LOC = "A7" | PULLUP; #INPUT FROM RS232 CHIP > > > a PULLUP. > > > So now I want a 2MHZ "clock" on some other pin, what is the criteria I > > should be looking for in a candidate pin? > > is that DUAL/GCLK thing significant, or am I supposed to use some > > attribute? For that matter what is the full set of > > attributes that is available, is it described in any manual? And > > Further, am I even on the right track? Is this even the correct > > manual to be looking at for this info??? > > The family data sheet tells you which pins are to be used for clock > inputs: they are GCLK and in some families LHCLK, RHCLK, or CC. "Dual" > simply means that the pins have one function during FPGA configuration > and another afterwards. > > So for Spartan 3E simply choose one of the many GCLK pins. I would > avoid the pins that also have a configuration function (I think GCLK1 > is like that). > > -a OK, so I'm looking at the correct thing to fix my warning? My place and route is complaining that clk_78122hz is being routed on general routing resources. my use of clk_7812hz is: -- JB_Top.vhd:351: signal clk_7812hz : std_logic := '0'; -- this is the clock for the 128uS period,its actally 7812.5hz JB_Top.vhd-361- -- JB_Top.vhd-443-clock_7812hz: PROCESS ( system_clock_used ) JB_Top.vhd-444-BEGIN JB_Top.vhd-445- IF ( rising_edge(system_clock_used)) then JB_Top.vhd:446: IF ( clk_7812hz_countdown = 0) THEN JB_Top.vhd:447: clk_7812hz_countdown <= clk_7812hz_clock_count; JB_Top.vhd:448: --clk_7812hz_countdown <= 6399; -- base clock choice JB_Top.vhd:449: clk_7812hz <= NOT clk_7812hz; JB_Top.vhd:450: if (clk_7812hz = '0') Then JB_Top.vhd:451: clk_7812hz_tick <= '1'; JB_Top.vhd-452- end if; JB_Top.vhd-453- else JB_Top.vhd:454: clk_7812hz_tick <= '0'; JB_Top.vhd:455: clk_7812hz_countdown <= clk_7812hz_countdown -1; JB_Top.vhd-456- End if; -- countdown ife JB_Top.vhd-457- JB_Top.vhd-458- END IF; JB_Top.vhd-459-END PROCESS clock_7812hz; JB_Top.vhd-460- JB_Top.vhd-461- JB_Top.vhd:462:clock_7812_ctr: PROCESS ( clk_7812hz ) JB_Top.vhd-463-BEGIN JB_Top.vhd:464: IF ( rising_edge(clk_7812hz)) then JB_Top.vhd-465- time_cntr_128us <= time_cntr_128us +1; JB_Top.vhd-466- uptime_at_128us <= time_cntr_500ns; JB_Top.vhd-467- -- JB_Top.vhd-506- JB_Top.vhd-507- JB_Top.vhd-508--- this clock is not uart related JB_Top.vhd:509:clock_20s: PROCESS ( clk_7812hz ) JB_Top.vhd-510-BEGIN JB_Top.vhd:511: IF ( rising_edge(clk_7812hz)) then JB_Top.vhd-512- IF ( clk_20s_countdown = 0) THEN JB_Top.vhd-513- clk_20s_countdown <= 78_125; JB_Top.vhd-514- clk_20s <= NOT clk_20s; What's the issue? its not even going on an output pin.Article: 140895
On May 28, 2:59=A0pm, jleslie48 <j...@jonathanleslie.com> wrote: > On May 28, 3:32 pm, doug <x...@xx.com> wrote: > > > > > jleslie48 wrote: > > > On May 27, 5:43 pm, rickman <gnu...@gmail.com> wrote: > > > >>On May 27, 4:10 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > >>>On May 27, 1:33 pm, Muzaffer Kal <k...@dspia.com> wrote: > > > >>>>On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 > > > >>>><j...@jonathanleslie.com> wrote: > > > >>>>>on a spartan 3e, the DCM speaks to havein a high-resolution phase > > >>>>>shifting function, but it goes on and says the DCM has a wide > > >>>>>frequency range of 5MHz to 300MHz. =A0How can I get my 2MHz signal= phase > > >>>>>locked? > > > >>>>>The idea is this, I have a 2MHz signal coming in on a pin, and I w= ant > > >>>>>to mimic that signal on an internal std_logic pin with the idea th= at > > >>>>>if the 2MHz signal on the incoming pin is ever lost, the internal > > >>>>>std_logic pin continues the original timing as if nothing has > > >>>>>happened. > > > >>>>>Any suggestions? > > > >>>>Implement your own NCO. Basically run a high resolution counter wit= h > > >>>>high speed clock and detect at which count the 2MHz signal is toggl= ing > > >>>>(both edges if need be) and generate an internal signal at the same > > >>>>count. Now even if the external signal disappears you have the coun= t > > >>>>(phase) already and you can keep generating the internal signal. Yo= u > > >>>>can use this internal signal either as a clock source (ie a divided > > >>>>clock) or as an enable to its downstream logic. > > >>>>-- > > >>>>Muzaffer Kal > > > >>>>DSPIA INC. > > >>>>ASIC/FPGA Design Services > > > >>>>http://www.dspia.com > > > >>>as I've been thinking about this today I also thought to forget the > > >>>DCM and just do it with the regular system clock. =A0The main system > > >>>clock will be anywhere between 25-100MHZ, and for that matter, the > > >>>25MHz can be 4X with the DCM. =A0so now the issue is on the rising e= dge > > >>>of the inbound 2MHz clock have the internal 2mhz clock count off 50 > > >>>ticks of the 100MHz clock to do my best "phase lock" > > > >>Hi Jonathan, > > > >>I am currently working on the same sort of design. =A0I don't think a= n > > >>NCO is the entire job. =A0What you need is a phase locked loop with a > > >>mode of holding the last setting when the input clock is lost. =A0To = do > > >>this you need an integrator between the phase detector and the NCO > > >>which will accumulate and hold a value to maintain the output > > >>frequency when the input clock is lost. =A0The trick is this is not a > > >>stable circuit and needs other feedback to stabilize it. =A0If you kn= ow > > >>anything about DSP, this is not a hard problem to analyze. =A0The > > >>integrator puts a pole on the unit circle at 1,0 which by itself is > > >>not stable. =A0You can add a proportional feedback element to add a z= ero > > >>which can be placed very close to the pole which will stabilize it fo= r > > >>frequencies other than near DC. =A0But we don't care about being DC > > >>bounded because the feedback loop will compensate for that. > > > >>Rick > > > > Sorry what does NCO stand for? > > > It is also called a DDS for Direct Digital Synthesizer. =A0Analog devic= es > > makes a family of them. And they are very nice units. Basically they > > are a phase accumulator. =A0The frequency output is equal to the clock > > frequency times the phase count divided by the counter full scale. > > The big advantage is that the step size is constant and is the > > clock frequency divided by the counter size. =A0Thus a 24bit counter > > and a 16MHz clock gives a step size of 1Hz. =A0Compare this with a > > frequency divider where you get an output of f, f/2, f/3 etc. > > The downside is that there is some jitter (up to one clock period) > > and that makes it difficult to use in some low noise applications. > > The commercial devices have a sin ROM and a D/A to give a nice > > sine wave output. They are useful in FPGAs where you can track > > moving input clocks. Rick's comments above are quite correct in > > that you can make a PLL in the fpga digitally. > > >Numerically Controlled Oscillator > > >/Mikhail > > Ahh, thanks again all. By the way, since I didn't see anyone else pointing this out, the DCM would not have worked for this as it doesn't have an oscillator, only delay lines. So in the DCM case no input translates into no output. Regards, GaborArticle: 140896
I am putting together a small board with two programmable logic devices ( XC2C64A and XC3S100 ) in a daisy chain configuration. I am trying to set up a slave parallel programming solution through an FTDI FT245RL and am wondering about ISE and its ability to identify the two devices through this configuration. Specifically, does the FTDI driver make the USB channel transparent to the ISE? I am needing some documentation in setting up this chain. I have looked over the schematics for Digilent's XC3S700AN starter kit, but schematics do not show the USB chain for programming the FPGA. Having done an amount of programming on the starter kit and the response in this forum that chain seems flaky with ISE. Have done some reading in XAPP502 but the USB channel has me a bit nervous. Any help would be appreciated. Sincerely, Cy Drollinger Electronic Realization L.L.C. Bozeman, MTArticle: 140897
David Antliff wrote: > On May 22, 2:30Â am, phil hays <philh...@dont.spam> wrote: ... >> To difference the .bit files, the header needs to be ignored. To make >> this automatic, I've written a little difference utility using Tcl. >> Would this be of interest? > > Yes, this would be useful please. I've created a webpage with a link to this script. I lost the original, so I had to write a new script with the same function. http://mysite.verizon.net/res12uj6d/ -- Phil Hays (phil_hays at eeei.gro (fix the order for email)Article: 140898
On May 29, 12:24=A0pm, phil hays <philh...@dont.spam> wrote: > I've created a webpage with a link to this script. I lost the original, > so I had to write a new script with the same function. > > http://mysite.verizon.net/res12uj6d/ Great, thank you very much for writing and posting this. Regards, -- David.Article: 140899
Sound advice. Processes should be separate only for separate functional parts. Splitting action into multiple case statements also causes errors of logic. 'Inferred latches for signal' is quite a strange phrase, maybe 'possible forgotten signal assignment' would be better. It only seems to be if ... then ... else ... end if; which generates inferred latches. case and if ... then ... end if; does not seem to. I guess this is because no else is definite latch/register, and case can contain many places of non assignment and so could flood the message display. It's not that strange really. cheers jacko http://nibz.googlecode.com version T much easier to read code. final version for a while.
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