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On Wed, 03 Jun 2009 13:11:59 -0500, "maxascent" <maxascent@yahoo.co.uk> wrote: >How would I create a create a secure netlist that I could give to a 3rd >party. Ideally I would like the edif output from Synplify but in a >protected form. What do you want the 3rd party to be able to do with this netlist? If you need them to be able to use it in any form other than storing it, you need to encyrpt it with the tool which will be used in that process. Ie, if you want them to be able to simulate it, you encrypt it with the target simulator so only that simulator can un-encrypt it. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 141051
Hi,
Bond wrote:
> I have to use the
> formula A=(t1/t2-50)/12.5. can a hardware module process this kind of
> formula or it should be left for microblaze.
the formula is not perfectly clear but I can infer a few things from past readings,
particularly from the ever inspiring DSP litterature.
The "/12.5" is clearly coming from a power of two, just do the maths :
*1 /1
*2 /(1/2)=/0.5
*4 /(1/4)=/0.25
*8 /(1/8)=/0.125
so if you divide by 0.125, you multiply by 8
Since you divide by 12.5, you actually use another 100x factor.
now : when you multiply by 8, you add 3 LSB (you add no information, these LSB remain zeroed).
For the 100x factor, you can "scale" the whole algorithm with this factor.
That is : the 100x multiply is only done by a display interface (just move the decimal point
when you printf() it).
This means that you don't need to perform the /12.5 division at all in VHDL.
Also, look at Digital Signal Processing sites and books, because
this domain uses a lot of "fixed point" binary representation
(you clearly don't need floating point numbers here !)
Now, the "-50" term is unclear.
It is either the data that was sampled 50ms ago, or a "magic constant"...
This kind of division may be handled with a multi-cycle Newton-Raphson technique,
which uses multiplies and add/sub operators.
Or you can use a simple 1-bit-per-cycle divider if speed allows it, and space is constrained
(probably the best solution).
BTW, beware of the obvious case of x/0...
> prashanta
yg
--
http://ygdes.com / http://yasep.org
Article: 141052On Wed, 03 Jun 2009 14:11:28 -0400, MM wrote: > "Allan Herriman" <allanherriman@hotmail.com> wrote in message > news:004237cd$0$9747$c3e8da3@news.astraweb.com... >> >> The Xilinx license is more flexible though - you can get a node locked >> license and run multiple concurrent instances of the software on that >> machine. > > Do you know if the same can be done with a floating license, i.e. > running multiple instances on a single machine with a single license? I do not know whether this is possible with a floating license, sorry. Regards, AllanArticle: 141053
On May 21, 6:06=A0am, Tommy Thorn <tommy.th...@gmail.com> wrote: > On May 18, 5:06=A0pm, DH <dh1...@gmail.com> wrote: > > > Hi, thanks to everyone that replied to this post! I really appreciate > > it. > > > To Antti: Thanks, the YARI processor looks like a good processor. > > Why thank you :-) > > > Update: After some discussion at school, I'm going > > to use the CoWare processor designer at school to make my processor > > now, it provides a reference 5 stage pipelined RISC core with > > bypassing done already, it's not MIPS, but there's compiler/assembler/ > > linker available. The best thing about this tool (though may be hard > > to do, we'll see) is that you can use it to generate the tool chain > > along with the processor RTL code. I will fall back to good old VHDL > > if this tool doesn't deliver, thanks to everyone that replied to this > > post! > > Good luck with that. If you change your mind and want to give YARI a > spin, I can help you. > > It might be useful to know how your core will be used. Fx. will it be > backed up with external memory or used as an embedded processor using > only the FPGA provided memory blocks? Which parts of the processor are > you planning on experimenting with? > > Cheers, > Tommy Hi Tommy, sorry for the late response, thanks for the offer :) my experimentation is going to use FPGA's internal RAM, and with Altera DE2 being my dev board, I have to deal with the synchronous RAM issue some designs I found to have (they use async ram). I'm experimenting with splitting the RISC pipeline into two pipelined parts, with each responsible for different instructions from the original RISC's instruction set. So for example if original ISA have 4 instructions A B C D, A and B are on the first pipeline, C and D are on the second pipeline. This is why I need to look for a processor with a 5 stage pipeline. I actually have a 5 stage pipelined processor and have modified it to work with my supplemental pipeline, now I need to consider the compilation issues... a rather large task IMHO... Regards, David.Article: 141054
On Jun 3, 6:09=A0pm, "MM" <mb...@yahoo.com> wrote: > Is your top level design in ISE or EDK? Can you post your system.mhs file= ? > > /Mikhail AFAIK, the top level desing is in ISE. The MHS file is OK, it seems to reflect changes I've done in XPS'. # Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build EDK_K_SP3.6 PORT fpga_0_RS232_RX_pin =3D fpga_0_RS232_RX, DIR =3D I PORT fpga_0_RS232_TX_pin =3D fpga_0_RS232_TX, DIR =3D O # (...) # #CLOCKS PORT CLK_200_MHz =3D DDR2_SDRAM_16Mx32_mpmc_clk_s, DIR =3D O, SIGIS =3D Cl= k PORT CLK_166_MHz =3D DDR2_SDRAM_32Mx64_clk_s, DIR =3D O, SIGIS =3D Clk PORT JP2KE_clk_pin =3D jp2k_clk_s, DIR =3D O, SIGIS =3D CLK PORT fsl2dvi_jp2kes2fsl_0_odck_rx_pin =3D fsl2dvi_jp2kes2fsl_0_odck_rx, DIR =3D O, SIGIS =3D Clk # (...) BEGIN clock_generator PARAMETER INSTANCE =3D clock_generator_0 PARAMETER HW_VER =3D 2.01.a PARAMETER C_EXT_RESET_HIGH =3D 1 PARAMETER C_CLKIN_FREQ =3D 100000000 PARAMETER C_CLKOUT0_FREQ =3D 100000000 PARAMETER C_CLKOUT0_BUF =3D TRUE PARAMETER C_CLKOUT0_PHASE =3D 0 PARAMETER C_CLKOUT0_GROUP =3D NONE PARAMETER C_CLKOUT1_FREQ =3D 200000000 PARAMETER C_CLKOUT1_BUF =3D TRUE PARAMETER C_CLKOUT1_PHASE =3D 0 PARAMETER C_CLKOUT1_GROUP =3D PLL0 PARAMETER C_CLKOUT2_FREQ =3D 200000000 PARAMETER C_CLKOUT2_BUF =3D TRUE PARAMETER C_CLKOUT2_PHASE =3D 90 PARAMETER C_CLKOUT2_GROUP =3D PLL0 PARAMETER C_CLKIN_BUF =3D FALSE PARAMETER C_CLKOUT3_FREQ =3D 50000000 PARAMETER C_CLKOUT3_PHASE =3D 0 PARAMETER C_CLKOUT3_GROUP =3D NONE PARAMETER C_CLKOUT3_BUF =3D TRUE PARAMETER C_CLKOUT4_FREQ =3D 166666667 PARAMETER C_CLKOUT4_PHASE =3D 0 PARAMETER C_CLKOUT4_GROUP =3D NONE PARAMETER C_CLKOUT4_BUF =3D TRUE PARAMETER C_CLKOUT5_FREQ =3D 100000000 PARAMETER C_CLKOUT5_PHASE =3D 0 PARAMETER C_CLKOUT5_GROUP =3D NONE PARAMETER C_CLKOUT5_BUF =3D TRUE PORT CLKOUT0 =3D sys_clk_s PORT CLKOUT1 =3D DDR2_SDRAM_16Mx32_mpmc_clk_s PORT CLKOUT2 =3D DDR2_SDRAM_16Mx32_mpmc_clk_90_s PORT CLKIN =3D dcm_clk_s PORT LOCKED =3D Dcm_all_locked PORT RST =3D net_gnd PORT CLKOUT3 =3D DVI_clk_s PORT CLKOUT4 =3D DDR2_SDRAM_32Mx64_clk_s PORT CLKOUT5 =3D jp2k_clk_s END # (...) As I "view RTL schematic" in ISE, I can see that CLKOUT5 is not connected, and JP2KE_clk_pin is fed with sys_clk_s (as it was in the previous version of the project). It is interesting because previously I could see correct connections in the RTL viewer, and the only problem (which still exists now) was no ability to add a constraint for the jp2k_clk_s signal. The only explanation I can imagine is that the project file(s) became somehow corrupted, but I feel nervous when I think about building the entire system again from scratch. The reason for this hipothesis is the fact that my ISE very often gives a "fatal error" unexpectedly and closes. /martenoArticle: 141055
Hi, I have an interesting idea/wish and wonder if anyone has had the same and found a way to solve it. I often work away from the physical hardware I am playing with and more recently I've been having a pain trying to find the best way to do debugging. I have a Linux machine at the lab, with usb and parallel jtag pods on it, hooked up to the hardware. For downloading bit streams I usually scp them to that machine, and then using VNC or ssh I fire up impact and use that machine to flash the fpgas. Now, I also use Identify when things are not quite working as I expect, and this is a pain to use like that, as it requires the whole design to be copied over to the machine, and that take way to long over DSL. I know Impact can run as a server, and I have used that pretty often to remote flash things. I also notice from digging into the Identify directory ( identify/CseJtag/bin/lin) that it seems to use a core set of Impact libraries... and I am sure you can guess my thinking here.. Is it possible to get Identify to also use the remote Impact?? Or would that require way to much forward thinking by the Tool makers... The second solution I thought of was "USB over IP" there are drivers for this in latest linux, but they seem to fall over with the Xilinx POD, it gets reset often, falls off the bus and then the tools loose connection.. Ideas are welcome... -- /\/\arc Kelly ..Just your average physicist trying to get by in a world full of normal people...Article: 141056
What I would like is the 3rd party top be able to use the netlist in their design and then place and route it. I know that xilinx do it with their encrypted NGC file. JonArticle: 141057
Hi We've run into a problem where we get all zeros out of our filter (simple low-pass filter inside an IF sampler) in hardware. RDY behaves as expected, thus it seems like the coefficients (mif) file is not loaded during implementation or something else causes the coefficients to be all zeros in hardware. In simulation the design works as expected. Any ideas would be much appreciated? JacoArticle: 141058
On 4 June, 12:29, Jaco Naude <naude.j...@gmail.com> wrote: > Hi > > We've run into a problem where we get all zeros out of our filter > (simple low-pass filter inside an IF sampler) in hardware. RDY behaves > as expected, thus it seems like the coefficients (mif) file is not > loaded during implementation or something else causes the coefficients > to be all zeros in hardware. > > In simulation the design works as expected. > > Any ideas would be much appreciated? > Jaco Have you tried a post P&R simulation? Are you sure it's the coefficients and not the input that is the problem? JonArticle: 141059
Hi everyone,
I cannot simulate a simple AND Gate
the original project:
I have downloaded the AND gate VHDL to a CPLD and it works file
without adding extra bits to simulate.
You create the ucf file and download to the CPLD and then real time
I've tested the out put and it works fine
I am getting to the AND gate project becuase I am having problem
simulating bigger VHDL code. trying to understand the basic.
When I simulate in ISim from 11.1 suite, I went step by step and I
figured out the simulation only run through the code outputC <=
inputA and inputB; only once.
So I added a SEQ and simulater again and this time it does do back to
the VHDL file and run outputC <= inputA and inputB; every time the
clk rising
the problem I have now is I cannot simulate a simple AND Gate in Isim
look at the tb file I have create when inputA is like the clock,
inputB is high always, but outputC is dead
Could you please help??? Thanks
This is the original project
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MyANDGate is
Port (inputA : in STD_LOGIC;
inputB : in STD_LOGIC;
outputC : out STD_LOGIC);
end MyANDGate;
architecture Behavioral of MyANDGate is
begin
outputC <= inputA and inputB;
end Behavioral;
______________________________________________________
Adding bit for simulation
VHDL file
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MyANDGate is
Port ( clk : in STD_LOGIC; -- simulation purpose only
inputA : in STD_LOGIC;
inputB : in STD_LOGIC;
outputC : out STD_LOGIC);
end MyANDGate;
architecture Behavioral of MyANDGate is
begin
SEQ: process(clk)
begin
if (clk'event and clk = '1') then
outputC <= inputA and inputB;
end if;
end process SEQ;
end Behavioral;
_______________________________________________________________
the tb file
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY MyANDGate_tb IS
END MyANDGate_tb;
ARCHITECTURE behavior OF MyANDGate_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MyANDGate
PORT(
clk : in std_logic;
inputA : IN std_logic;
inputB : IN std_logic;
outputC : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal inputA : std_logic := '0';
signal inputB : std_logic := '1';
--Outputs
signal outputC : std_logic;
constant clk_period : time := 0.5425347us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MyANDGate PORT MAP (
clk => clk,
inputA => inputA,
inputB => inputB,
outputC => outputC
);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
clk_process :process
begin
clk <= '0';
inputA <= '0';
wait for clk_period/2;
clk <= '1';
inputA <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100ms.
wait for 100ms;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
Article: 141060Hi! I'm a beginner and I have an assignment to design 4 bit adder using FPGA (I have a kit xsa-3s1000 board on Xstend 3.0). I'm using ISE Webpack 10.1 version. I designed the adder with two 4-bit and 1-bit carry-in inputs and 4-bit and 1-bit carry-out outputs... Now I need to connect it to two LED 7-segment displays in order to display the result of the sum. I figured that I need two decoders for each LED display...I know how to write code for the decoder, for example for 3-to-7 decoder: s<="0110000" when d="001" else ; --one input d and one output .. but in my project I need a decoder with 2 inputs and 1 output... Could anyone help please? Thank you!Article: 141061
Hi, I am trying to develop a simple code to use in 8051s core. Using softconsole I had the ihx code file. But I am not sure how to load it. I am using RAM for code memory. I had made 8051s core & connected to code ram,xdata ram using mux. But from actel site not getting help to load ihx file to code RAM. Pl. Help BiswarupArticle: 141062
>Heinz, Marvell's 88E1111 device supports SGMII to MII conversion. Apart from this there are IP core available with Lattice and Xilinx for SGMII to MII conversion. Regards, Veera >Hello >is something like Serial Gigabit Media Independent Interface (SGMII) to >Media Independent Interface (MII) available somewhere? I have to use A SGMII >connected Gigabit PHY with a Standard Fast Ethernet MAC using MII. > >Thanks for any help > > Heinz > >Article: 141063
Hi! I have just started using Xilinx ISE 11. I have made a schematic. Everything works fine and I have written the file to my CPLD. But problem is that the I/O marker names that I specify in the schematic change when it generates the CODE and I see different pin names in the PlanAhead. Is it possible that the names of I/O markers donot change. Thanks alotArticle: 141064
I want to write data to a register in the FPGA via jtag. I use the
BSCAN_VIRTEX4 and write a tcl to write the data. But it did not work. This
is the first time that I use the tcl and jtag. I don't know why? The
promblem is the tcl part or the verilog part? The following is my code, I
want to write data to the "mux_reg".
module jtag(
output wire o_tdo);
reg[2:0] mux_reg;
wire rst;
wire shift;
wire clk;
wire tdi;
BSCAN_VIRTEX4 #(
.JTAG_CHAIN(3))
BSCAN_VIRTEX_inst (
.CAPTURE(),
.DRCK(clk), // Data register output for USER functions
.RESET(rst), // Reset output from TAP controller
.SEL(),
.SHIFT(shift), // SHIFT output from TAP controller
.TDI(tdi), // TDI output from TAP controller
.UPDATE(),
.TDO(o_tdo) // Data input for USER function
);
always @(posedge clk or posedge rst)
if(rst)
mux_reg <= 3'b000;
else if(shift)
mux_reg <= {mux_reg[1:0],tdi};
assign o_tdo = mux_reg[2];
endmodule
tcl:
source csejtag.tcl
source csejtagglobals.tcl
::chipscope::csejtag_session create messageRouterFn
::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_AUTO 0
::chipscope::csejtag_target lock $handle 1000
::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT
set hextdobuf [::chipscope::csejtag_tap shift_device_dr $handle 0
$CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 3 “101”]
::chipscope::csejtag_target unlock $handle
::chipscope::csejtag_target close $handle
Article: 141065On Tue, 2 Jun 2009 17:29:33 +0000 (UTC), jhallen@TheWorld.com (Joseph H Allen) wrote: >In article <CZcVl.51777$Xo1.33938@en-nntp-07.dc1.easynews.com>, >Joel Koltner <zapwireDASHgroups@yahoo.com> wrote: > >>VPI stands for "Value Probe Initiative," and there was a bit of a = running joke=20 >>about how much of that "value" was for the end-user vs. Tektronix. :-) > >Hmm.. this might be the problem: US Patent 4708661, Nov. 24 1987. = "Modified >BNC Connector for Active Probe". It looks like the TekProbe patent ran = out. > >The new patent is: D566047 (Apr 2008). Claim: "The ornamental design of= a >plug for accessory-host interface, as shown and described." > >So there is no technical advantage, it's just an ornamental design which >is patented that so nobody can copy it. Nice. Aha. Snarketing.Article: 141066
"PeterUK" <mastermaster01@hotmail.com> wrote in message news:StudnRzdVa7RXLrXnZ2dnUVZ_uednZ2d@giganews.com... > the problem I have now is I cannot simulate a simple AND Gate in Isim > look at the tb file I have create when inputA is like the clock, > inputB is high always, but outputC is dead ... > -- Stimulus process > stim_proc: process > begin > -- hold reset state for 100ms. > wait for 100ms; > > wait for clk_period*10; > > -- insert stimulus here It simulated correctly. I would call it a success and move on. Add a clk if you want it to toggle.Article: 141067
On 4 June, 15:43, "Biswarup" <biswa...@stoneindia.co.in> wrote: > Hi, > > I am trying to develop a simple code to use in 8051s core. Using > softconsole I had the ihx code file. But I am not sure how to load it. I am > using RAM for code memory. I had made 8051s core & connected to code > ram,xdata ram using mux. But from actel site not getting help to load ihx > file to code RAM. > Pl. Help > > Biswarup http://antti-brain.googlegroups.com/web/AnttiBrain_Issue10_MAY2009.pdf?hl=en look pages 4 and 7 there is soft processor in Actel FPGA, it not 8051s based (doesnt fit into A3P060) but we had same problem - Actel FPGAs (except fusion) do not have "initialized rom" so there is NO way to automatically put any code into the RAMs you have connected to the 8051s, the only way is the same as we did, use very small ROM bootstrap that loads from external serial flash or other media the rom can be either made from versatiles, or then use the 128 byte flash rom as we did AnttiArticle: 141068
Marteno, It sounds as you need to clean your project. Unfortunately, Xilinx tools aren't reliable in detecting design changes. There are several ways of doing this. You can do it from ISE Project menu, or you could clean hardware from the EDK Hardware menu first just to be sure. You could also manually delete relevant (system.ncd, clock_generator.ncd ) or simply all ncd files from the directory tree. Note that there is a cache directory where EDK stores copies of ncd files. /MikhailArticle: 141069
>Hi! I'm a beginner and I have an assignment to design 4 bit adder using >FPGA (I have a kit xsa-3s1000 board on Xstend 3.0). I'm using ISE Webpack >10.1 version. >I designed the adder with two 4-bit and 1-bit carry-in inputs and 4-bit >and 1-bit carry-out outputs... >Now I need to connect it to two LED 7-segment displays in order to display >the result of the sum. >I figured that I need two decoders for each LED display...I know how to >write code for the decoder, for example for 3-to-7 decoder: >s<="0110000" when d="001" else ; --one input d and one output >.. >but in my project I need a decoder with 2 inputs and 1 output... >Could anyone help please? >Thank you! > > > I figured it out a week ago already:) I took a while for the admin to post my thread!!Article: 141070
On Jun 3, 11:11=A0am, "MM" <mb...@yahoo.com> wrote: > "Allan Herriman" <allanherri...@hotmail.com> wrote in message > > news:004237cd$0$9747$c3e8da3@news.astraweb.com... > > > > > The Xilinx license is more flexible though - you can get a node locked > > license and run multiple concurrent instances of the software on that > > machine. > > Do you know if the same can be done with a floating license, i.e. running > multiple instances on a single machine with a single license? > > /Mikhail The FlexLM floating license server checks the user count in the license file. Once "user count" licenses have been checked out, it will not allow another check out to ANY machine. ALArticle: 141071
On 4 June, 13:43, "haowen" <wild...@msn.com> wrote:
> I want to write data to a register in the FPGA via jtag. I use the
> BSCAN_VIRTEX4 and write a tcl to write the data. But it did not work. Thi=
s
> is the first time that I use the tcl and jtag. I don't know why? =A0The
> promblem is the tcl part or the verilog part? =A0The following is my code=
, I
> want to write data to the "mux_reg".
>
> module jtag(
>
> =A0 =A0 output wire o_tdo);
>
> reg[2:0] mux_reg;
> wire =A0 =A0 rst;
> wire =A0 =A0 shift;
> wire =A0 =A0 clk;
> wire =A0 =A0 tdi;
>
> BSCAN_VIRTEX4 #(
> =A0 =A0 =A0 .JTAG_CHAIN(3))
> BSCAN_VIRTEX_inst (
> =A0 =A0 =A0 .CAPTURE(),
> =A0 =A0 =A0 .DRCK(clk), =A0 =A0 =A0// Data register output for USER =A0fu=
nctions
>
> =A0 =A0 =A0 .RESET(rst), =A0 =A0 // Reset output from TAP controller
> =A0 =A0 =A0 .SEL(), =A0 =A0 =A0 =A0 =A0 =A0 =A0
> =A0 =A0 =A0 .SHIFT(shift), =A0 =A0 // SHIFT output from TAP controller
> =A0 =A0 =A0 .TDI(tdi), =A0 =A0 =A0 =A0 =A0 =A0 // TDI output from TAP con=
troller
> =A0 =A0 =A0 .UPDATE(), =A0 =A0 =A0
> =A0 =A0 =A0 .TDO(o_tdo) =A0 =A0 =A0 // Data input for USER function
>
> =A0 =A0);
>
> always @(posedge clk or posedge rst)
> =A0 =A0 =A0 =A0if(rst)
> =A0 =A0 =A0mux_reg <=3D 3'b000;
> =A0 =A0else if(shift)
> =A0 =A0 =A0 =A0 =A0 mux_reg <=3D {mux_reg[1:0],tdi};
>
> assign o_tdo =3D mux_reg[2];
>
> endmodule
>
> tcl:
>
> source csejtag.tcl
> source csejtagglobals.tcl
>
> ::chipscope::csejtag_session create messageRouterFn
>
> ::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_AUTO 0
> ::chipscope::csejtag_target lock $handle 1000
> ::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT
>
> set hextdobuf [::chipscope::csejtag_tap shift_device_dr $handle 0
> $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 3 =93101=94]
>
> ::chipscope::csejtag_target unlock $handle
> ::chipscope::csejtag_target close $handle
I got this working on a Spartan 3 using Chipscope 8.2 and I found I
had to issue the scan_dr command twice because there was a pipeline
delay. Also, I needed to select the USER1 instruction by doing a
scan_ir first.
Article: 141072"anushina" <kudrey@yahoo.com> wrote in message news:qLWdncbdTf3PXLrXnZ2dnUVZ_sSdnZ2d@giganews.com... > but in my project I need a decoder with 2 inputs and 1 output... > Could anyone help please? It's a common need. They generally take the form of: c = s ? a : b; You might consider switching on which hex digit to display and run it through a single 7-segment decoder, rather than having 2 decoders, although that is possible to do also. Heck, do both, and see if there's a reason to prefer one over the other.Article: 141073
It has finally been found that PAR behaves differently depending on whether its output is set to a directory or to a file, i.e. the following two commands will produce different results: par -pl high -rl std -t 36 cufc_top_map.ncd results.dir curc_top.pcf par -pl high -rl std -t 36 cufc_top_map.ncd cufc_top_par.ncd cufc_top.pcf The same problem exists in ISE 10.1.03 /Mikhail "MM" <mbmsv@yahoo.com> wrote in message news:76bs81F1bsm16U1@mid.individual.net... > Can someone explain the following behaviour? > > 1. Running MPPR to find the optimal seed number > par -n 0 -pl high -rl std -t 2 cufc_top_map.ncd results.dir cufc_top.pcf > > Level/ Design Timing Number Run NCD > Cost [ncd] Score Score Unrouted Time Status > ---------- ------ -------- -------- ----- ------------ > H_S_36 * 2269 302 0 33:09 Complete > H_S_26 * 4271 496 0 37:41 Complete > etc... > > 2. Running PAR with the found seed number > par -pl high -rl std -t 36 cufc_top_map.ncd cufc_top_par cufc_top.pcf > > Timing Score: 243686 > > > /Mikhail >Article: 141074
On Jun 3, 6:22=A0pm, whygee <why...@yg.yg> wrote: > Hi, > > Bond wrote: > > I have to use the > > formula A=3D(t1/t2-50)/12.5. can a hardware module process this kind of > > formula or it should be left for microblaze. > > the formula is not perfectly clear but I can infer a few things from past= readings, > particularly from the ever inspiring DSP litterature. > > The "/12.5" is clearly coming from a power of two, just do the maths : > =A0 =A0 =A0*1 =A0 =A0 =A0/1 > =A0 =A0 =A0*2 =A0 =A0 =A0/(1/2)=3D/0.5 > =A0 =A0 =A0*4 =A0 =A0 =A0/(1/4)=3D/0.25 > =A0 =A0 =A0*8 =A0 =A0 =A0/(1/8)=3D/0.125 > so if you divide by 0.125, you multiply by 8 > Since you divide by 12.5, you actually use another 100x factor. > > now : when you multiply by 8, you add 3 LSB (you add no information, thes= e LSB remain zeroed). > For the 100x factor, you can "scale" the whole algorithm with this factor= . > That is : the 100x multiply is only done by a display interface (just mov= e the decimal point > =A0 when you printf() it). > > This means that you don't need to perform the /12.5 division at all in VH= DL. > Also, look at Digital Signal Processing sites and books, because > this domain uses a lot of "fixed point" binary representation > (you clearly don't need floating point numbers here !) thank you for giving such a wonderful trick but still i think i have to design a multiplier which i will definitely try. > > Now, the "-50" term is unclear. actully the term 't1/t2' is duty cycle and we subtract 50 from the value of the duty cycle. so it is a constant. > It is either the data that was sampled 50ms ago, or a "magic constant"... > > This kind of division may be handled with a multi-cycle Newton-Raphson te= chnique, > which uses multiplies and add/sub operators. > could you please give some hints on implementing this technique. it would be great if you clearify me the algorithm as you did in the case of division by12.5. > Or you can use a simple 1-bit-per-cycle divider if speed allows it, and s= pace is constrained > (probably the best solution). > i didnt get this as well so once again it would be great if you clerified me with algorithm. > BTW, beware of the obvious case of x/0... > > > prashanta > > yg > > --http://ygdes.com/http://yasep.org thank you prashanta
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