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In article <nrtQj.10950$V14.4094@nlpi070.nbdc.sbc.com>, notthisjoergsch@removethispacbell.net says... > krw wrote: > > In article <k4t21496ku8p7hs9vm2t00254ov2q6udc0@4ax.com>, > > quiettechblue@yahoo.com says... > >> On Sat, 19 Apr 2008 20:47:57 -0400, krw <krw@att.bizzzzzzzzzz> wrote: > >> > >>> In article <PLsOj.7522$GE1.332@nlpi061.nbdc.sbc.com>, > >>> notthisjoergsch@removethispacbell.net says... > >>>> Joel Koltner wrote: > >>>>> "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message > >>>>> news:tq7Oj.1556$FF6.588@newssvr29.news.prodigy.net... > >>>>>> All I know from here (CA) is that their benefits are mind-boggling... > >>>>> Well, it's entirely reasonable to have retirement benefits for public > >>>>> employees be comparable to what private companies offer... I just hope that > >>>>> public employee salaries will then become comparable as well (which implies a > >>>>> pay raise), since otherwise I don't see how the gov't. expects they'll get > >>>>> comparable quality out of their workers. > >>>>> > >>>> Private companies generally offer zilch in retirement benefits. Those > >>>> days are long gone. > >>> I don't know about "gone". The age of the "defined benefit" is > >>> pretty much gone in private industry but several still have "defined > >>> contribution" plans. Now, 401Ks make up for a lot of what's been > >>> lost and are portable. > >>> > >>>>> One problem with the government seems to be that they don't expect their > >>>>> employees to be agile over time. See this article: > >>>>> http://www.gcn.com/print/24_30/37174-1.html -- Someone the government ends up > >>>>> with a bunch of 70 year old programmers and therefore has to hire IBM to build > >>>>> them the modernized e-filing systems? Surely there must be some new hires in > >>>>> the past, say, 40 years who could have been working on this and hence, on > >>>>> average, would only be middle-aged today!? > >>>>> > >>>> A 70 year old programmer can be better than a 40 year old. At least > >>>> that's my impression when I see all the "modern" bloatware ;-) > >>> Maybe. There are better things to do at 70, though. ;-) > >>>>>> Oh, and then lots of jobs have the retirement benefit tied to the last work > >>>>>> year. > >>>>> I expect that was implemented to help people who were *forced* to move? > >>>>> > >>>>> It seems like it needs reworking to differentiate between cases where the > >>>>> government wants to move you vs. you just voluntarily wanting to do so. > >>>>> > >>>> Or you just have to have the right connections to make that happen ... > >>>> > >>>> Anyhow, why should retirement checks be based on the last year of > >>>> service? IMHO that's wrong. For everyone else it sure doesn't work that way. > >>> The last years' is indicative of the final salary. Most "defined > >>> benefit" plans do take the last year, or last couple of years into > >>> account. What most private pensions *don't* do, that public plans > >>> do is include overtime in the formula. It's not hard to double > >>> one's income for a couple of years. There is no way the tax payer > >>> should pay that forever. > >> So you say. While there are classes where that is easily done it is > >> usually in the mid range hourly and low range salaried that it is > >> reasonably possible. But how may 50+ year olds do you know that can > >> and will work significant overtime? > > > > Overtime should never be needed in a well run company. That said, > > I've been averaging 60hr weeks (some 70+ and a few weeks with > > holidays, less) since August and have at least a few more months of > > work left on the pile, if I want it. There is no reason a 50s can't > > work overtime but there is also no reason to need, want, or expect > > it. BTW, I certainly wouldn't be working the overtime were I > > salaried. > > > > So what do you do at the end of this gig? Maybe buy Adnan Kashoggi's > yacht ;-) Every hour I work now is at least two I don't have to later. ;-) As they say, "you gotta make hay while the sun is shining". -- KeithArticle: 131626
On 26 avr, 23:33, Alan Nishioka <a...@nishioka.com> wrote: > swissiyous...@gmail.com wrote: > > is someone has the code of CRC (cyclical redundancy check) that xilinx > > use in the bitstream ? is it a simple CRC ( the XOR of words ) ? > > try > <http://www.xilinx.com/support/documentation/application_notes/xapp151...> > > Alan Nishioka Thank you !Article: 131627
krw wrote: > > Every hour I work now is at least two I don't have to later. ;-) > As they say, "you gotta make hay while the sun is shining". And Moonshine, when it isn't! -- http://improve-usenet.org/index.html Use any search engine other than Google till they stop polluting USENET with porn and junk commercial SPAM If you have broadband, your ISP may have a NNTP news server included in your account: http://www.usenettools.net/ISP.htmArticle: 131628
On Apr 26, 9:53=A0am, Rob <buz...@leavemealone.com> wrote: > Austin, > > Just curious: why even spec "Iccintmin is 244 mA typically" if Xilinx > really wants their users to design for 1.65A on power-up/configuration? > > I haven't read the data sheet on this part but the OP makes it sound > like the data sheet suggests a lower power-up requirement if the design > is within the nominal limits on voltage, temperature, etc... > > Rob > > austin wrote: > > KJ, > > > I am trying to politely say, he is on his on, he has exceeded the spec. > > > I am also saying that there are those who might test their systems in a > > burn-in oven, and reject the units that won't power on when hot. > > > If he has 10 units he has to ship next week, this might be a perfectly > > good temporary solution, until he re-designs his power supply. > > > AustinArticle: 131629
On Apr 26, 9:53=A0am, Rob <buz...@leavemealone.com> wrote: > Austin, > > Just curious: why even spec "Iccintmin is 244 mA typically" if Xilinx > really wants their users to design for 1.65A on power-up/configuration? > > I haven't read the data sheet on this part but the OP makes it sound > like the data sheet suggests a lower power-up requirement if the design > is within the nominal limits on voltage, temperature, etc... > > Rob > > austin wrote: > > KJ, > > > I am trying to politely say, he is on his on, he has exceeded the spec. > > > I am also saying that there are those who might test their systems in a > > burn-in oven, and reject the units that won't power on when hot. > > > If he has 10 units he has to ship next week, this might be a perfectly > > good temporary solution, until he re-designs his power supply. > > > Austin Give us a break! This particular parameter has wide variations. It is higher at high temperature and it varies widely (much more widely than most other parameters) with processing tolerances. We sell hundreds of thousands of parts every day, to thousands of customers with thousands of different board designs. We want to make sure that every user-design works all the time. That's why we test exhaustively, and we guardband the test results. That makes some of them look excessive, and they often are. But that is the price for guaranteed performance over a wide range of ambient conditions and the expected processing variations. You can probably violate the max inrush current spec, if the part is always cool when it is being turned on. But one day one user might turn power back on when the part is still hot, and the configuration might then not work, and we get ugly complaints... There is no way for us to predict what hundred thousand users might occasionally do with our parts. That's why we do worst-case testing and guardband our specifications. We prefer satisfied customers... Peter AlfkeArticle: 131630
Peter, I wasn't trying to give Xilinx a hard time. If I was, I would have been more pointed in my remarks. I think I started off my email by saying, "Just curious"; which I thought was a polite and non-aggressive choice of words. Remember, Austin said the OP is on his own since he violated the spec. My curiosity was peaked because the OP's interpretation of the data sheet suggested that the spec was between 244mA and 1.65A; and depending on other operating conditions his 1A might be OK. I believe this is what the OP was inquiring about inf the first place. I don't need to be patronized. I am very well aware of how successful Xilinx is, so you don't have to tell me that they sell 100's of 1000's of parts a day. So the answer is, since this parameter varies widely Xilinx doesn't feel comfortable recommending anything lower than the 1.65A. This is a simple answer that would have appeased everyone from the beginning. Take care, Rob Peter Alfke wrote: > On Apr 26, 9:53 am, Rob <buz...@leavemealone.com> wrote: >> Austin, >> >> Just curious: why even spec "Iccintmin is 244 mA typically" if Xilinx >> really wants their users to design for 1.65A on power-up/configuration? >> >> I haven't read the data sheet on this part but the OP makes it sound >> like the data sheet suggests a lower power-up requirement if the design >> is within the nominal limits on voltage, temperature, etc... >> >> Rob >> >> austin wrote: >>> KJ, >>> I am trying to politely say, he is on his on, he has exceeded the spec. >>> I am also saying that there are those who might test their systems in a >>> burn-in oven, and reject the units that won't power on when hot. >>> If he has 10 units he has to ship next week, this might be a perfectly >>> good temporary solution, until he re-designs his power supply. >>> Austin > > Give us a break! > This particular parameter has wide variations. It is higher at high > temperature and it varies widely (much more widely than most other > parameters) with processing tolerances. > We sell hundreds of thousands of parts every day, to thousands of > customers with thousands of different board designs. We want to make > sure that every user-design works all the time. That's why we test > exhaustively, and we guardband the test results. That makes some of > them look excessive, and they often are. But that is the price for > guaranteed performance over a wide range of ambient conditions and the > expected processing variations. > > You can probably violate the max inrush current spec, if the part is > always cool when it is being turned on. But one day one user might > turn power back on when the part is still hot, and the configuration > might then not work, and we get ugly complaints... > There is no way for us to predict what hundred thousand users might > occasionally do with our parts. That's why we do worst-case testing > and guardband our specifications. We prefer satisfied customers... > > Peter AlfkeArticle: 131631
On Apr 26, 12:14=A0am, -jg <Jim.Granvi...@gmail.com> wrote: > Peter Alfke wrote: > > The design is done, we are finishing documentation, and Ken Chapman > > has graciously agreed to give it a thorough hardware test net week: > > 4 LUTs, 4 flip-flops, insensitive to contact bounce or any type of > > erratic mechanical movement. > > =A0Then it must be VERY clever, even Clairvoyant, if it can separate > 'any type of erratic mechanical movement', from a genuine > mechanical movement! =A0;) > I would love to be clairvoyant, but in this design I only make two assumptions: that one of the two contacts is reliably open or closed, when the other one makes a (bouncy) transition. And that the mechanical travel time from one contact bouncing to the other contact bouncing is longer than a clock period of 10 to 100 MHz. I think those are reasonably safe assumptions. PeterArticle: 131632
On Fri, 25 Apr 2008 06:43:24 -0700, Joerg <notthisjoergsch@removethispacbell.net> wrote: >JosephKK wrote: >> On Mon, 21 Apr 2008 18:56:41 GMT, Joerg >> <notthisjoergsch@removethispacbell.net> wrote: >> >>> Joel Koltner wrote: >>>> Hi Joerg, >>>> >>>> "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message >>>> news:PLsOj.7522$GE1.332@nlpi061.nbdc.sbc.com... >>>>> Private companies generally offer zilch in retirement benefits. Those days >>>>> are long gone. >>>> Actually I think a very significant fraction of companies (at least those >>>> hiring EEs) offer some sort of contribution to 401k plans, sometimes profit >>>> sharing, sometimes stock options, etc... but I concur that the old days of >>>> "company pensions" is pretty much gone. >>>> >>> Mostly it's a mere pittance. And that's ok, I am a strong believer that >>> everyone should pull their own weight. Except disabled people, of course. >> Actually i have found an amazing amount of them that can do just that. >> I expect you have heard of Steven Hawking? >> > >Yes, a remarkable guy. I didn't mean folks who develop Lou Gehrig's >although they will also need support once it has progresed to a point. I >mean people like the guy with Down syndrome we sometimes visit. He's on >disability and that is really the only way for him to live. > >>> >>>>> A 70 year old programmer can be better than a 40 year old. >>>> Absolutely, but if you're an employer it's definitely a legitimate >>>> consideration that starting a bunch of 70-year-olds on a, say, decade-long >>>> "modernization" project is rather riskier than if you toss a few 50- or >>>> 30-year-olds into the mix as well. :-) >> Correct. >> >>> True. However, we should embrace the Japanese concept of letting older >>> folks teach the young ones, not lay them off. >> There is a trade off there. You need to limit that to the most >> flexible and brightest old personnel. >> > >That would be no problem. > >>> >>>>> Anyhow, why should retirement checks be based on the last year of service? >>>>> IMHO that's wrong. >>>> I agree that one year seems too short, but trying to figure out how many years >>>> should be taken into consideration (which is effectively what happens in >>>> private companies if the company is contributing to your 401k) is not going to >>>> be easy either. >>>> >>> Just make it the same as with 401(k), IRA, old style pension funds, >>> social security etc. What counts is what you pay in over your whole career. >> Heavily weighted by the early amounts because of compound interest. >> Check it out. Moreover, no matter what the contributions were there >> should come a point where the interest on the early contributions >> outweigh the current contributions. Do the arithmetic. A spreadsheet >> program makes this relatively painless. >> > >I don't think we'll see the interest rates of yesteryear anytime soon. >But the point is there should not be preferential treatment of public >service employees on the shoulders of the taxpayer. Preferential? I think not. Civil service employees generally get what was normal in industry 10 years ago. They usually trade job security for about a sixth less pay. It is the near invulnerable job security that is the problem. > > >>> We can read such stories almost daily, just an example from this morning: >>> http://www.sacbee.com/111/story/876845.html >>> >>> Guess who gets to pay the tab for the agency's legal defense?Article: 131633
On Fri, 25 Apr 2008 06:58:37 -0700, Joerg <notthisjoergsch@removethispacbell.net> wrote: >JosephKK wrote: >> On Fri, 18 Apr 2008 20:22:49 GMT, Joerg >> <notthisjoergsch@removethispacbell.net> wrote: >> >>> Joel Koltner wrote: >>>> "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message >>>> news:KD6Oj.9778$2g1.2542@nlpi068.nbdc.sbc.com... >>>>> That is strange. Normally they should have known this guy inside out before >>>>> even offering tenure if that's what his new position entails. >>>> I believe they did know him inside and out, were happy with his performance, >>>> and that's why it happened: They had already decided they were going to offer >>>> him the promotion, but some standard procedure required getting a student >>>> evaluation as well... so they had to find someone who was willing to write up >>>> a positive one. I just think it's strange that they bother getting a student >>>> evaluation when their minds are already made up... since it then puts them in >>>> the rather awkward position of having to say, "Please write us a good >>>> evaluation, or if you don't feel you can, that's OK, we'll find someone >>>> else..." Weird. >>>> >>>> Perhaps they'd do better to ask a handful of students to write up objective >>>> evaluations without the pressure of "...but, um, it has to be positive?" -- >>>> and then culling any that were negative? :-) I suppose they're stuck in a >>>> way... being tied to the government (they're a land-grant university) means >>>> they have to follow lots of procedures that regular businesses don't. >>>> >>>> Regarding the nice retirement packages... my understanding was that state >>>> workers ended up with rather cushy retirement packages in exchange for having >>>> to accept noticeably below-average salaries (relative to private industry) >>>> during their working years. In Oreogn we have the PERS (Public Employee >>>> Retirement System) which used to work this way, but the "cushy" benefits were >>>> signifcantly reduced via the ballot box when some interested parties pointed >>>> out how much better PERS was than what those folks in private industry get. >>>> Hence you now have a system where public employee pay still isn't competitive >>>> with private industry and now the retirement isn't either! This was a common >>>> topic of complaint by the professors (that you'd get to know well enough) when >>>> I was in grad school; a significant number left for private industry during >>>> that time, and I certainly coudn't blame them. >>>> >>>> That being said, I don't know enough to evaluate whether or not public jobs >>>> are still attractive when you look at the total package -- some people would >>>> argue they are and that PERS benefit reductions were just "corrections" to a >>>> system that had become too "generous" in its compensation. >>>> >>> All I know from here (CA) is that their benefits are mind-boggling. >> OK lets get to that. >> >>> Paid sick leave, >> Not particularly uncommon until you get to low end hourly. Standard >> for engineers since WWII. >> > >Most people I know don't. > > >>> fat disability payments where lots of people tried and >>> succeeded to be declared "disabled", >> Yes there has been abuses. >> > >Big time. I've seen lots of it. People who collected fat checks because >of back injuries and then personally erecting retaining walls and stuff. > IMHO there is an utter lack of enforcement. > >Hey, didn't even Spike Helmick try to collect a fat pension "upgrade" >claiming he fell off his armchair? > > >>> cradle-to-grave medical with hardly any co-pay. >> When i worked for private as an engineer it was $5 for office visit, >> $20 for lab, $5 per prescription. Today with State of CA it is $10 or >> more for office visit, $0 for lab, $5 to $25 per prescription. It >> increases in retirement. Then Medicare is supposed to kick in and >> relieve much of the State burden. If you are 65 or older and don't >> like what you have try Medicare and see how well you like that. >> > >I must pay $65 for an office visit. Plus the first $2700 (per person!) >per year out of pocket, else the premiums become unbearable. A lot of >engineers I know how no health insurance at all because they can't >afford it any longer. > > >>> The latter alone will saddle our communities with previously >>> unheard of debt. >>> Oh, and then lots of jobs have the retirement benefit >>> tied to the last work year. So, folks have themselves transferred into >>> high-cost areas such as the Bay Area for 13 months or so, then move >>> back. That ratchets their monthly checks up substantially, until their >>> dying day. That ain't right. >> It has been changed to the highest paid three years average in the >> last ten. And it now takes ten years to become "vested", instead of >> five. >> > >That's good but still not fair compared to people in non-gvt jobs. > > >> Now, you have been reading my stuff for some years now, do you think i >> am a doofus parading as an engineer? When i was hired some 15 years >> ago a PE could only expect about $5000 a month in State service. What >> was your monthly average then. What was it 5 years ago? What is it >> today. CA State pay rates for engineers and almost all others is a >> matter of public record. Try looking them up for yourself. You would >> do well to start with www.spb.ca.gov. Better still, compare them to >> County and City rates for the last 20 years. And finally note that >> for most cases the State does not give you a better paycheck based on >> where the job is, let alone where you live. Current pay rates are here: http://www.dpa.ca.gov/publications/pay-scales/index.htm Please note some of the wild variation in engineer classifications. For this group we should look for electrical or electronic engineers. Senior engineer supervises working engineers, supervising engineers are the bosses of seniors, and they in turn report to principle engineers. I have not bothered to find historical pay rates yet. All of my peer group has made more in private than in public positions. If you are not doing as well, that is not my problem. >> >> 80 percent to 90 percent of half to two thirds of what a private >> engineer can make ain't all that much. You may get a lower top >> percentage, but it is / was based on a much better salary. >> > >Half? $5k/mo is about what engineers in industry made 15 years ago. > >But the real perks are in other jobs where the legislature has caved in >to the unions. Prison guards etc. A while ago the news reported the >staggering number of applications sent in. It may not be a fun job but >it sure must have become a plum job.Article: 131634
On Fri, 25 Apr 2008 10:19:34 -0700, Joerg <notthisjoergsch@removethispacbell.net> wrote: >JosephKK wrote: >> On Thu, 17 Apr 2008 17:13:27 -0400, "Steve" <sjburke1@comcast.net> >> wrote: >> >>> "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message >>> news:U5MNj.6956$GE1.6193@nlpi061.nbdc.sbc.com... >>>> qrk wrote: >>>>> On Thu, 17 Apr 2008 09:43:09 -0700 (PDT), Dave <dhschetz@gmail.com> >>>>> wrote: >>>>> >>>>>> Does anybody out there have a good methodology for determining your >>>>>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >>>>>> The brute force method is fairly maddening. I'd be curious to hear if >>>>>> anybody has any 'tricks of the trade' here. >>>>>> >>>>>> Also, just out of curiosity, how many of you do your own PCB layout, >>>>>> versus farming it out? It would certainly save us a lot of money to >>>>>> buy the tools and do it ourselves, but it seems like laying out a >>>>>> board out well requires quite a bit of experience, especially a 6-8 >>>>>> layer board with high pin count FPGA's. >>>>>> >>>>>> We're just setting up a hardware shop here, and although I've been >>>>>> doing FPGA and board schematics design for a while, it's always been >>>>>> at a larger company with resources to farm the layout out, and we >>>>>> never did anything high-speed to really worry about the board layout >>>>>> too much. Thanks in advance for your opinions. >>>>>> >>>>>> Dave >>>>> Sure wish there was a slick way of doing FPGA pinouts. I usually use >>>>> graph paper and figure out the FPGA pinout to other parts to minimize >>>>> routing snarls. >>>>> >>>>> I do pcb layouts on my own and other folks designs. Our boards have >>>>> high-speed routing, switching power supplies, and high-gain analog >>>>> stuff; sometimes all on the same board. Unless the service bureau has >>>>> someone who understands how to lay out such circuitry and place >>>>> sensitive analog stuff near digital junk, it is more trouble to farm >>>>> out than do it yourself if you want the board to work on the first >>>>> cut. >>>>> >>>> Or find a good layouter and develop a long-term business relationship. My >>>> layouter knows just from looking at a schematic which areas are critical. >>>> He's a lot older than I am and that is probably one of the reasons why his >>>> stuff works without much assistance from me. Nothing can replace a few >>>> decades of experience. >>>> >>>> >>>>> Doing your own layout will take a lot of learning to master the PCB >>>>> layout program and what your board vendor can handle. It will take 5 >>>>> to 10 complicated boards to become mildly proficient at layout. I >>>>> don't know about saving cost. Your time may be better spent doing >>>>> other activities rather than learning about layout and doing the >>>>> layouts. ... >>>> >>>> Yep, that's why I usually do not do my own layouts. Occassionally I route >>>> a small portion of a circuit and send that to my layouter. No DRC or >>>> anything, just to show him how I'd like it done. >>>> >>>> >>>>> ... The upside to doing your own layout - you control the whole >>>>> design from start to finish. If you have a challenging layout, you'll >>>>> have a much higher probability of having a working board on the first >>>>> try which has hidden savings (getting to market earlier <- less >>>>> troubleshooting + less respins). >>>>> >>>>> --- >>>>> Mark >>>> >>>> -- >>>> Regards, Joerg >>>> >>>> http://www.analogconsultants.com/ >>>> >>>> "gmail" domain blocked because of excessive spam. >>>> Use another domain or send PM. >>> I agree with Joerg. Good high speed or mixed signal PCB layout is a career >>> choice, and we electrical engineers already chose our career. A good layout >>> requires someone who understands not just the software package, but the >>> details of how the manufacturing operation is going to proceed, what the >>> limits of the processes are, what the assembly operations require of the >>> board, and is anal about things like footprint libraries and solder mask >>> clearances and a thousand other details that I'm only partially aware of. >>> The more complex your design, the more critical these things become. >>> >>> I have two good local outfits for farming out boards. For complex stuff, >>> they know I'll come to their place and sit next to the designer for a good >>> bit of the initial placement. While we are doing placement, we are also >>> discussing critical nets, routing paths, layer usage, etc. That gives us >>> direct face to face communication and avoids spending lots of time trying to >>> write/draw everything in gory detail (which gets ignored or misunderstood a >>> lot of the time). That investment pays big dividends in schedule and board >>> performance. >>> >>> Don't be fooled by the relatively low cost of the software. That's not where >>> the big costs are. >>> >>> I once laid off my entire PCB layout department and sent all the work >>> outside, because although my employees all knew how to use the software, >>> none of them could tell me what their completion date would be, or how many >>> hours it would take, and they certainly weren't interested in meeting >>> schedules. The outside sources would commit to a cost and a delivery date. >>> And we already knew they could meet our performance objectives. Fixed price >>> contracts are great motivators. Missing an engineering test window, or >>> slipping a production schedule because of a layout delay can be enormously >>> expensive. >>> >>> Of course, if I had let my engineers do their own layouts, the motivation >>> would have been present, but the technical proficiency would not. How >>> proficient can anyone become if they only do layout a few times a year? >>> Also, on many projects engineers use the layout period for other important >>> things like documentation, test procedures, writing test code, etc. Doing >>> your own layout serializes these tasks and will stretch your schedule. >>> >>> So my advice is to keep doing what you have been doing. Its far more likely >>> that its the cheapest approach, even though you occasionally have to write a >>> big check. >>> >>> Steve >>> >> >> Pretty much honest responses. Almost all of good value. >> >> Mark hinted and Joerg mentioned one of the foremost subjects, >> floorplanning. This will impact everything you do. From the original >> schematic drawing to the FPGA VHDL/Verilog coding and optimizing to >> PWB layout , documentation, and testing. Each of these activities >> requires floorplanning to get good results. To achieve the best PWD >> layout results make several different versions for your first few >> boards and route them all to completion. It will make huge >> improvements in your understanding. >> > >Right. The same goes for code, especially micro controllers. Without >spending a lot of time on a floor plan chances are it won't fit in or >it'll become a hodge-podge of code snippets somehow stitched together. >Seen a lot of that :-( > >There seems to be a huge software company up north that has in part lost >the art of good floorplanning ... Actually it never had it.Article: 131635
On Sat, 26 Apr 2008 09:05:27 -0700, Joerg <notthisjoergsch@removethispacbell.net> wrote: >Eric Smith wrote: >> Joerg wrote: >>> The latter is a concern in my field (medical). We need to be able to >>> inspect. >> >> For medical devices/equipment, I'd be concerned with getting an RoHS >> waiver and non-green parts and solder, so that the device/equipment >> isn't likely to fail in a few years due to tin wiskers and harm the >> patient. > > >Sure. However, about a year ago we learned that we better brace >ourselves for not so good things to come: > >http://www.greensupplyline.com/howto/192300282 Yep. Volume issues. All the standard parts are RoHS. Then the questions get asked. Fortunately there are recent 4-element alloys that have fairly good properties and seem to lack tin whisker problems. Nothing fully qualified for space / life critical quite yet, but it is on the horizon.Article: 131636
Peter Alfke wrote: > On Apr 26, 12:14=EF=BF=BDam, -jg <Jim.Granvi...@gmail.com> wrote: > > > > No mention of catching illegal states ? (clock too slow) ? > > > > -jg > > I'll run the clock between 10 and 100 MHz, so it will never be too > slow. > There is no way to move a whole quadrant in one such clock period. Hi Peter, Hmm, history is littered with such brave. sweeping statements!. In the example I came across, the designer had also asserted the clock would never be to slow, :), but he did the maths based on average MASS velocities, and forgot about shock/whiplash. In a practical installation, he needed a faster clocked PLD for reliable operation. The real world can do that to designers. There is also a drive these days to save power, and use only as many MHz as will suffice. So, given the ease with which designers can get this wrong, and the ease with which catching this can be added, I would suggest that a good reference design should include this optional feature. Feel free to blame me for the inclusion :) Jim GranvilleArticle: 131637
Peter Alfke wrote: > On Apr 26, 12:14=EF=BF=BDam, -jg <Jim.Granvi...@gmail.com> wrote: > > Peter Alfke wrote: > > > The design is done, we are finishing documentation, and Ken Chapman > > > has graciously agreed to give it a thorough hardware test net week: > > > 4 LUTs, 4 flip-flops, insensitive to contact bounce or any type of > > > erratic mechanical movement. > > > > =EF=BF=BDThen it must be VERY clever, even Clairvoyant, if it can separa= te > > 'any type of erratic mechanical movement', from a genuine > > mechanical movement! =EF=BF=BD;) > > > I would love to be clairvoyant, but in this design I only make two > assumptions: > that one of the two contacts is reliably open or closed, when the > other one makes a (bouncy) transition. > And that the mechanical travel time from one contact bouncing to the > other contact bouncing is longer than a clock period of 10 to 100 MHz. > I think those are reasonably safe assumptions. > Peter Hi Peter, Your second description does not fully follow your first; the point I was making, was that in a full quadrant design, it is impossible to discriminate between "erratic mechanical movement" and a genuine movement and the counter must track Up/Dn/Up/Dn/Up until the contact settles. "insensitive to contact bounce" is thus impossible: the system should follow the bounce. (Which I think is what your second description is actually saying?) -jgArticle: 131638
i v some questions about the encrypted bitstream in the Virtex 5 , hope someone could answer me : 1* As we know the algorithm used to encrypt data in Virtex 5 ( AES 256 cbc ), can i edit by myself an encrypted rbt file ( ascii version of bit fie) strating from the unencrypted one ? 2* is only configurable data encrypted ? 3* is some hash function applied to unencrypted data before to be encrypted by AES 256 ? 4* In accordance with xilinx notes configurable data is encrypted with AES 256 mode cbc using the key user and a known startCBC vector ; so please explain me how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY !Article: 131639
JosephKK wrote: > On Fri, 25 Apr 2008 06:43:24 -0700, Joerg > <notthisjoergsch@removethispacbell.net> wrote: > >> JosephKK wrote: >>> On Mon, 21 Apr 2008 18:56:41 GMT, Joerg >>> <notthisjoergsch@removethispacbell.net> wrote: >>> >>>> Joel Koltner wrote: >>>>> Hi Joerg, >>>>> >>>>> "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message >>>>> news:PLsOj.7522$GE1.332@nlpi061.nbdc.sbc.com... >>>>>> Private companies generally offer zilch in retirement benefits. Those days >>>>>> are long gone. >>>>> Actually I think a very significant fraction of companies (at least those >>>>> hiring EEs) offer some sort of contribution to 401k plans, sometimes profit >>>>> sharing, sometimes stock options, etc... but I concur that the old days of >>>>> "company pensions" is pretty much gone. >>>>> >>>> Mostly it's a mere pittance. And that's ok, I am a strong believer that >>>> everyone should pull their own weight. Except disabled people, of course. >>> Actually i have found an amazing amount of them that can do just that. >>> I expect you have heard of Steven Hawking? >>> >> Yes, a remarkable guy. I didn't mean folks who develop Lou Gehrig's >> although they will also need support once it has progresed to a point. I >> mean people like the guy with Down syndrome we sometimes visit. He's on >> disability and that is really the only way for him to live. >> >>>>>> A 70 year old programmer can be better than a 40 year old. >>>>> Absolutely, but if you're an employer it's definitely a legitimate >>>>> consideration that starting a bunch of 70-year-olds on a, say, decade-long >>>>> "modernization" project is rather riskier than if you toss a few 50- or >>>>> 30-year-olds into the mix as well. :-) >>> Correct. >>> >>>> True. However, we should embrace the Japanese concept of letting older >>>> folks teach the young ones, not lay them off. >>> There is a trade off there. You need to limit that to the most >>> flexible and brightest old personnel. >>> >> That would be no problem. >> >>>>>> Anyhow, why should retirement checks be based on the last year of service? >>>>>> IMHO that's wrong. >>>>> I agree that one year seems too short, but trying to figure out how many years >>>>> should be taken into consideration (which is effectively what happens in >>>>> private companies if the company is contributing to your 401k) is not going to >>>>> be easy either. >>>>> >>>> Just make it the same as with 401(k), IRA, old style pension funds, >>>> social security etc. What counts is what you pay in over your whole career. >>> Heavily weighted by the early amounts because of compound interest. >>> Check it out. Moreover, no matter what the contributions were there >>> should come a point where the interest on the early contributions >>> outweigh the current contributions. Do the arithmetic. A spreadsheet >>> program makes this relatively painless. >>> >> I don't think we'll see the interest rates of yesteryear anytime soon. >> But the point is there should not be preferential treatment of public >> service employees on the shoulders of the taxpayer. > > Preferential? I think not. Civil service employees generally get > what was normal in industry 10 years ago. They usually trade job > security for about a sixth less pay. It is the near invulnerable job > security that is the problem. > But: John Doe does not get what was normal in industry 10 years ago. He just gets ever increasing property tax and other bills. Followed by eternal lamentations that those taxes aren't enough. The litmus test is this: When an agency receives boatloads of applications like it supposedly happens for the prison guard jobs then something is seriously out of balance. And yes, I agree with you that tenure track should not exist. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131640
On Apr 27, 1:31=C2=A0am, -jg <Jim.Granvi...@gmail.com> wrote: > Peter Alfke wrote: > > On Apr 26, 12:14=EF=BF=BDam, -jg <Jim.Granvi...@gmail.com> wrote: > > > Peter Alfke wrote: > > > > The design is done, we are finishing documentation, and Ken Chapman > > > > has graciously agreed to give it a thorough hardware test net week: > > > > 4 LUTs, 4 flip-flops, insensitive to contact bounce or any type of > > > > erratic mechanical movement. > > > > =EF=BF=BDThen it must be VERY clever, even Clairvoyant, if it can sepa= rate > > > 'any type of erratic mechanical movement', from a genuine > > > mechanical movement! =EF=BF=BD;) > > > I would love to be clairvoyant, but in this design I only make two > > assumptions: > > =C2=A0that one of the two contacts is reliably open or closed, when the > > other one makes a (bouncy) transition. > > And that the mechanical travel time from one contact bouncing to the > > other contact bouncing is longer than a clock period of 10 to 100 MHz. > > I think those are reasonably safe assumptions. > > Peter > > Hi Peter, > Your second description does not fully follow your first; the point > I was making, was that in a full quadrant design, it is impossible > to discriminate between "erratic mechanical movement" and a genuine > movement > and the counter must track Up/Dn/Up/Dn/Up until the contact settles. > "insensitive to contact bounce" is thus impossible: the system should > follow > the bounce. (Which I think is what your second description is > actually saying?) > > -jg Let's discuss this when the design is completely tested and described. My design does not follow the bouncing contact, it just ignores it and waits for the other contact to make a change... PeterArticle: 131641
JosephKK wrote: > On Fri, 25 Apr 2008 06:58:37 -0700, Joerg > <notthisjoergsch@removethispacbell.net> wrote: > >> JosephKK wrote: >>> On Fri, 18 Apr 2008 20:22:49 GMT, Joerg >>> <notthisjoergsch@removethispacbell.net> wrote: >>> >>>> Joel Koltner wrote: >>>>> "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message >>>>> news:KD6Oj.9778$2g1.2542@nlpi068.nbdc.sbc.com... >>>>>> That is strange. Normally they should have known this guy inside out before >>>>>> even offering tenure if that's what his new position entails. >>>>> I believe they did know him inside and out, were happy with his performance, >>>>> and that's why it happened: They had already decided they were going to offer >>>>> him the promotion, but some standard procedure required getting a student >>>>> evaluation as well... so they had to find someone who was willing to write up >>>>> a positive one. I just think it's strange that they bother getting a student >>>>> evaluation when their minds are already made up... since it then puts them in >>>>> the rather awkward position of having to say, "Please write us a good >>>>> evaluation, or if you don't feel you can, that's OK, we'll find someone >>>>> else..." Weird. >>>>> >>>>> Perhaps they'd do better to ask a handful of students to write up objective >>>>> evaluations without the pressure of "...but, um, it has to be positive?" -- >>>>> and then culling any that were negative? :-) I suppose they're stuck in a >>>>> way... being tied to the government (they're a land-grant university) means >>>>> they have to follow lots of procedures that regular businesses don't. >>>>> >>>>> Regarding the nice retirement packages... my understanding was that state >>>>> workers ended up with rather cushy retirement packages in exchange for having >>>>> to accept noticeably below-average salaries (relative to private industry) >>>>> during their working years. In Oreogn we have the PERS (Public Employee >>>>> Retirement System) which used to work this way, but the "cushy" benefits were >>>>> signifcantly reduced via the ballot box when some interested parties pointed >>>>> out how much better PERS was than what those folks in private industry get. >>>>> Hence you now have a system where public employee pay still isn't competitive >>>>> with private industry and now the retirement isn't either! This was a common >>>>> topic of complaint by the professors (that you'd get to know well enough) when >>>>> I was in grad school; a significant number left for private industry during >>>>> that time, and I certainly coudn't blame them. >>>>> >>>>> That being said, I don't know enough to evaluate whether or not public jobs >>>>> are still attractive when you look at the total package -- some people would >>>>> argue they are and that PERS benefit reductions were just "corrections" to a >>>>> system that had become too "generous" in its compensation. >>>>> >>>> All I know from here (CA) is that their benefits are mind-boggling. >>> OK lets get to that. >>> >>>> Paid sick leave, >>> Not particularly uncommon until you get to low end hourly. Standard >>> for engineers since WWII. >>> >> Most people I know don't. >> >> >>>> fat disability payments where lots of people tried and >>>> succeeded to be declared "disabled", >>> Yes there has been abuses. >>> >> Big time. I've seen lots of it. People who collected fat checks because >> of back injuries and then personally erecting retaining walls and stuff. >> IMHO there is an utter lack of enforcement. >> >> Hey, didn't even Spike Helmick try to collect a fat pension "upgrade" >> claiming he fell off his armchair? >> >> >>>> cradle-to-grave medical with hardly any co-pay. >>> When i worked for private as an engineer it was $5 for office visit, >>> $20 for lab, $5 per prescription. Today with State of CA it is $10 or >>> more for office visit, $0 for lab, $5 to $25 per prescription. It >>> increases in retirement. Then Medicare is supposed to kick in and >>> relieve much of the State burden. If you are 65 or older and don't >>> like what you have try Medicare and see how well you like that. >>> >> I must pay $65 for an office visit. Plus the first $2700 (per person!) >> per year out of pocket, else the premiums become unbearable. A lot of >> engineers I know how no health insurance at all because they can't >> afford it any longer. >> >> >>>> The latter alone will saddle our communities with previously >>>> unheard of debt. >>>> Oh, and then lots of jobs have the retirement benefit >>>> tied to the last work year. So, folks have themselves transferred into >>>> high-cost areas such as the Bay Area for 13 months or so, then move >>>> back. That ratchets their monthly checks up substantially, until their >>>> dying day. That ain't right. >>> It has been changed to the highest paid three years average in the >>> last ten. And it now takes ten years to become "vested", instead of >>> five. >>> >> That's good but still not fair compared to people in non-gvt jobs. >> >> >>> Now, you have been reading my stuff for some years now, do you think i >>> am a doofus parading as an engineer? When i was hired some 15 years >>> ago a PE could only expect about $5000 a month in State service. What >>> was your monthly average then. What was it 5 years ago? What is it >>> today. CA State pay rates for engineers and almost all others is a >>> matter of public record. Try looking them up for yourself. You would >>> do well to start with www.spb.ca.gov. Better still, compare them to >>> County and City rates for the last 20 years. And finally note that >>> for most cases the State does not give you a better paycheck based on >>> where the job is, let alone where you live. > > Current pay rates are here: > > http://www.dpa.ca.gov/publications/pay-scales/index.htm > > Please note some of the wild variation in engineer classifications. > For this group we should look for electrical or electronic engineers. > Senior engineer supervises working engineers, supervising engineers > are the bosses of seniors, and they in turn report to principle > engineers. > > I have not bothered to find historical pay rates yet. All of my peer > group has made more in private than in public positions. If you are > not doing as well, that is not my problem. > Research specialists making >10k/mo? That is a rather decent salary. Most researchers in industry do not make that much. Also, you have to consider that you guys have what almost amounts to tenure. When the budget is tight the taxpayer is expected to jump in. When the budget is tight in industry layoffs follow in due course. Right now EE is on a roll but remember 2001-2004? How many folks with masters degrees did low-wage jobs at hardware stores selling weed eaters and circular saws? I've met some. That (usually) does not happen to people in public service positions. [...] -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131642
JosephKK wrote: > On Fri, 25 Apr 2008 10:19:34 -0700, Joerg > <notthisjoergsch@removethispacbell.net> wrote: > >> JosephKK wrote: >>> On Thu, 17 Apr 2008 17:13:27 -0400, "Steve" <sjburke1@comcast.net> >>> wrote: >>> >>>> "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message >>>> news:U5MNj.6956$GE1.6193@nlpi061.nbdc.sbc.com... >>>>> qrk wrote: >>>>>> On Thu, 17 Apr 2008 09:43:09 -0700 (PDT), Dave <dhschetz@gmail.com> >>>>>> wrote: >>>>>> >>>>>>> Does anybody out there have a good methodology for determining your >>>>>>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >>>>>>> The brute force method is fairly maddening. I'd be curious to hear if >>>>>>> anybody has any 'tricks of the trade' here. >>>>>>> >>>>>>> Also, just out of curiosity, how many of you do your own PCB layout, >>>>>>> versus farming it out? It would certainly save us a lot of money to >>>>>>> buy the tools and do it ourselves, but it seems like laying out a >>>>>>> board out well requires quite a bit of experience, especially a 6-8 >>>>>>> layer board with high pin count FPGA's. >>>>>>> >>>>>>> We're just setting up a hardware shop here, and although I've been >>>>>>> doing FPGA and board schematics design for a while, it's always been >>>>>>> at a larger company with resources to farm the layout out, and we >>>>>>> never did anything high-speed to really worry about the board layout >>>>>>> too much. Thanks in advance for your opinions. >>>>>>> >>>>>>> Dave >>>>>> Sure wish there was a slick way of doing FPGA pinouts. I usually use >>>>>> graph paper and figure out the FPGA pinout to other parts to minimize >>>>>> routing snarls. >>>>>> >>>>>> I do pcb layouts on my own and other folks designs. Our boards have >>>>>> high-speed routing, switching power supplies, and high-gain analog >>>>>> stuff; sometimes all on the same board. Unless the service bureau has >>>>>> someone who understands how to lay out such circuitry and place >>>>>> sensitive analog stuff near digital junk, it is more trouble to farm >>>>>> out than do it yourself if you want the board to work on the first >>>>>> cut. >>>>>> >>>>> Or find a good layouter and develop a long-term business relationship. My >>>>> layouter knows just from looking at a schematic which areas are critical. >>>>> He's a lot older than I am and that is probably one of the reasons why his >>>>> stuff works without much assistance from me. Nothing can replace a few >>>>> decades of experience. >>>>> >>>>> >>>>>> Doing your own layout will take a lot of learning to master the PCB >>>>>> layout program and what your board vendor can handle. It will take 5 >>>>>> to 10 complicated boards to become mildly proficient at layout. I >>>>>> don't know about saving cost. Your time may be better spent doing >>>>>> other activities rather than learning about layout and doing the >>>>>> layouts. ... >>>>> Yep, that's why I usually do not do my own layouts. Occassionally I route >>>>> a small portion of a circuit and send that to my layouter. No DRC or >>>>> anything, just to show him how I'd like it done. >>>>> >>>>> >>>>>> ... The upside to doing your own layout - you control the whole >>>>>> design from start to finish. If you have a challenging layout, you'll >>>>>> have a much higher probability of having a working board on the first >>>>>> try which has hidden savings (getting to market earlier <- less >>>>>> troubleshooting + less respins). >>>>>> >>>>>> --- >>>>>> Mark >>>>> -- >>>>> Regards, Joerg >>>>> >>>>> http://www.analogconsultants.com/ >>>>> >>>>> "gmail" domain blocked because of excessive spam. >>>>> Use another domain or send PM. >>>> I agree with Joerg. Good high speed or mixed signal PCB layout is a career >>>> choice, and we electrical engineers already chose our career. A good layout >>>> requires someone who understands not just the software package, but the >>>> details of how the manufacturing operation is going to proceed, what the >>>> limits of the processes are, what the assembly operations require of the >>>> board, and is anal about things like footprint libraries and solder mask >>>> clearances and a thousand other details that I'm only partially aware of. >>>> The more complex your design, the more critical these things become. >>>> >>>> I have two good local outfits for farming out boards. For complex stuff, >>>> they know I'll come to their place and sit next to the designer for a good >>>> bit of the initial placement. While we are doing placement, we are also >>>> discussing critical nets, routing paths, layer usage, etc. That gives us >>>> direct face to face communication and avoids spending lots of time trying to >>>> write/draw everything in gory detail (which gets ignored or misunderstood a >>>> lot of the time). That investment pays big dividends in schedule and board >>>> performance. >>>> >>>> Don't be fooled by the relatively low cost of the software. That's not where >>>> the big costs are. >>>> >>>> I once laid off my entire PCB layout department and sent all the work >>>> outside, because although my employees all knew how to use the software, >>>> none of them could tell me what their completion date would be, or how many >>>> hours it would take, and they certainly weren't interested in meeting >>>> schedules. The outside sources would commit to a cost and a delivery date. >>>> And we already knew they could meet our performance objectives. Fixed price >>>> contracts are great motivators. Missing an engineering test window, or >>>> slipping a production schedule because of a layout delay can be enormously >>>> expensive. >>>> >>>> Of course, if I had let my engineers do their own layouts, the motivation >>>> would have been present, but the technical proficiency would not. How >>>> proficient can anyone become if they only do layout a few times a year? >>>> Also, on many projects engineers use the layout period for other important >>>> things like documentation, test procedures, writing test code, etc. Doing >>>> your own layout serializes these tasks and will stretch your schedule. >>>> >>>> So my advice is to keep doing what you have been doing. Its far more likely >>>> that its the cheapest approach, even though you occasionally have to write a >>>> big check. >>>> >>>> Steve >>>> >>> Pretty much honest responses. Almost all of good value. >>> >>> Mark hinted and Joerg mentioned one of the foremost subjects, >>> floorplanning. This will impact everything you do. From the original >>> schematic drawing to the FPGA VHDL/Verilog coding and optimizing to >>> PWB layout , documentation, and testing. Each of these activities >>> requires floorplanning to get good results. To achieve the best PWD >>> layout results make several different versions for your first few >>> boards and route them all to completion. It will make huge >>> improvements in your understanding. >>> >> Right. The same goes for code, especially micro controllers. Without >> spending a lot of time on a floor plan chances are it won't fit in or >> it'll become a hodge-podge of code snippets somehow stitched together. >> Seen a lot of that :-( >> >> There seems to be a huge software company up north that has in part lost >> the art of good floorplanning ... > > Actually it never had it. > :-) Although I must say that the folks who designed MS-Works did a fine job. Even the Windows versions of it never crashed on me. That is quite unusual for Windows programs. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131643
swiss, There is nothing proprietary about the algorithm, nor the format: it is all documented. All configuration bitstream data (config memory and BRAM contents) are encrypted. There is no built in hardened secure authentication (e.g. SHA-XXX), only AES256 decryption. SHA-XXX can be added as soft IP, and used to authenticate after startup using the ICAP feature (we have SHA-256 as a reference design, in process). Any bitstream, encrypted or not, is accepted by the part today. If you are an areospace/defense customer, contact your FAE for information on how parts which will only accept encrypted bitstreams are accomplished. What is it you are trying to do? Why? What problem are you trying to solve? How do you solve this problem today? (for our market research) AustinArticle: 131644
JosephKK wrote: > On Sat, 26 Apr 2008 09:05:27 -0700, Joerg > <notthisjoergsch@removethispacbell.net> wrote: > >> Eric Smith wrote: >>> Joerg wrote: >>>> The latter is a concern in my field (medical). We need to be able to >>>> inspect. >>> For medical devices/equipment, I'd be concerned with getting an RoHS >>> waiver and non-green parts and solder, so that the device/equipment >>> isn't likely to fail in a few years due to tin wiskers and harm the >>> patient. >> >> Sure. However, about a year ago we learned that we better brace >> ourselves for not so good things to come: >> >> http://www.greensupplyline.com/howto/192300282 > > Yep. Volume issues. All the standard parts are RoHS. Then the > questions get asked. Fortunately there are recent 4-element alloys > that have fairly good properties and seem to lack tin whisker > problems. Nothing fully qualified for space / life critical quite > yet, but it is on the horizon. > I just hope RoHS doesn't blow up in our face like other hip-shot decisions by politicos. Such as MTBE in California gasoline. But it might. Only time will tell. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131645
Joerg wrote: > > I just hope RoHS doesn't blow up in our face like other hip-shot > decisions by politicos. Such as MTBE in California gasoline. But it > might. Only time will tell. Speaking of gasoline, try this: Put 1/4 cup of modern gasoline with its mandated percentage of ethanol in an open tray, and wait a few minutes. First, the container will chill down from the 70F range to the low 40s and then you will cloud up, and you will see brown dirt, and water globules form on the bottom of the container. This will spell the end to lawn mowers, and other gasoline driven devices, that don't have sealed pressurized gas tanks. -ChuckArticle: 131646
Joerg wrote: > > Research specialists making >10k/mo? That is a rather decent salary. > Most researchers in industry do not make that much. > > Also, you have to consider that you guys have what almost amounts to > tenure. When the budget is tight the taxpayer is expected to jump in. > When the budget is tight in industry layoffs follow in due course. Right > now EE is on a roll but remember 2001-2004? How many folks with masters > degrees did low-wage jobs at hardware stores selling weed eaters and > circular saws? I've met some. That (usually) does not happen to people > in public service positions. Marion County, Florida recently laid off about half of it's building inspectors and support staff. The trucks they drove were auctioned off a few days ago, as well. That money will go back into the county's general fund, as well as the unused salaries. -- http://improve-usenet.org/index.html Use any search engine other than Google till they stop polluting USENET with porn and junk commercial SPAM If you have broadband, your ISP may have a NNTP news server included in your account: http://www.usenettools.net/ISP.htmArticle: 131647
-jg wrote: > > Peter Alfke wrote: > >> On Apr 26, 12:14�am, -jg <Jim.Granvi...@gmail.com> wrote: >>> Peter Alfke wrote: >>>> The design is done, we are finishing documentation, and Ken Chapman >>>> has graciously agreed to give it a thorough hardware test net week: >>>> 4 LUTs, 4 flip-flops, insensitive to contact bounce or any type of >>>> erratic mechanical movement. >>> �Then it must be VERY clever, even Clairvoyant, if it can separate >>> 'any type of erratic mechanical movement', from a genuine >>> mechanical movement! �;) >>> >> I would love to be clairvoyant, but in this design I only make two >> assumptions: >> that one of the two contacts is reliably open or closed, when the >> other one makes a (bouncy) transition. >> And that the mechanical travel time from one contact bouncing to the >> other contact bouncing is longer than a clock period of 10 to 100 MHz. >> I think those are reasonably safe assumptions. >> Peter > > Hi Peter, > Your second description does not fully follow your first; the point > I was making, was that in a full quadrant design, it is impossible > to discriminate between "erratic mechanical movement" and a genuine > movement > and the counter must track Up/Dn/Up/Dn/Up until the contact settles. > "insensitive to contact bounce" is thus impossible: the system should > follow > the bounce. (Which I think is what your second description is > actually saying?) > > -jg The system does not count edges, it counts states. This means that bounces will not matter as long as only one input changes at a time. If you miss and even number of edges, you are at the same state you started at and the result is correct. If you miss an odd number, you are in the next state and the result is correct at the next clock. This is not the case if you use the edges for clocks. That is a very bad thing to do and will give you lots of problems. You do care if both inputs bounce. That is tough to follow.Article: 131648
Sir Austin As a designer using extensively Xilinx products , i want to verify that really aes 256 is used to encrypt bitstream . When i tried to encrypt configurable data ( after writing to FDRI) in the unencrypted raw bit file with AES 256 cbc i couldn't find the right cipher in the encrypted one !? why ? If some designer would have wanted to decrypt his bitstream , so as you said "there is nothing proprietary about the algorithm" why this designer can not recover his unencrypted bitstream with his secret key ?! Thank you , SwissiArticle: 131649
swissi, I have no idea what you are trying to tell me. If you have the key used to encrypt the bitstream, then of course, you can decrypt the bitstream. That is how it works, and how it is used. The only information you need is the key, and where in the bitstream the encryption begins (there is pre-pended information which is always common, encrypted or not preceding the information). Are you just trying to check that we are using AES256? Are you trying to make sure that your bitstream has been encrypted? Austin
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