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On Fri, 18 Apr 2008 20:22:49 GMT, Joerg <notthisjoergsch@removethispacbell.net> wrote: >Joel Koltner wrote: >> "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message >> news:KD6Oj.9778$2g1.2542@nlpi068.nbdc.sbc.com... >>> That is strange. Normally they should have known this guy inside out before >>> even offering tenure if that's what his new position entails. >> >> I believe they did know him inside and out, were happy with his performance, >> and that's why it happened: They had already decided they were going to offer >> him the promotion, but some standard procedure required getting a student >> evaluation as well... so they had to find someone who was willing to write up >> a positive one. I just think it's strange that they bother getting a student >> evaluation when their minds are already made up... since it then puts them in >> the rather awkward position of having to say, "Please write us a good >> evaluation, or if you don't feel you can, that's OK, we'll find someone >> else..." Weird. >> >> Perhaps they'd do better to ask a handful of students to write up objective >> evaluations without the pressure of "...but, um, it has to be positive?" -- >> and then culling any that were negative? :-) I suppose they're stuck in a >> way... being tied to the government (they're a land-grant university) means >> they have to follow lots of procedures that regular businesses don't. >> >> Regarding the nice retirement packages... my understanding was that state >> workers ended up with rather cushy retirement packages in exchange for having >> to accept noticeably below-average salaries (relative to private industry) >> during their working years. In Oreogn we have the PERS (Public Employee >> Retirement System) which used to work this way, but the "cushy" benefits were >> signifcantly reduced via the ballot box when some interested parties pointed >> out how much better PERS was than what those folks in private industry get. >> Hence you now have a system where public employee pay still isn't competitive >> with private industry and now the retirement isn't either! This was a common >> topic of complaint by the professors (that you'd get to know well enough) when >> I was in grad school; a significant number left for private industry during >> that time, and I certainly coudn't blame them. >> >> That being said, I don't know enough to evaluate whether or not public jobs >> are still attractive when you look at the total package -- some people would >> argue they are and that PERS benefit reductions were just "corrections" to a >> system that had become too "generous" in its compensation. >> > >All I know from here (CA) is that their benefits are mind-boggling. OK lets get to that. >Paid sick leave, Not particularly uncommon until you get to low end hourly. Standard for engineers since WWII. > fat disability payments where lots of people tried and >succeeded to be declared "disabled", Yes there has been abuses. >cradle-to-grave medical with hardly any co-pay. When i worked for private as an engineer it was $5 for office visit, $20 for lab, $5 per prescription. Today with State of CA it is $10 or more for office visit, $0 for lab, $5 to $25 per prescription. It increases in retirement. Then Medicare is supposed to kick in and relieve much of the State burden. If you are 65 or older and don't like what you have try Medicare and see how well you like that. >The latter alone will saddle our communities with previously >unheard of debt. > Oh, and then lots of jobs have the retirement benefit >tied to the last work year. So, folks have themselves transferred into >high-cost areas such as the Bay Area for 13 months or so, then move >back. That ratchets their monthly checks up substantially, until their >dying day. That ain't right. It has been changed to the highest paid three years average in the last ten. And it now takes ten years to become "vested", instead of five. Now, you have been reading my stuff for some years now, do you think i am a doofus parading as an engineer? When i was hired some 15 years ago a PE could only expect about $5000 a month in State service. What was your monthly average then. What was it 5 years ago? What is it today. CA State pay rates for engineers and almost all others is a matter of public record. Try looking them up for yourself. You would do well to start with www.spb.ca.gov. Better still, compare them to County and City rates for the last 20 years. And finally note that for most cases the State does not give you a better paycheck based on where the job is, let alone where you live. 80 percent to 90 percent of half to two thirds of what a private engineer can make ain't all that much. You may get a lower top percentage, but it is / was based on a much better salary.Article: 131551
On Sat, 19 Apr 2008 20:47:57 -0400, krw <krw@att.bizzzzzzzzzz> wrote: >In article <PLsOj.7522$GE1.332@nlpi061.nbdc.sbc.com>, >notthisjoergsch@removethispacbell.net says... >> Joel Koltner wrote: >> > "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message >> > news:tq7Oj.1556$FF6.588@newssvr29.news.prodigy.net... >> >> All I know from here (CA) is that their benefits are mind-boggling... >> > >> > Well, it's entirely reasonable to have retirement benefits for public >> > employees be comparable to what private companies offer... I just hope that >> > public employee salaries will then become comparable as well (which implies a >> > pay raise), since otherwise I don't see how the gov't. expects they'll get >> > comparable quality out of their workers. >> > >> >> Private companies generally offer zilch in retirement benefits. Those >> days are long gone. > >I don't know about "gone". The age of the "defined benefit" is >pretty much gone in private industry but several still have "defined >contribution" plans. Now, 401Ks make up for a lot of what's been >lost and are portable. > >> > One problem with the government seems to be that they don't expect their >> > employees to be agile over time. See this article: >> > http://www.gcn.com/print/24_30/37174-1.html -- Someone the government ends up >> > with a bunch of 70 year old programmers and therefore has to hire IBM to build >> > them the modernized e-filing systems? Surely there must be some new hires in >> > the past, say, 40 years who could have been working on this and hence, on >> > average, would only be middle-aged today!? >> > >> >> A 70 year old programmer can be better than a 40 year old. At least >> that's my impression when I see all the "modern" bloatware ;-) > >Maybe. There are better things to do at 70, though. ;-) >> >> >> Oh, and then lots of jobs have the retirement benefit tied to the last work >> >> year. >> > >> > I expect that was implemented to help people who were *forced* to move? >> > >> > It seems like it needs reworking to differentiate between cases where the >> > government wants to move you vs. you just voluntarily wanting to do so. >> > >> >> Or you just have to have the right connections to make that happen ... >> >> Anyhow, why should retirement checks be based on the last year of >> service? IMHO that's wrong. For everyone else it sure doesn't work that way. > >The last years' is indicative of the final salary. Most "defined >benefit" plans do take the last year, or last couple of years into >account. What most private pensions *don't* do, that public plans >do is include overtime in the formula. It's not hard to double >one's income for a couple of years. There is no way the tax payer >should pay that forever. So you say. While there are classes where that is easily done it is usually in the mid range hourly and low range salaried that it is reasonably possible. But how may 50+ year olds do you know that can and will work significant overtime?Article: 131552
On Sat, 19 Apr 2008 22:34:30 -0400, krw <krw@att.bizzzzzzzzzz> wrote: >In article <ovwOj.2084$pS4.1733@newssvr13.news.prodigy.net>, >notthisjoergsch@removethispacbell.net says... >> krw wrote: >> > In article <PLsOj.7522$GE1.332@nlpi061.nbdc.sbc.com>, >> > notthisjoergsch@removethispacbell.net says... >> >> Joel Koltner wrote: >> >>> "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message >> >>> news:tq7Oj.1556$FF6.588@newssvr29.news.prodigy.net... >> >>>> All I know from here (CA) is that their benefits are mind-boggling... >> >>> Well, it's entirely reasonable to have retirement benefits for public >> >>> employees be comparable to what private companies offer... I just hope that >> >>> public employee salaries will then become comparable as well (which implies a >> >>> pay raise), since otherwise I don't see how the gov't. expects they'll get >> >>> comparable quality out of their workers. >> >>> >> >> Private companies generally offer zilch in retirement benefits. Those >> >> days are long gone. >> > >> > I don't know about "gone". The age of the "defined benefit" is >> > pretty much gone in private industry but several still have "defined >> > contribution" plans. Now, 401Ks make up for a lot of what's been >> > lost and are portable. >> > >> >> Sure, but 401(k) is generally funded by the employee. Occasionally the >> company throws in a little extra but that is mostly a mere drop in the >> bucket in contrast to the lavish pension plans that cover many state >> workers. > >It's quite normal for a company to add significantly to the 401K, >sometimes with strings attached, sometimes without. My PPOE had a >fairly decent 401K (in addition to pension plans for everyone >joining before '06, or so). They matched 1:1 up to 6% of salary >(plus bonusus) and had no management fees for the normal funds. I >understand it's gotten better since they've dropped the pension >plans for the newbs. > >> >>> One problem with the government seems to be that they don't expect their >> >>> employees to be agile over time. See this article: >> >>> http://www.gcn.com/print/24_30/37174-1.html -- Someone the government ends up >> >>> with a bunch of 70 year old programmers and therefore has to hire IBM to build >> >>> them the modernized e-filing systems? Surely there must be some new hires in >> >>> the past, say, 40 years who could have been working on this and hence, on >> >>> average, would only be middle-aged today!? >> >>> >> >> A 70 year old programmer can be better than a 40 year old. At least >> >> that's my impression when I see all the "modern" bloatware ;-) >> > >> > Maybe. There are better things to do at 70, though. ;-) >> >> >> Yes, definitely. OTOH completely quitting a career has brought many fine >> engineers into the grave within less than a year. My father who worked >> as a data processing engineer continued as a consultant and gradually >> tapered it off. He said that there was a rash of unexpected deaths of >> otherwise quite healthy colleagues right after retirement, and it was >> among the group of engineers who shut their careers down more or less >> overnight after the first retirement check arrived. > >I got quite bored, once I wasn't allowed to make messes at home >anymore. Good thing that only lasted a week or two. ;-) >> >> >>>> Oh, and then lots of jobs have the retirement benefit tied to the last work >> >>>> year. >> >>> I expect that was implemented to help people who were *forced* to move? >> >>> >> >>> It seems like it needs reworking to differentiate between cases where the >> >>> government wants to move you vs. you just voluntarily wanting to do so. >> >>> >> >> Or you just have to have the right connections to make that happen ... >> >> >> >> Anyhow, why should retirement checks be based on the last year of >> >> service? IMHO that's wrong. For everyone else it sure doesn't work that way. >> > >> > The last years' is indicative of the final salary. Most "defined >> > benefit" plans do take the last year, or last couple of years into >> > account. What most private pensions *don't* do, that public plans >> > do is include overtime in the formula. It's not hard to double >> > one's income for a couple of years. There is no way the tax payer >> > should pay that forever. >> > >> >> But it's happening. And we are all paying for that. > >Precisely. It's not going to get better. The government requires >others to have fully funded retirement plans, but would have none of >it for themselves. Actually CalPERS is one exception to the slightly over broad brush. Of course over 2E11 dollars is not a toy.Article: 131553
On Mon, 21 Apr 2008 18:56:41 GMT, Joerg <notthisjoergsch@removethispacbell.net> wrote: >Joel Koltner wrote: >> Hi Joerg, >> >> "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message >> news:PLsOj.7522$GE1.332@nlpi061.nbdc.sbc.com... >>> Private companies generally offer zilch in retirement benefits. Those days >>> are long gone. >> >> Actually I think a very significant fraction of companies (at least those >> hiring EEs) offer some sort of contribution to 401k plans, sometimes profit >> sharing, sometimes stock options, etc... but I concur that the old days of >> "company pensions" is pretty much gone. >> > >Mostly it's a mere pittance. And that's ok, I am a strong believer that >everyone should pull their own weight. Except disabled people, of course. Actually i have found an amazing amount of them that can do just that. I expect you have heard of Steven Hawking? > > >>> A 70 year old programmer can be better than a 40 year old. >> >> Absolutely, but if you're an employer it's definitely a legitimate >> consideration that starting a bunch of 70-year-olds on a, say, decade-long >> "modernization" project is rather riskier than if you toss a few 50- or >> 30-year-olds into the mix as well. :-) Correct. >> > >True. However, we should embrace the Japanese concept of letting older >folks teach the young ones, not lay them off. There is a trade off there. You need to limit that to the most flexible and brightest old personnel. > > >>> Anyhow, why should retirement checks be based on the last year of service? >>> IMHO that's wrong. >> >> I agree that one year seems too short, but trying to figure out how many years >> should be taken into consideration (which is effectively what happens in >> private companies if the company is contributing to your 401k) is not going to >> be easy either. >> > >Just make it the same as with 401(k), IRA, old style pension funds, >social security etc. What counts is what you pay in over your whole career. Heavily weighted by the early amounts because of compound interest. Check it out. Moreover, no matter what the contributions were there should come a point where the interest on the early contributions outweigh the current contributions. Do the arithmetic. A spreadsheet program makes this relatively painless. > >We can read such stories almost daily, just an example from this morning: >http://www.sacbee.com/111/story/876845.html > >Guess who gets to pay the tab for the agency's legal defense?Article: 131554
"Julio Espada" <newsnet@jmo.biz> a écrit dans le message de news: 481125b4$0$14073$a729d347@news.telepac.pt... > Hi! > > I'm looking for the Atmel ATF750C library for Proteus but I'm unable to > find it on both Atmel & Labcenter sites. Does anyone know where can I find > this ? Or perhaps, any other application that can simulate the ATF750C ? Have you asked Labcenter directly through their web forum ? They are usually very quick in providing good answers... and even to model a couple of new components free of charge for registered customers... If not then another way may be just to use a generic PAL simulator, as this chip seems to be a kind of 22V10. Old but good tools like PALASM ? Yours, Robert www.alciom.comArticle: 131555
On Mon, 21 Apr 2008 12:40:55 -0700, "Joel Koltner" <zapwireDASHgroups@yahoo.com> wrote: >"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message >news:Jr5Pj.4650$vF.1890@newssvr21.news.prodigy.net... >> Mostly it's a mere pittance. And that's ok, I am a strong believer that >> everyone should pull their own weight. > >I guess it depends on the employer... > >Do you see anything bad about the old system of pensions (from private >companies, ignore the government for the moment)? I see them more as >"different" than particularly better or worse. These days you're personally >responsible for more of your retirement planning, which has the upside that >you can probably do a better job than some company-wide pension programs used >to do, but the downside is that those who plan poorly (or not at all) end up >needing that much more government assistance once they're retired. > >> True. However, we should embrace the Japanese concept of letting older folks >> teach the young ones, not lay them off. > >Yes, agreed 100%. > >> Just make it the same as with 401(k), IRA, old style pension funds, social >> security etc. What counts is what you pay in over your whole career. > >The end result there is that if your employer requires you to move to, e.g., >California for the last few years of employment you'll pretty much be forced >to then immediately move when you hit retirement. I suppose that isn't >particularly awful, since that fact would have been clear when the employer >said, "move!" > >> Guess who gets to pay the tab for the agency's legal defense? > >Sheesh... screw the taxpyers with retiremend funding and then screw'em again >when someone tries to blow the whistle. Nice... Finally, someone else caught on. > >---Joel >Article: 131556
On Fri, 18 Apr 2008 00:09:02 -0700 (PDT), "David L. Jones" <altzone@gmail.com> wrote: >On Apr 18, 8:15 am, Dave <dhsch...@gmail.com> wrote: >> On Apr 17, 5:13 pm, "Steve" <sjbur...@comcast.net> wrote: >> >> >> >> > "Joerg" <notthisjoerg...@removethispacbell.net> wrote in message >> >> >news:U5MNj.6956$GE1.6193@nlpi061.nbdc.sbc.com... >> >> > > qrk wrote: >> > >> On Thu, 17 Apr 2008 09:43:09 -0700 (PDT), Dave <dhsch...@gmail.com> >> > >> wrote: >> >> > >>> Does anybody out there have a good methodology for determining your >> > >>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >> > >>> The brute force method is fairly maddening. I'd be curious to hear if >> > >>> anybody has any 'tricks of the trade' here. >> >> > >>> Also, just out of curiosity, how many of you do your own PCB layout, >> > >>> versus farming it out? It would certainly save us a lot of money to >> > >>> buy the tools and do it ourselves, but it seems like laying out a >> > >>> board out well requires quite a bit of experience, especially a 6-8 >> > >>> layer board with high pin count FPGA's. >> >> > >>> We're just setting up a hardware shop here, and although I've been >> > >>> doing FPGA and board schematics design for a while, it's always been >> > >>> at a larger company with resources to farm the layout out, and we >> > >>> never did anything high-speed to really worry about the board layout >> > >>> too much. Thanks in advance for your opinions. >> >> > >>> Dave >> >> > >> Sure wish there was a slick way of doing FPGA pinouts. I usually use >> > >> graph paper and figure out the FPGA pinout to other parts to minimize >> > >> routing snarls. >> >> > >> I do pcb layouts on my own and other folks designs. Our boards have >> > >> high-speed routing, switching power supplies, and high-gain analog >> > >> stuff; sometimes all on the same board. Unless the service bureau has >> > >> someone who understands how to lay out such circuitry and place >> > >> sensitive analog stuff near digital junk, it is more trouble to farm >> > >> out than do it yourself if you want the board to work on the first >> > >> cut. >> >> > > Or find a good layouter and develop a long-term business relationship. My >> > > layouter knows just from looking at a schematic which areas are critical. >> > > He's a lot older than I am and that is probably one of the reasons why his >> > > stuff works without much assistance from me. Nothing can replace a few >> > > decades of experience. >> >> > >> Doing your own layout will take a lot of learning to master the PCB >> > >> layout program and what your board vendor can handle. It will take 5 >> > >> to 10 complicated boards to become mildly proficient at layout. I >> > >> don't know about saving cost. Your time may be better spent doing >> > >> other activities rather than learning about layout and doing the >> > >> layouts. ... >> >> > > Yep, that's why I usually do not do my own layouts. Occassionally I route >> > > a small portion of a circuit and send that to my layouter. No DRC or >> > > anything, just to show him how I'd like it done. >> >> > >> ... The upside to doing your own layout - you control the whole >> > >> design from start to finish. If you have a challenging layout, you'll >> > >> have a much higher probability of having a working board on the first >> > >> try which has hidden savings (getting to market earlier <- less >> > >> troubleshooting + less respins). >> >> > >> --- >> > >> Mark >> >> > > -- >> > > Regards, Joerg >> >> > >http://www.analogconsultants.com/ >> >> > > "gmail" domain blocked because of excessive spam. >> > > Use another domain or send PM. >> >> > I agree with Joerg. Good high speed or mixed signal PCB layout is a career >> > choice, and we electrical engineers already chose our career. A good layout >> > requires someone who understands not just the software package, but the >> > details of how the manufacturing operation is going to proceed, what the >> > limits of the processes are, what the assembly operations require of the >> > board, and is anal about things like footprint libraries and solder mask >> > clearances and a thousand other details that I'm only partially aware of. >> > The more complex your design, the more critical these things become. >> >> > I have two good local outfits for farming out boards. For complex stuff, >> > they know I'll come to their place and sit next to the designer for a good >> > bit of the initial placement. While we are doing placement, we are also >> > discussing critical nets, routing paths, layer usage, etc. That gives us >> > direct face to face communication and avoids spending lots of time trying to >> > write/draw everything in gory detail (which gets ignored or misunderstood a >> > lot of the time). That investment pays big dividends in schedule and board >> > performance. >> >> > Don't be fooled by the relatively low cost of the software. That's not where >> > the big costs are. >> >> > I once laid off my entire PCB layout department and sent all the work >> > outside, because although my employees all knew how to use the software, >> > none of them could tell me what their completion date would be, or how many >> > hours it would take, and they certainly weren't interested in meeting >> > schedules. The outside sources would commit to a cost and a delivery date. >> > And we already knew they could meet our performance objectives. Fixed price >> > contracts are great motivators. Missing an engineering test window, or >> > slipping a production schedule because of a layout delay can be enormously >> > expensive. >> >> > Of course, if I had let my engineers do their own layouts, the motivation >> > would have been present, but the technical proficiency would not. How >> > proficient can anyone become if they only do layout a few times a year? >> > Also, on many projects engineers use the layout period for other important >> > things like documentation, test procedures, writing test code, etc. Doing >> > your own layout serializes these tasks and will stretch your schedule. >> >> > So my advice is to keep doing what you have been doing. Its far more likely >> > that its the cheapest approach, even though you occasionally have to write a >> > big check. >> >> > Steve >> >> I tend to agree with the 'farm-it-out' crowd. Unfortunately, my >> current employer doesn't want to work with my previous layout people, >> so I've been trying to search for a new partner. I've found plenty of >> board fab and assembly places, but not so much on the layout. It made >> me think that the rest of the world did their own layout. The opinions >> look pretty split from the replies here, maybe it comes down to how >> many times you do a layout each year, and how much you enjoy that sort >> of work. I definitely think it's something you have to do fairly often >> to keep your chops up. >> >> Andy, I'd also like to hear more about your pin-swap FPGA design flow >> - what tools do that? Also curious about any timing issues that have >> been caught after the pin-swap. > >In Altium Designer I use the incredibly useful "subnet jumper" feature >for BGA's. >The procedure goes something like this: >1) Fan out all the required FPGA pins first (automatically or >manually) to just outside the chip boundry. (leave several diagonal >entry paths for core and other power flood fills to get in) >2) Fully route all non-pin-swappable pins and other critical lines. >3) Ensure any other parts placements are near any required FPGA pins >or block features you think you might need. >4) Route every track just short of the fanout tracks >5) Hit the "add subnet jumper" feature and it finishes the tracks and >does all the pin swaps for you and updates the schematic. > >Probably needs a picture or two to explain it best though... > >The great part about subnet jumpers is if there are timing or other >problems you can just remove the subnet jumpers and add/edit tracks >and pins as needed and then replace the subnet jumpers. Only takes a >minute or two. > >Dave. That does sound specific to one particular tool (vendors's software).Article: 131557
krunal wrote:
> hi....I want to implement Sigma Delta ADC in Spartan 3E starter
> kit....i have implemented it as xilinx's xapp-155.....in ise it works
> well for 8 bit....but give problem for 16 bit.....When i open it in
> sysgen it now work.......actually in program the dac.v is
> included......i dont know how to open that include file in
> sysgen....please help........if any one have verilog or vhdl code for
> that please send me........and i want to interface the exeternal ADC
> also.....so please help me......
.-. - ..-. --
.... - ....
... -.-- -- ...
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From: Thorsten Kiefer <webmaster@nillakaes.de>
Subject: noob question
Newsgroups: comp.arch.fpga
Date: Fri, 25 Apr 2008 14:06:44 +0200
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Hi,
when i synthesize this :
architecture Behavioral of vga_test is
constant MXINIT : integer := 100;
constant MYINIT : integer := 100;
signal mousex_reg,mousey_reg : unsigned(9 downto 0);
signal mousex_next,mousey_next : unsigned(9 downto 0);
....
begin
process(clk,reset)
begin
if reset='1' then
rgb_reg <= (others=>'0');
mousex_reg <= MXINIT;
mousey_reg <= MYINIT;
elsif rising_edge
......
i get the following error messages :
HDLParsers:800 - "/home/thorsten/work/xilinx/vgatest1/vga_test.vhd" Line 66.
Type of mousex_reg is incompatible with type of MXINIT.
ERROR:HDLParsers:800 - "/home/thorsten/work/xilinx/vgatest1/vga_test.vhd"
Line 67. Type of mousey_reg is incompatible with type of MYINIT.
using the unsigned() conversion function doesnt work either.
Best Regards
Thorsten
Article: 131558Hi there, I wanna use in my design 4 EMACs. I have used CORE Generator to generate 2 Virtex 5 Embedded Tri-Mode Ethernet MAC wrappers 1.4 (each contains 2 EMACs). In fact, they have the same properties except of MAC addresses. I have written the top module where I used two generated components and made control for them. But after I started simulation, just one EMAC0 and EMAC1 generate txclient and rxclient clocks, EMAC2 and EMAC3 don't. I'm using in my project XC5VLX50T chip, which has 4 EMACs onto. It looks like EMAC2 and EMAC3 clock outputs go to undefined states after around 1 us. Could someone tell me what's wrong there? or what is the right way to use 4 EMACs together? Cheers, Vlad.Article: 131559
On 25 Apr., 14:06, Thorsten Kiefer <webmas...@nillakaes.de> wrote: > Hi, > when i synthesize this : > > architecture Behavioral of vga_test is > constant MXINIT : integer := 100; > constant MYINIT : integer := 100; > signal mousex_reg,mousey_reg : unsigned(9 downto 0); > signal mousex_next,mousey_next : unsigned(9 downto 0); > .... > begin > process(clk,reset) > begin > if reset='1' then > rgb_reg <= (others=>'0'); > mousex_reg <= MXINIT; > mousey_reg <= MYINIT; > elsif rising_edge > ...... > > i get the following error messages : > HDLParsers:800 - "/home/thorsten/work/xilinx/vgatest1/vga_test.vhd" Line 66. > Type of mousex_reg is incompatible with type of MXINIT. > ERROR:HDLParsers:800 - "/home/thorsten/work/xilinx/vgatest1/vga_test.vhd" > Line 67. Type of mousey_reg is incompatible with type of MYINIT. > > using the unsigned() conversion function doesnt work either. > > Best Regards > Thorsten I would declare registers us std_logic_vector(9 downto 0) and use following type conversion conv_std_logic_vector(MXINIT, 10). Or mousex_reg <= unsigned(conv_std_logic_vector(MXINIT, 10)); TPArticle: 131560
JosephKK wrote: > On Mon, 21 Apr 2008 18:56:41 GMT, Joerg > <notthisjoergsch@removethispacbell.net> wrote: > >> Joel Koltner wrote: >>> Hi Joerg, >>> >>> "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message >>> news:PLsOj.7522$GE1.332@nlpi061.nbdc.sbc.com... >>>> Private companies generally offer zilch in retirement benefits. Those days >>>> are long gone. >>> Actually I think a very significant fraction of companies (at least those >>> hiring EEs) offer some sort of contribution to 401k plans, sometimes profit >>> sharing, sometimes stock options, etc... but I concur that the old days of >>> "company pensions" is pretty much gone. >>> >> Mostly it's a mere pittance. And that's ok, I am a strong believer that >> everyone should pull their own weight. Except disabled people, of course. > Actually i have found an amazing amount of them that can do just that. > I expect you have heard of Steven Hawking? > Yes, a remarkable guy. I didn't mean folks who develop Lou Gehrig's although they will also need support once it has progresed to a point. I mean people like the guy with Down syndrome we sometimes visit. He's on disability and that is really the only way for him to live. >> >>>> A 70 year old programmer can be better than a 40 year old. >>> Absolutely, but if you're an employer it's definitely a legitimate >>> consideration that starting a bunch of 70-year-olds on a, say, decade-long >>> "modernization" project is rather riskier than if you toss a few 50- or >>> 30-year-olds into the mix as well. :-) > Correct. > >> True. However, we should embrace the Japanese concept of letting older >> folks teach the young ones, not lay them off. > There is a trade off there. You need to limit that to the most > flexible and brightest old personnel. > That would be no problem. >> >>>> Anyhow, why should retirement checks be based on the last year of service? >>>> IMHO that's wrong. >>> I agree that one year seems too short, but trying to figure out how many years >>> should be taken into consideration (which is effectively what happens in >>> private companies if the company is contributing to your 401k) is not going to >>> be easy either. >>> >> Just make it the same as with 401(k), IRA, old style pension funds, >> social security etc. What counts is what you pay in over your whole career. > Heavily weighted by the early amounts because of compound interest. > Check it out. Moreover, no matter what the contributions were there > should come a point where the interest on the early contributions > outweigh the current contributions. Do the arithmetic. A spreadsheet > program makes this relatively painless. > I don't think we'll see the interest rates of yesteryear anytime soon. But the point is there should not be preferential treatment of public service employees on the shoulders of the taxpayer. >> We can read such stories almost daily, just an example from this morning: >> http://www.sacbee.com/111/story/876845.html >> >> Guess who gets to pay the tab for the agency's legal defense? -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131561
hi Thanks for the link. Well the problem is the this is a university project and I'm stuck with what they gave me which is the hydraXC module on the eval board and a zip file containing the HydraXC user manual and something that looks like a sample project. Within the zip file in that sample project there is a folder with 2 files: top.bit and image.bin. What I did first was i formatted the sd card to fat 16 and then copied the 2 file on it. Inserted the sd card into the hydra and powered on. but nothing happens. shouldn't I see some output on the serial interface? When I generate a bitstream with EDK I follow the same procedure right? Copy onti the sd card and power on? Btw: I followed your link but either I'm blind or the site does not contain any manuals or sample projects. thanks urbanArticle: 131562
JosephKK wrote: > On Fri, 18 Apr 2008 20:22:49 GMT, Joerg > <notthisjoergsch@removethispacbell.net> wrote: > >> Joel Koltner wrote: >>> "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message >>> news:KD6Oj.9778$2g1.2542@nlpi068.nbdc.sbc.com... >>>> That is strange. Normally they should have known this guy inside out before >>>> even offering tenure if that's what his new position entails. >>> I believe they did know him inside and out, were happy with his performance, >>> and that's why it happened: They had already decided they were going to offer >>> him the promotion, but some standard procedure required getting a student >>> evaluation as well... so they had to find someone who was willing to write up >>> a positive one. I just think it's strange that they bother getting a student >>> evaluation when their minds are already made up... since it then puts them in >>> the rather awkward position of having to say, "Please write us a good >>> evaluation, or if you don't feel you can, that's OK, we'll find someone >>> else..." Weird. >>> >>> Perhaps they'd do better to ask a handful of students to write up objective >>> evaluations without the pressure of "...but, um, it has to be positive?" -- >>> and then culling any that were negative? :-) I suppose they're stuck in a >>> way... being tied to the government (they're a land-grant university) means >>> they have to follow lots of procedures that regular businesses don't. >>> >>> Regarding the nice retirement packages... my understanding was that state >>> workers ended up with rather cushy retirement packages in exchange for having >>> to accept noticeably below-average salaries (relative to private industry) >>> during their working years. In Oreogn we have the PERS (Public Employee >>> Retirement System) which used to work this way, but the "cushy" benefits were >>> signifcantly reduced via the ballot box when some interested parties pointed >>> out how much better PERS was than what those folks in private industry get. >>> Hence you now have a system where public employee pay still isn't competitive >>> with private industry and now the retirement isn't either! This was a common >>> topic of complaint by the professors (that you'd get to know well enough) when >>> I was in grad school; a significant number left for private industry during >>> that time, and I certainly coudn't blame them. >>> >>> That being said, I don't know enough to evaluate whether or not public jobs >>> are still attractive when you look at the total package -- some people would >>> argue they are and that PERS benefit reductions were just "corrections" to a >>> system that had become too "generous" in its compensation. >>> >> All I know from here (CA) is that their benefits are mind-boggling. > OK lets get to that. > >> Paid sick leave, > Not particularly uncommon until you get to low end hourly. Standard > for engineers since WWII. > Most people I know don't. >> fat disability payments where lots of people tried and >> succeeded to be declared "disabled", > Yes there has been abuses. > Big time. I've seen lots of it. People who collected fat checks because of back injuries and then personally erecting retaining walls and stuff. IMHO there is an utter lack of enforcement. Hey, didn't even Spike Helmick try to collect a fat pension "upgrade" claiming he fell off his armchair? >> cradle-to-grave medical with hardly any co-pay. > When i worked for private as an engineer it was $5 for office visit, > $20 for lab, $5 per prescription. Today with State of CA it is $10 or > more for office visit, $0 for lab, $5 to $25 per prescription. It > increases in retirement. Then Medicare is supposed to kick in and > relieve much of the State burden. If you are 65 or older and don't > like what you have try Medicare and see how well you like that. > I must pay $65 for an office visit. Plus the first $2700 (per person!) per year out of pocket, else the premiums become unbearable. A lot of engineers I know how no health insurance at all because they can't afford it any longer. >> The latter alone will saddle our communities with previously >> unheard of debt. >> Oh, and then lots of jobs have the retirement benefit >> tied to the last work year. So, folks have themselves transferred into >> high-cost areas such as the Bay Area for 13 months or so, then move >> back. That ratchets their monthly checks up substantially, until their >> dying day. That ain't right. > It has been changed to the highest paid three years average in the > last ten. And it now takes ten years to become "vested", instead of > five. > That's good but still not fair compared to people in non-gvt jobs. > Now, you have been reading my stuff for some years now, do you think i > am a doofus parading as an engineer? When i was hired some 15 years > ago a PE could only expect about $5000 a month in State service. What > was your monthly average then. What was it 5 years ago? What is it > today. CA State pay rates for engineers and almost all others is a > matter of public record. Try looking them up for yourself. You would > do well to start with www.spb.ca.gov. Better still, compare them to > County and City rates for the last 20 years. And finally note that > for most cases the State does not give you a better paycheck based on > where the job is, let alone where you live. > > 80 percent to 90 percent of half to two thirds of what a private > engineer can make ain't all that much. You may get a lower top > percentage, but it is / was based on a much better salary. > Half? $5k/mo is about what engineers in industry made 15 years ago. But the real perks are in other jobs where the legislature has caved in to the unions. Prison guards etc. A while ago the news reported the staggering number of applications sent in. It may not be a fun job but it sure must have become a plum job. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131563
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On Apr 22, 8:22 am, Philip Potter <p...@doc.ic.ac.uk> wrote: > Stef wrote: > > In comp.arch.fpga, > > jjlind...@hotmail.com <jjlind...@hotmail.com> wrote: > >> Hello, thanks for responding to my post. Sorry for me confusing > >> everyone. Let's say I have a large design that has lots of inputs and > >> outputs and let's say I'm only interested in a simulation consisting > >> of only a few inputs and outputs. When I run ModelSim it will add in > >> all the inputs/output of the module I am simulating, thus adding in > >> all of the inputs and outputs of my design into the waveform window. I > >> was hoping I could configure something so when the simulation finishes > >> it would display the signals I'm interested in. Is that possible? I'll > >> also try the other newsgroup and see if anyone has a solution. > > > I don't believe modelsim automatically adds signals to the wave window, > > it also does not automatically run a simulation. > > How do you start modelsim? Your environment may start modelsim with a > > scriptfile (.do) and it may have generated a default for this script > > that adds all your IO to the wave window and runs the simulation to > > completion. > > > If you can find that script, you can probably modify it to suit your > > needs. > > Alternatively, you can just delete the signals you don't want from the > wave window after they've been added. I've seen a reference design once that used a .tcl script to display on the simulation window only the signals of interest but I couldn't figure out how they called the .tcl script. When I run ModelSim I simply change the directory to the directory of my verilog design and the testbench. I then compile and simulate the design using the testbench. I would like to learn how to use scripts to run the simulation. If anyone can suggest a good web site that covers things like this please let me know. Thanks, joeArticle: 131565
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Article: 131566Thorsten Kiefer wrote: > Hi, > > i get the following error messages : > HDLParsers:800 - "/home/thorsten/work/xilinx/vgatest1/vga_test.vhd" > Line 66. Type of mousex_reg is incompatible with type of MXINIT. > ERROR:HDLParsers:800 - > "/home/thorsten/work/xilinx/vgatest1/vga_test.vhd" Line 67. Type of > mousey_reg is incompatible with type of MYINIT. > > using the unsigned() conversion function doesnt work either. > > Best Regards > Thorsten Hi Thorsten, Try http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf Also, you might be better asking this sort of thing on comp.lang.vhdl . HTH., Syms.Article: 131567
Syms, Morose vode? AustinArticle: 131568
On Apr 25, 8:06=A0am, Thorsten Kiefer <webmas...@nillakaes.de> wrote: > Hi, > when i synthesize this : You need to use the to_unsigned function in ieee.numeric_std. You can't simply cast an integer to an unsigned because in order to do so, that function would need to know how many bits of precision you would like (which is what the second parameter in the 'to_unsigned' function defines). Change to the following... mousex_reg <=3D to_unsigned(MXINIT, mousex_reg'length); mousey_reg <=3D to_unsigned(MYINIT, mousey_reg'length); KJArticle: 131569
austin wrote: > Syms, > > Morose vode? > > Austin I was inspired by this:- http://www.youtube.com/watch?v=q9v3C08oLqA Sorry! Syms.Article: 131570
"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message news:rslQj.11920$GE1.7212@nlpi061.nbdc.sbc.com... > But the real perks are in other jobs where the legislature has caved in to > the unions. Prison guards etc. A while ago the news reported the staggering > number of applications sent in. It may not be a fun job but it sure must > have become a plum job. I know of a friend of a friend who's a prison guard, and besides the money, one nice option they have here in Oregon is that they can completely swap hours with their co-workers. This guy will take a couple months off during the summer and then work a bunch of 60 hour weeks the rest of the year for someone else who's then taking his few months off. Definitely some advantages to having a job where you're largely interchangeable with any of your co-workers and are being paid by the hour! Of course, prison guard jobs are kind of like mining jobs... usually it's good pay and no problems, but when something does go wrong you're rather likely to end up dead...Article: 131571
"JosephKK" <quiettechblue@yahoo.com> wrote in message news:o20314pl6k3565m260fkarco8n63bpb5hb@4ax.com... > That does sound specific to one particular tool (vendors's software). Yeah, after Dave posted that I checked and unfortunately Pulsonix can't do it... although it's "close enough" that I imagine adding it as a feature wouldn't be particularly difficult. I think it's a good idea -- hopefully it will show up in more tools over time.Article: 131572
Hi all, Im building a custom IP that needs to write data to DDR Ram on the XUPV2P board (Virtex 2 Pro). Basically need to dump data from a 16kb BRAM to DDR in burst mode. Data width is 64bits, which is the same as the PLB DDR Controller Im using. Can someone point me to an example that shows how to write to the PLB bus? The PLB IPIF example was confusing and I couldnt follow it completely. Maybe a more noob friendly way example would help. Some sample code to get me started would be great :) TIA. Raghu. PS : 1st post here. Yay!Article: 131573
Hi there, I am trying to get a design passing the timing to run at 622.08MHz clock on a Cyclone III device. All the critical paths has been pipelined so there is only one level of combinational logic inbetween registers and the fitter and synthesizer's setting has been tuned up for performance oriented according to the QII handbook. But still, some paths failed because of the propagation delay on the interconnections between LABs. I know I can set minimum delay constraints on these pathes to force the fitter place those LEs close together, but I am afraid some other paths will be placed apart on the chip and fail the timing. And I will have to put constraints on them and repeat this cycle over and over. Now I am trying different fitter seeds to see if there is a lucky initial placement plan will work magically. But, are there any smart way to do this? And, is there anyway to set the fitter to give higher priority in place and route to high frequency clock domains? BTW, the design has already passed the timing for the fast timing model, but not for the other two slow timing model. Does that mean the design may work in some compilation, but may not work in some worse cases? Thanks in advance and any advice will be highly appreciated. HuaArticle: 131574
Thorsten Kiefer wrote: > Hi, > when i synthesize this : > > > > architecture Behavioral of vga_test is > constant MXINIT : integer := 100; > constant MYINIT : integer := 100; > signal mousex_reg,mousey_reg : unsigned(9 downto 0); > signal mousex_next,mousey_next : unsigned(9 downto 0); > .... > begin > process(clk,reset) > begin > if reset='1' then > rgb_reg <= (others=>'0'); > mousex_reg <= MXINIT; > mousey_reg <= MYINIT; > elsif rising_edge > ...... > > i get the following error messages : > HDLParsers:800 - "/home/thorsten/work/xilinx/vgatest1/vga_test.vhd" Line 66. > Type of mousex_reg is incompatible with type of MXINIT. > ERROR:HDLParsers:800 - "/home/thorsten/work/xilinx/vgatest1/vga_test.vhd" > Line 67. Type of mousey_reg is incompatible with type of MYINIT. > > using the unsigned() conversion function doesnt work either. Use the to_unsigned() function defined in numeric_std. Philip
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