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In article <yc6dnTsXAsXiJonVnZ2dnUVZ_gSdnZ2d@earthlink.com>, mike.terrell@earthlink.net says... > > Joerg wrote: > > > > Research specialists making >10k/mo? That is a rather decent salary. > > Most researchers in industry do not make that much. > > > > Also, you have to consider that you guys have what almost amounts to > > tenure. When the budget is tight the taxpayer is expected to jump in. > > When the budget is tight in industry layoffs follow in due course. Right > > now EE is on a roll but remember 2001-2004? How many folks with masters > > degrees did low-wage jobs at hardware stores selling weed eaters and > > circular saws? I've met some. That (usually) does not happen to people > > in public service positions. > > > Marion County, Florida recently laid off about half of it's building > inspectors and support staff. The trucks they drove were auctioned off > a few days ago, as well. That money will go back into the county's > general fund, as well as the unused salaries. One of the local sheriffs just handed out pink slips to about half his deputies and staff. He's looking for more tenants for his hotel, to pay for those remaining. Maybe he should ask Joe Arpaio for some help. -- KeithArticle: 131651
krw wrote: > > One of the local sheriffs just handed out pink slips to about half > his deputies and staff. He's looking for more tenants for his > hotel, to pay for those remaining. Maybe he should ask Joe Arpaio > for some help. Some cities are claiming that they are going to have to lay off the police, close the fire departments, and stop ambulance services after not getting the huge increases they demanded. It is going to be a slaughterhouse at election time. -- http://improve-usenet.org/index.html Use any search engine other than Google till they stop polluting USENET with porn and junk commercial SPAM If you have broadband, your ISP may have a NNTP news server included in your account: http://www.usenettools.net/ISP.htmArticle: 131652
austin wrote: > swissi, > > I have no idea what you are trying to tell me. > > Austin Hey Austin, You remember a day or two ago, in all seriousnes, you said I need to treat your future customers with a little patience? Let me know when I can be rude to this one! To be honest, I don't think they're a 'keeper'. Thanks, Syms.Article: 131653
Hi, I'm the same problem that you, I can't connect PPC with FSL. I succed to connect Microblaze with HW block, but using PPC it isnt the same case. Can you help me by disceape me solution that you have found. think youArticle: 131654
On Apr 25, 4:49 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > laura wrote: > > I have an array of N switches . Initially all are OFF. > > Somebody turns them ON in some order. It is possible that more > > switches are turned ON in the same moment. > > Depending on your definition of 'the same moment', and realizing > that real switches often bounce. > > > I need a device which shows me the order in which the switches were > > turned ON. For instance the device should give me: 4,3,1,5,2 (this is > > the order in which the switches were turned ON). > > Latch the switch inputs, latch the latch output, and compare them. > (Use XOR gates.) A priority encoder will tell you which one > changed. More logic will detect any multiple switch transitions, > but if you have a fast enough clock, those should be rare. > > > The way in which the output is shown in not important. It must be > > simple to read (by a human, computer, etc). > > It is important that the device is able to handle the turned ON (in > > the same moment) of the multiple switches. > > Are you only detecting ON transitions, and ignoring any that go OFF, > then on again? In that case, have the second latch only detect > ON transitions. You will need a reset signal to start over again. > The original problem description seems to imply that the reset would happen when all switches are turned OFF. > My favorite switch/logic puzzle from many years ago: > > You have a long hallway with N lights. There is a switch at each > end, and one between each light (N+1 switches total), such that you > can walk down the hall flipping switches. Each one will turn on the > light in front of you, and turn off the light behind. > > Assuming only switches, light bulbs, and a power source (no computers > or logic gates), what is the simplest switch configuration needed > to make this work. (For example, SPST, SPDT, DPST, DPDT, etc.) > How should the switches and lights be wired up? > > -- glen Good puzzle. Everyone knows the one where each switch turns on or off all of the lights (sometimes known as the stairway landing switch problem). Cheers, GaborArticle: 131655
What kind of design are you running at 620MHz ? Rgds AndreArticle: 131656
On Apr 26, 10:33 pm, Alan Nishioka <a...@nishioka.com> wrote: > swissiyous...@gmail.com wrote: > > is someone has the code of CRC (cyclical redundancy check) that xilinx > > use in the bitstream ? is it a simple CRC ( the XOR of words ) ? > > try > <http://www.xilinx.com/support/documentation/application_notes/xapp151...> > > Alan Nishioka I found this one to be very useful: http://www.easics.be/webtools/crctool In case you're trying to construct the FCS of an ethernet packet: please note it is not equal to the CRC, you have to do some bit/byte juggling to convert CRC to FCS. BartArticle: 131657
Symon, I sometimes feel impatient, and react poorly to posts where 10 minutes with Google, and the poster would have their answer. However, I feel that we should all be patient. We were all ignorant at one time. There is no supported forum for students, and those wishing to learn about FPGAs. One of their only resources is this newsgroup. As for semaphores and Aldiss Lamps, no, I am not proficient in either. But we did use an AM modulated laser pens one field day to communicate a few Km between hilltops (with 1 cm^2 solar cell demodulators). AustinArticle: 131658
Symon, I had no intent to be rude! I am honestly saying I do not understand. I am trying the best I can, but for some reason (perhaps my defective brain cells), it isn't making any sense. If I have offended anyone, I apologize! I am just trying to understand what is being asked. AustinArticle: 131659
On Apr 25, 2:31 pm, Kevin Neilson <kevin_neil...@removethiscomcast.net> wrote: > KJ wrote: > > On Apr 21, 1:11 pm, Kevin Neilson > > <kevin_neil...@removethiscomcast.net> wrote: > > >> Yes, my son--you are quickly learning the lameness of VHDL. A number > >> isn't a number--sometimes it must be in single quotes, sometimes in > >> double quotes, and most often expressed in binary, just as the ancients > >> used to write. And almost never can you use a number directly, but must > >> convert it from one arcane type to another. -Kevin- Hide quoted text - > > > On the first day, the VHDL gods created 'integer', 'natural', etc. and > > created ways to easily specify such numbers in any base, and saw that > > it was good...and the VHDL gods said, go forth and use these types for > > they are of my creation and they are good....but the unbelievers who > > think every number will potentially be bigger than 32 bits on each and > > every design that they create and the scallywags that created > > std_logic_arith refused to use 'integer' and instead used > > std_logic_vectors to perform arithmetic and then cursed the VHDL > > language for the numerous type conversions that they themselves > > brought down upon themselves.... > > > KJ > > There is some truth to that. I am usually hamstrung by requirements > such as "all ports must be std_logic_vectors", which is a human failing > and not technically a shortcoming of the language. Nonetheless, I > prefer a language which never requires cumbersome conversions and yet > will simulate x's and z's if I need it to. -Kevin While I also don't like archaic conventions such as requiring SLV on all ports, I prefer a language (VHDL) that catches and identifies problems with conversions, data widths, etc. before simulation. If I have to get a little more verbose, (and get a lot more flexibility in the bargain), that is time well spent. AndyArticle: 131660
On Apr 25, 9:31=A0am, "Joel Koltner" <zapwireDASHgro...@yahoo.com> wrote: > "JosephKK" <quiettechb...@yahoo.com> wrote in message > > news:o20314pl6k3565m260fkarco8n63bpb5hb@4ax.com... > > > That does sound specific to one particular tool (vendors's software). > > Yeah, after Dave posted that I checked and unfortunately Pulsonix can't do= > it... although it's "close enough" that I imagine adding it as a feature > wouldn't be particularly difficult. =A0I think it's a good idea -- hopeful= ly it > will show up in more tools over time. There's a new tool on the market for this - Taray's 7 Circuits http://www.tarayinc.com/ You do minimal floorplanning right in the tool, and it optimizes the I/ O assignment for the specific electrical characteristics of the device, and the arrangements of the other major devices the FPGA is connected to. Works with both Cadence and Mentor schematics. The nice part is that the EE doesn't have to actually do any PCB layout, but it makes the layout flow much better (fewer vias, layers, shorter connections, etc). -BrianArticle: 131661
Hua wrote: > Hi there, > > I am trying to get a design passing the timing to run at 622.08MHz > clock on a Cyclone III device. > > All the critical paths has been pipelined so there is only one level > of combinational logic inbetween registers and the fitter and > synthesizer's setting has been tuned up for performance oriented > according to the QII handbook. But still, some paths failed because of > the propagation delay on the interconnections between LABs. I know I > can set minimum delay constraints on these pathes to force the fitter > place those LEs close together, but I am afraid some other paths will > be placed apart on the chip and fail the timing. And I will have to > put constraints on them and repeat this cycle over and over. > > Now I am trying different fitter seeds to see if there is a lucky > initial placement plan will work magically. But, are there any smart > way to do this? > > And, is there anyway to set the fitter to give higher priority in > place and route to high frequency clock domains? > > BTW, the design has already passed the timing for the fast timing > model, but not for the other two slow timing model. Does that mean the > design may work in some compilation, but may not work in some worse > cases? > > Thanks in advance and any advice will be highly appreciated. Altera parts aren't my area of expertise, but I was curious about this question so I poked into the Cyclone III datasheet. You should have a look at Clock Tree Specifications, Table 1-18 in the datasheet, as the part is not capable of running this fast. The maximum clock frequency is 500 MHz. Ed McGettigan -- Xilinx Inc.Article: 131662
austin <austin@xilinx.com> wrote: > Are you just trying to check that we are using AES256? I think it's this that he's trying to do. G.Article: 131663
The nano semiconductor is supposed to give 50 times lower power consumption aswell as significantly faster switch times to work with radio at 60 GHz. Any comments on plausability, impact etc..? http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel5/55/4455672/04435099.pdf?isnumber=4455672&arnumber=4435099 http://www.qunano.com/Article: 131664
sky465nm@trline4.org wrote: > The nano semiconductor is supposed to give 50 times lower power consumption > aswell as significantly faster switch times to work with radio at 60 GHz. > > Any comments on plausability, impact etc..? > > http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel5/55/4455672/04435099.pdf?isnumber=4455672&arnumber=4435099 > > http://www.qunano.com/ > Well, it is InAs, not silicon, so expect cost to be substantially higher, if there even IS any commercial development of this material. Vertical channels is a cute idea, it makes putting the gate on all 4 sides of the channel simple. It also means (I think) that you have to grow the semiconductor on TOP of at least one layer of metal. This is counter to all the commercial semi manufacturing processes. It may be suitable for RF front ends or other exotic requirements, but not likely to soon be applied to CPUs, FPGAs, etc. JonArticle: 131665
Hello Group,
I have done a couple of small fpga projects with verilog. I am
looking for some follow-up fun projects to increase my experience and
exposure to FPGA/verilog?
I am thinking of interfacing with the memory
blocks on the xilinx board and do some memory IO there. I've recently
done a music player through serial interface. I want to use the
onboard USB interface or ethernet interface, but I am not sure how to
proceed. The usb interface is currently used to program the board and
the ethernet interface seems like it would require a significant
amount of work to get a ethernet core and tcp/ip stack programmed.
Your input is welcome, thanks!
Fei
Article: 131666I would like to automatically embed the Xilinx compile (synthesize) time into my FPGA. I have a script file that can put the time and date into my Verilog code. I would like to automatically call that script file from the Xilinx ISE everytime i run the synthesizer. Is there anyway for the ISE to call an outside routine (other than running the whole thing from a command line without the ISE) ? Is there an easier way to embed date and time in the FPGA?. I want to make it as easy as possible otherwise no one will do it. That is why I would like to have it hook right into the ISE. Suggestions apreciated, BobArticle: 131667
freeagent.20.oracle@xoxy.net wrote: > I would like to automatically embed the Xilinx compile (synthesize) > time into my FPGA. I have a script file that can put the time and date > into my Verilog code. > > > Bob Hi Bob, You could use data2mem to put the time into a BRAM after the compile is complete. Dunno if that helps you? Cheers, Syms.Article: 131668
Rob, Line 1 of my first reply. One last comment, there is no 'in-rush current', the current is what is needed, and does not vary while powering on. 1.65 amperes is primarily static leakage at the highest junction temperature, fastest silicon process, and highest Vccint. It is NOT something special, or unusual, required ONLY during power on. After configuration, if anything, the current will be more as the IOs and clock trees and the fabric begins to operate. AustinArticle: 131669
Schematics are now available on our website for our low cost development board Darnaw1. These and other materials for this board are linked on http://www.enterpoint.co.uk/component_replacements/drigmorn1.html. John Adair Enterpoint Ltd.Article: 131670
hi folks ! Very interesting question , me too i want to be sur that my bitstream is encrypted with aes 256 cbc . how can i check this ?! Austin u told us one time about how to make the difference between encrypted and unencrypted bitstream ... mowaArticle: 131671
mowa, The first, and most obvious difference, is that an unencrypted bitstream is mostly all 0's. There are less than 10% of the bits that are set to 1's in a bitstream. Identifying the structure of the bitstream is not all that tough: 1312 bit frames in V4 and V5, 41 frames for a column of CLB's, locations of BRAM data, etc. For example, place all BRAMs in a design with initial values of 0xAAh, and then the 10101010 binary patterns will pop out for the BRAM blocks. When encrypted, there will never be a block of 10101010 the length of a BRAM any longer (as it will have been encrypted) The second, and fairly obvious difference, is that encryption tends to make things look like noise, so an encrypted bitstream has ~ 50% 1's and 50% 0's (looks like a random string of 1's and 0's). Nothing in the bitstream will "make any sense" or correlate with anything that you think it should be (i.e BRAM contents as above). To prove to yourself that the encryption which is performed is AES256 per the NIST standard, one has to read how we format the bistream: what comes before the encrypted part, and what follows after the encryption ends and then to decrypt that middle part using a NIST c or Fortran program with the key you used to encrypt with. The AES256 encryption has been confirmed by more than one third party, so depending on how paranoid you are, you may or may not want to duplicate this work (although it is not hard to do, just takes some programming skills). AustinArticle: 131672
Thanks for all your answers, here in my country we use 750C at university. "-jg" <Jim.Granville@gmail.com> wrote in message news:a1642d33-7d26-4a46-a73d-6ae7138105bf@f24g2000prh.googlegroups.com... > Julio Espada wrote: > >> Hi! >> >> I'm looking for the Atmel ATF750C library for Proteus but I'm unable to >> find >> it on both Atmel & Labcenter sites. Does anyone know where can I find >> this ? >> Or perhaps, any other application that can simulate the ATF750C ? >> >> Thanks in advance for any help. > > If you want mixed mode Spice simulation, then you will need > a Spice flow that supports D/T FF and AND/OR PLD logic. > > If you just want functional boolean simulation, the Atmel > tools can support that. > > The 750 is similar to a 2 x 22V10 (but with .T register option). > > Some Spice flows support Boolean Eqn, or other methods of > Logic - I see Proteus mention a JED pathway, so you need > to find the intermediate format, that the JED is turned into, and > try and work with that. > > -jg > >Article: 131673
In trying to fix a bug with Ethernet MAC/phy operation, I came across AR 24494 which mentions "silicon rev CES4 or later". How can one determine the silicon rev? I have two different parts marked as follows: Virtex4 XC4VFX12 FF668AGQ0513 -- does Q0513 mean 13th week of 2005? DD15537A 10C-ES Virtex4 XC4VFX12 FFG668DGQ0733 DD1466805A 10C My guess is that the first part is pre CES4 and the last part is post CES4. Can someone explain the system here? I thought I had seen Peter explain the sequence of silicon rev numbers here before, but I can't seem to find it in the archives or on xilinx.com. thanks, -Jeff From invalid@dont.spam Mon Apr 28 20:04:15 2008 Path: flpi142.ffdc.sbc.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!bigfeed.bellsouth.net!news.bellsouth.net!cycny01.gnilink.net!spamkiller2.gnilink.net!gnilink.net!trndny03.POSTED!933f7776!not-for-mail From: Phil Hays <invalid@dont.spam> Subject: Re: How to embed time and date in Xilinx FPGA? User-Agent: Pan/0.14.2.91 (As She Crawled Across the Table) Message-Id: <pan.2008.04.29.03.04.14.423049@dont.spam> Newsgroups: comp.arch.fpga References: <d8dc14p130ogqm5fjvb00aeufpucrbu34g@4ax.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 67 Date: Tue, 29 Apr 2008 03:04:15 GMT NNTP-Posting-Host: 71.112.133.22 X-Complaints-To: abuse@verizon.net X-Trace: trndny03 1209438255 71.112.133.22 (Mon, 28 Apr 2008 23:04:15 EDT) NNTP-Posting-Date: Mon, 28 Apr 2008 23:04:15 EDT Xref: prodigy.net comp.arch.fpga:144107 X-Received-Date: Mon, 28 Apr 2008 23:04:16 EDT (flpi142.ffdc.sbc.com) freeagent.20.oracle wrote: > I would like to automatically embed the Xilinx compile (synthesize) time > into my FPGA. I have a script file that can put the time and date into my > Verilog code. > > I would like to automatically call that script file from the Xilinx ISE > everytime i run the synthesizer. Is there anyway for the ISE to call an > outside routine (other than running the whole thing from a command line > without the ISE) ? > > Is there an easier way to embed date and time in the FPGA?. I want to make > it as easy as possible otherwise no one will do it. That is why I would > like to have it hook right into the ISE. My suggestion would be to use the exported Tcl script from ISE 10.1. This would allow you to use the ISE GUI, and do any other function in the script. There would be a fair amount of setup, but after that it would be easy, just click on an icon to launch ISE. To set this up, follow the directions below. Open Project Navigator and export a Tcl script to the default name and location. I suggest having the top radio button checked: (All properties with complete script). Then exit Project Navigator. Copy this script to the src directory. Download this script to the same directory. http://mysite.verizon.net/fastfpga/project.tcl Edit the project.tcl script to make the names match, and to add in the date and time script. Save the bld directory if there is anything in it. This script does assume that none of your source files are in the bld directory. Assuming Windows, create a shortcut (Linux "Launcher") with a command of: xtclsh path_to_your_project\src\project.tcl Set the directory to start in to: path_to_your_project\src\ Double click the shortcut. Script takes about 30 seconds to run (YMMV), then launches ISE. Assuming you don't want a shortcut or launcher (Also easier to debug if the shortcut doesn't work): Open a terminal window. cd path_to_your_project/src/ xtclsh project.tcl Every time you run the project.tcl script, it creates a temporary .ise file. You can save settings by just "project => generate Tcl script..." again, and the saved settings will be copied back to the src directory. If you don't save settings, the script in src doesn't change. Hope this is useful to you. -- Phil HaysArticle: 131674
"austin" <austin@xilinx.com> wrote in message news:fv5dn9$7i92@cnn.xsj.xilinx.com... > > One last comment, there is no 'in-rush current', the current is what is > needed, and does not vary while powering on. 1.65 amperes is primarily > static leakage at the highest junction temperature, fastest silicon > process, and highest Vccint. It is NOT something special, or unusual, > required ONLY during power on. After configuration, if anything, the > current will be more as the IOs and clock trees and the fabric begins to > operate. Austin, I think there will be a flame of responses to what you have just said! If that's the case, this current has to be clearly specified as maximum static leakage and NOT as a power-up requirement. I think there are lots of boards out there, which violate this spec, because they were designed for this as the maximum total current at best, based on other data sheet values, power calculator reports, and actual measurements. What's the point of using your power tools if they report static current value, which is 2-5 times less than the spec?! I've just run the XPower Estimator off of your web site for XC4VFX40, FF1152, commercial, maximum process, 1.26V core voltage, 78C ambient temperature with no air flow (which gives 84.6 C junction temperature). Under these conditions the reported Iccq is 0.723 A. Even at 100 C junction for the industrial part the projected current is only 0.895 A /Mikhail
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