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jraj.thakkar@gmail.com wrote:
> My background is in Software Engineering C,C++,Java and Unix. I am
> getting started with VHDL and Verilog. What is the good way/books/
> websites/training to get started? I have B.S. and M.S. in Computer
> Engineering.
If you are excited about flashing the lights on
a physical circuit board, start with that,
and run all the demos.
If you are excited by writing clean synthesis code,
testing it algorithmically,
and having it work the first time,
start with a verilog/vhdl simulator.
Also, what is the learning curve in VHDL and Verilog?
About the same as C, C++, Java or Unix.
-- Mike Treseler
Article: 131901Hi, I have a basic question. Is is possible in the xilinx ISE enviroment to make a verilog wrapper of some VHDL code. I don't want to recode it in verilog. Thanks RobArticle: 131902
On May 6, 9:22 am, Simon <wlpstx...@gmail.com> wrote: > Hi, > > This is my first time install Xilinx ISE in CentOS, I thought it's the > free clone of RHEL. But I cannot find the ISE in the application menu > list. I don't mean I have to have it, but just don't know if it's the > default like that. I don't know if it's showing in the RHEL or your > CentOS. I am pleased to see how close the CentOS to RHEL. Thank you > for your time and reply. > > Simon As Xilinx tools are installed appart from the system package manager there is no entry in the application menu. You have to set up you environment to be able to use the tools. source /opt/Xilinx/10.1/ISE/settings32.sh or source /opt/Xilinx/10.1/ISE/settings32.csh You can maybe set up the application menu, but is it really important ?Article: 131903
On May 6, 3:38=A0pm, egadget1 <rnu...@gmail.com> wrote: > Hi, > > =A0I have a basic question. =A0Is is possible in the xilinx ISE enviroment= > to make a verilog wrapper of some VHDL code. =A0I don't want to recode > it in verilog. > > Thanks > Rob Never mine I figured it out. RobArticle: 131904
egadget1 wrote: >> I have a basic question. Is is possible in the xilinx ISE enviroment >> to make a verilog wrapper of some VHDL code. I don't want to recode >> it in verilog. >> >> Thanks >> Rob > > Never mind I figured it out. The rule is, you have to tell us what you did ;)Article: 131905
Hello. We need a boards with 4 or 6 or even 8 identical FPGA chips installed, each one should be mid-range Altera Cyclone II or III, let say, each chip should contain between 30.000 LEs and 60.000 LEs. It can be Xilinx Spartan, but board should contain 4-6 or 8 Spartan chips with roughly same logic capacity. Board should contain power supply, some flash ROM and RAM for Altera Nios or Xilinx MicroBlaze, FPGA configuration loader and USB port. A lot of various FPGA kits are offered via Internet, but often they are contain only one FPGA chip. Because we demand only small quantity of such boards (maybe 10 or even 20, but unlikely more), we cannot order our own boards, so we're looking for ready-made ones, with reasonable cost. It is also interesting, if it is possible to order some ready-made boards with the same specifications but for PCIe instead of USB, but also with reasonable cost. I'll be thankful if someone can drop me an URL to something we're looking for: climber.tim@gmail.comArticle: 131906
Why? What is it you are trying to show, prove, or do? It would be nice to know. AustinArticle: 131907
Pico Computing (http://www.picocomputing.com/) has done some interesting work with multi-FPGA kits. At a Xilinx X-Tech event, they had a PCIe board with 15 S35000s. I have never done business with them and can't make any other comments about their quality. - NathanArticle: 131908
climber.tim@gmail.com wrote: > It can be Xilinx Spartan, but board should contain 4-6 or 8 Spartan > chips with roughly same logic capacity. Um, what would be wrong with 4 Spartan starter kits and some duct tape? G.Article: 131909
Suggestion: if you are using XST (or any other synthesis tool) and have Xilinx's PlanAhead, you can bring in an NGC/EDIF and view the schematic with PlanAhead's viewer. I just started using it and find that it's pretty good. -KevinArticle: 131910
I'd like to infer a DSP48 in XST and can't find a template that will
infer all of these opmodes:
P=M
P=M+C
P=P+M
P=P-M
(where M=A*B)
I can get XST to do any of these, one or two at a time, but when I try
to do all at once it adds a bunch of fabric. Any suggestions? The code
below, for example, properly connects up the ALUMODE pins (in a V5) for
the add/subtract function, but the mux that should be inferred as the
the DSP48's Z mux gets put in fabric instead, so P gets routed through a
fabric mux which feeds into C.
-Kevin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity xst_mac is
port (clk, reset, sel, add_sub: in std_logic;
A, B : in signed(17 downto 0);
C : in signed(47 downto 0);
P : out signed(47 downto 0));
end xst_mac;
architecture synth of xst_mac is
signal mult : signed(35 downto 0);
signal accum : signed(47 downto 0);
begin
process (clk)
begin
if (clk'event and clk='1') then
if (reset = '1') then
accum <= (others => '0');
mult <= (others => '0');
else
if (sel='0') then
accum <= C + mult;
elsif (add_sub='1') then
accum <= accum + mult;
else
accum <= accum - mult;
end if;
mult <= A * B;
end if;
end if;
end process;
P <= accum;
end synth;
Article: 131911On May 7, 12:11=A0am, austin <aus...@xilinx.com> wrote: > Why? > > What is it you are trying to show, prove, or do? > > It would be nice to know. It is most cost-optimal for crypto-tasks, if I'm correct, of course. Like it was done there: http://www.copacobana.org/faq.htmlArticle: 131912
climber.tim@gmail.com wrote: > It is most cost-optimal for crypto-tasks, if I'm correct, of course. > Like it was done there: > http://www.copacobana.org/faq.html Ah, ok then, 120 Spartan starter kits and a bigger roll of duct tape :) For something so massively parallel and where each FPGA presumably spends almost all of its time operating independently, I would think some cheap off-the-shelf single-FPGA module in quantity might actually be the easiest way to go. Probably not a problem to hook up 120 USB devices to a PC to control them or whatever. Might get a little warm though. G.Article: 131913
Not quite a single board solution but we can offer a stacked array of boards over a number of our products that fit together nicely. Have a look here http://www.enterpoint.co.uk/moelbryn/overcoat.html. This is a build to order option and can be done easily on our Broaddown2, Raggedstone1, Drigmorn1, Broaddown4 boards. It may also be possibly to stack our Darnaw1 module (PGA) but we have never bought the socket for this as yet so that would need to be confirmed. Also worth considering is our Hollybush1 product - http://www.enterpoint.co.uk/moelbryn/hollybush1.html. Again a stacking approach but this time the standard PCI104 connectior can be used in a dedicated(non standard) fashion to interconnect the stack. All the pins on this interface can be any direction as defined by FPGA build and used as you like. Our OVERCOAT technique can also be used on this board to add 116 I/O on top of the PCI104 interface if more interconnect is needed. All that would be needed would be a power card to power the array and we are working on that and I think there are some products out there already for that. John Adair Enterpoint Ltd. On 6 May, 22:04, climber....@gmail.com wrote: > Hello. > > We need a boards with 4 or 6 or even 8 identical FPGA chips installed, > each one should be mid-range Altera Cyclone II or III, let say, each > chip should contain between 30.000 LEs and 60.000 LEs. > It can be Xilinx Spartan, but board should contain 4-6 or 8 Spartan > chips with roughly same logic capacity. > Board should contain power supply, some flash ROM and RAM for Altera > Nios or Xilinx MicroBlaze, FPGA configuration loader and USB port. > A lot of various FPGA kits are offered via Internet, but often they > are contain only one FPGA chip. > Because we demand only small quantity of such boards (maybe 10 or even > 20, but unlikely more), we cannot order our own boards, so we're > looking for ready-made ones, with reasonable cost. > It is also interesting, if it is possible to order some ready-made > boards with the same specifications but for PCIe instead of USB, but > also with reasonable cost. > I'll be thankful if someone can drop me an URL to something we're > looking for: climber....@gmail.comArticle: 131914
jraj.thakkar@gmail.com wrote: > Hi all, > > My background is in Software Engineering C,C++,Java and Unix. I am > getting started with VHDL and Verilog. What is the good way/books/ > websites/training to get started? I have B.S. and M.S. in Computer > Engineering. Also, what is the learning curve in VHDL and Verilog? If you are interested in processors, have a look at: "Digital Design and Computer Architecture" by D.M. Harris & S. L. Harris, Morgan Kaufmann After reviewing digital logic fundamentals they go on with showing the synthesisable subset of VHDL and Verilog, side by side. Then they talk about processor architectures and walk you through a simplified MIPS32 processor implementation. The book is very easy to read. Cheers, GuenterArticle: 131915
I am trying to write an sdio host controller. sdio is an extension to the sd/mmc protocol used on memory cards. It is used for pda peripheral devices, for example. Note that this question is about the sdio protocol, not the spi protocol that is part of the sdio/sd/mmc specification. I am able to send and receive a response on the cmd line, but when I send or request data, I never see it on the data lines. Specifically, cmd52 works for both read and write and I get the correct response. But while cmd53 responds on the cmd line, I never see activity on the data lines. Does anyone know what I am missing? Alan Nishioka alan@nishioka.comArticle: 131916
Kevin Neilson wrote: > I'd like to infer a DSP48 in XST and can't find a template that will > infer all of these opmodes: > ... Never mind--I don't think this type of inference is supported at the time. -KevinArticle: 131917
Lattice is holding a webcast today, Wednesday, May 7th, on our latest version of our FPGA software design tools "ispLEVER 7.1 FPGA Design Tool Technical Rollout." The presenter will be Troy Scott, from our software marketing group. If you're interested, the event takes place live at 11am Pacific, 18:00 GMT. In addition, you will be able to view this webcast archive on-demand, at your convenience, starting a few hours after the live event takes place. You can register by clicking: http://www.latticesemi.com/corporate/webcasts/isplever7.1fpgadesigntool.cfm Bart Borosky, LatticeArticle: 131918
On Wed, 7 May 2008 10:52:01 -0700 (PDT), bart <bart.borosky@latticesemi.com> wrote: >Lattice is holding a webcast today, Wednesday, May 7th, on our latest >version of our FPGA software design tools "ispLEVER 7.1 FPGA Design >Tool Technical Rollout." The presenter will be Troy Scott, from our >software marketing group. > >If you're interested, the event takes place live at 11am Pacific, >18:00 GMT. In addition, you will be able to view this webcast archive >on-demand, at your convenience, starting a few hours after the live >event takes place. > >You can register by clicking: >http://www.latticesemi.com/corporate/webcasts/isplever7.1fpgadesigntool.cfm > >Bart Borosky, Lattice To Lattice: We dumped Lattice over buggy compilers and dinky performance. Now that you're spamming our group, I'll make the ban permanent. To the group: Whenever anybody spams us, please 1. Blackball them as a vendor 2. Say bad things about their companies and products, preferably with lots of google-searchable keywords. John From webmaster@nillakaes.de Wed May 07 11:36:41 2008 Path: flpi142.ffdc.sbc.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin2!goblin.stu.neva.ru!newsfeeder.dynfx.net!weretis.net!news01.khis.de!feed.cnntp.org!news.cnntp.org!not-for-mail Message-Id: <4821f694$0$22077$6e1ede2f@read.cnntp.org> From: Thorsten Kiefer <webmaster@nillakaes.de> Subject: ps2 mouse protocol Newsgroups: comp.arch.fpga Date: Wed, 07 May 2008 20:36:41 +0200 User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 14 Organization: CNNTP NNTP-Posting-Host: 1136c9cd.read.cnntp.org X-Trace: DXC=H7\h=?\THj5B_=;Ija]Aa;WoT\PAgXa?1^U4Y3YFcPR?CWCf629N194Vfa3D?:k27;7L3;mO3M2E8b1=MN:mKEU4 X-Complaints-To: abuse@cnntp.org Xref: prodigy.net comp.arch.fpga:144382 X-Received-Date: Wed, 07 May 2008 14:36:08 EDT (flpi142.ffdc.sbc.com) Hi, I'm trying to communicate with the ps2 mouse. So I first force the ps2c line to '0' for 100us. Then I force the ps2d line to '0' and ps2c to high impedance. Now the mouse should take over the ps2c line and send a falling edge on ps2c. But it does not, and ps2c stays '1'. And thus my state machine infinitely waits for the falling edge. Can anyone help me with that ? Best Regards ThorstenArticle: 131919
John Larkin wrote: > > To Lattice: > > We dumped Lattice over buggy compilers and dinky performance. Now that > you're spamming our group, I'll make the ban permanent. > > > To the group: > > Whenever anybody spams us, please > > 1. Blackball them as a vendor > > 2. Say bad things about their companies and products, preferably with > lots of google-searchable keywords. > > John Was this really necessary? If there were technical webcasts from any of the big vendors, I'd like to know about them though preferably more than 8 minutes beforehand. If the posts of this nature got to be more than a couple a month from any one source I'd agree with the spam catagorization but it isn't that frequent. I'm disappointed that you had problems with them in the past and won't trust them for future designs because of your history; competition is almost always good. But is it reason to be publicly vocal? Kill-lists are easy to manage if bart's messages offend you. - John_HArticle: 131920
Eric Smith wrote: (snip) > Kevin Neilson wrote: >>That's interesting--I'm not even familiar with an "asynchronous >>processor". What does that mean? -Kevin > There's no central clock. At any given time, one particular "unit" > in the computer is active. When it completes its work, it sends a > pulse to the next unit that needs to do something, thus handing off > control. Sometimes also known as "self timed logic", and probably easier to search under that name. (snip) > There were quite a few asynchronous computers in the old days, but > the world settled on synchronous designs for various reasons. In recent > years there has been a resurgence of interest in asynchronous designs, > partly due to the possibility of power savings. There are still no > mainstream asynchronous processors, though. There are rumors of asynchronous functional modules, such as multipliers or dividers. That might make more sense in current systems than a completely asynchronous design. -- glenArticle: 131921
John Larkin wrote: > On Wed, 7 May 2008 10:52:01 -0700 (PDT), bart > <bart.borosky@latticesemi.com> wrote: > > >>Lattice is holding a webcast today, Wednesday, May 7th, on our latest >>version of our FPGA software design tools "ispLEVER 7.1 FPGA Design >>Tool Technical Rollout." The presenter will be Troy Scott, from our >>software marketing group. >> >>If you're interested, the event takes place live at 11am Pacific, >>18:00 GMT. In addition, you will be able to view this webcast archive >>on-demand, at your convenience, starting a few hours after the live >>event takes place. >> >>You can register by clicking: >>http://www.latticesemi.com/corporate/webcasts/isplever7.1fpgadesigntool.cfm >> >>Bart Borosky, Lattice > > > > > To Lattice: > > We dumped Lattice over buggy compilers and dinky performance. Now that > you're spamming our group, I'll make the ban permanent. General Comment: I've not found complex Sw yet that does not have some bugs/blindspots. I've also improved (pretty much) all the engineering SW I use, by giving usable errata reports to the supplier(s). 'dinky' I have no idea about, does not sound like an engineering term ? Do all your design decisions have the same carefull reasoning basis ? What Bart could do is include a link to the Tools Revision History, so potential (and past) users can see what has been changed. -jgArticle: 131922
On May 2, 1:40 pm, austin <aus...@xilinx.com> wrote: > More, > > The process statement does execute statements (in this case, > instructions) in order, and is in essence, a convenience to put > conventional software 'instructions' inside the VHDL, but as I noted, it > doesn't create any hardware. > > Austin If by "The process statement" you mean the literal keyword "process", yes, that creates no hardware. I don't see how anyone cares about that. I think some of us thought you meant *the* process rather than the keyword "process". Certainly a process generates hardware and is what most people use to infer edge clocked registers. The other stuff you said doesn't seem to make sense. Sure, you can use a process in a testbench, but they are also used extensively in code to be synthesized, not as a convenient place to put "software".Article: 131923
John Larkin wrote:
> bart <bart.borosky@latticesemi.com> wrote:
>
>> Lattice is holding a webcast today, Wednesday, May 7th, on our
>> latest version of our FPGA software design tools "ispLEVER 7.1
>> FPGA Design Tool Technical Rollout." The presenter will be Troy
>> Scott, from our software marketing group.
>>
>> If you're interested, the event takes place live at 11am Pacific,
>> 18:00 GMT. In addition, you will be able to view this webcast
>> archive on-demand, at your convenience, starting a few hours
>> after the live event takes place.
>>
>> You can register by clicking:
>> http://www.latticesemi.com/corporate/webcasts/isplever7.1fpgadesigntool.cfm
>
> We dumped Lattice over buggy compilers and dinky performance.
> Now that you're spamming our group, I'll make the ban permanent.
You're wrong. Proper announcements are quite topical. The quality
may be questionable, and that is also suitable for discussion. Of
course, making the announcement less than one hour before the event
begins is indicative of poor thinking. Even 24 hours notice would
be cutting it close.
--
[mail]: Chuck F (cbfalconer at maineline dot net)
[page]: <http://cbfalconer.home.att.net>
Try the download section.
** Posted from http://www.teranews.com **
Article: 131924Hi Peter, Ken, Peter Alfke wrote: > The quadrature encoder has been tested and proven to work ( thank you, > Ken Chapman), detecting every transition as a count pulse, It also seems to bundle all illegal transistions into 'rotary_left' bucket ? ie Missing is : Illegal_event <= (rotary_q1 xor delay_rotary_q1) and (rotary_q2 xor delay_rotary_q2); > never an > accumulated error. The only flaw is a one-pulse backlash. That could be a quite serious drawback in a closed loop system ? eg a DC servo system with a relatively coarse quadrature encoder, should be able to seek any edge, and 'dither-lock' there. > That means, > it does not recognize the first change after a reversal of direction. > You could call it hysteresis, analogous to a +/- 1 count ambiguity, > known to exist in many conversions. Do you have device report files ? This seems to use quite few flip-flops. Tolerable in a FPGA, less desirable in a CPLD. What is the latency, and the max count speed, in clk terms ? -jg
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