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On Apr 20, 10:58=A0am, chrisde...@gmail.com wrote: > =A0 However, the design I am currently working on requires only one of > the blocks to run at 1/4 that of the original clock speed. I am using > a DCM to clock divide the master clock, and the output goes into this > block. The problem happens when > > - the reset signal which resets the DCM, is the same reset which goes > into this same block. > - This will result in a problem, as the clock-divide-by-4 as I call > it, will not emit a clock pulse in reset state, as the DCM has not > locked yet. the synchronous reset will thus not work for this block. > Mike mentioned this in his first post but you seemed to have missed the point with the diversion down clock enable lane. The reset to the block that you're trying to control should not be the same signal as the reset to the DCM. Instead... 1. Take the reset input to the DCM or it together with the DCM not locked output to create a new signal that is used to asynchronously preset a shift register. 2. Clock the shift register with the DCM output clock (i.e. the clock / 4). 3. Use the output of the shift register as the reset to the block that you're trying to control. The shift register output will now be properly synchronized to the 'clock / 4' clock domain and will be nominally active for as many clock cycles as you make the shift register. Add one extra flop to the shift register to account for not knowing precisely when the reset input to the shift register will go away (i.e. to get a minimum 1 clock cycle wide reset, make the shift register 2 flops long). Kevin JenningsArticle: 131401
On Sun, 20 Apr 2008 06:05:49 -0700 (PDT), Michael <nleahcim@gmail.com> wrote: >On Apr 19, 10:41 pm, Frank Buss <f...@frank-buss.de> wrote: >> Michael wrote: >> > Hi there - I am slowly teaching myself VHDL this weekend. I am getting >> > an error that I do not understand: "parse error, unexpected IF". My >> > very simple code is at the bottom of this post, and the error is being >> > caused by the "if switches(0)=0 then" line. Can somebody tell me what >> > I'm doing wrong? I'm sure it's terribly simple - but coming from a C >> > background I am having trouble understanding what I'm doing wrong. >> >> You can't use IF outside of processes, a bit like that you can't use the C >> IF outside of functions. You could write it like this: >> >> led <= cnt(30 downto 23) when switches(0)=0 else enccnt; >> >> A bit like the ?-operator in C. > >Hi Frank - thanks for clearing that up. I had not realized that >limitation of IF. Why can ifs only be used inside processes? That >strikes me as an odd limitation, though I'm sure there's a good reason >behind it. It may be to remind you that - within a process - you can treat VHDL as a programming language with all the limitations of sequential programming like C (at least for simulation, though for synthesis you have to obey further restrictions; e.g. no files!), but outside a process you are in a completely different paradigm, closer to dataflow or functional programming (FP) languages, where you can directly express parallelism (such as interactions between sequential processes). It's quite funny because with the arrival of multicore CPUs, the C programming community (along with the rest of the sequential mindset) are talking like there is some kind of crisis! They will either have to look back a quarter century or so for solutions like Occam, CSP or even Ada's tasking, or adopt something more like VHDL to exploit today's commodity CPUs to more than 1/4 of their capacity. - BrianArticle: 131402
But why is it necessary? Doesn't the normal FPGA configuration process reset the DDR2 interface? I can't find any info on how to use this input.Article: 131403
Hi All i am new to FPGA's and have picked up a celoxica rc1000pp (virtex 2000e) cheap, the downside...no manuals or software. i expected that (being an old bit of kit) the drivers and manuals would be easy to get hold of....oh how i was wrong does anyone on this mailing list have any details on the board... i know there is an old windows driver, source-code for an old linux driver available. i'm not really interested in handel-c but i've been told it was possible to use vhdl and load it on there (source provided apparently)...if someone has that source :-) also any and all documentation would be great (pdf's etc preferred) i jumped in at the deep end but the more docs and code i can get the better (i will probably update the linux pci driver for latest kernel and go from there...though i'll need the old source first ;-) if you can help then thanks very much in advance TimArticle: 131404
On Apr 19, 6:09=A0pm, Moikel <obviouslyadu...@gmail.com> wrote: > Hello, > > I am writing my report on a university project. The project work > involved an FPGA implementation of a neural network. > > I have created two versions of the design; a serial and a parallel > version. Both synthesise and work in hardware. > > I am comparing the two in terms of performance. I would also like to > compare them in terms of how much FPGA resources they consume. Could > somebody please give me some advice on what elements of synthesis > would be good for comparison? > > I'm currently comparing Max Clock. Frequency, Number of Slices, Number > of Bonded IOBs. > > Thanks Be careful when measuring 'Number of Slices' or 'number of flip flops' or any other internal resource count, they can be misleading when used as a metric for design comparisons. The problem with these is that synthesis will often replicate logic or not optomize things as small as they 'could' be (generally they do this in order to get better clock speed performance), because they don't need to in order to meet the design requirements. From the perspective of synthesis software, meeting design requirements means simply: - It fits in the selected device - It runs at the selected clock speed(s). One way to get a reasonable estimate of internal resource usage is to target the design to something intentionally too small so that, no matter how hard synthesis works, the design won't fit. Then the software will tell you how many slices/flops/etc. that it is trying to fit, this number is frequently different than the numbers you will gets when it targets a larger device that the design actually will fit into. In one recent test case, the difference was 16% of the design. Kevin JenningsArticle: 131405
Hi all, I'm having a little problem to implement a DCM. It's the first time i need it (to be able to use DDR SDRAM). Before i'm going to think about a design for a memory controller, i first want to verify that i'm able to control a DCM. I've read a lot of datasheets, and think i know the theory. In ISE 9.2i i added an IP for a DCM which is easy to configure. To test if my configuration is right, i want to measure these clocks by using the DIFF CLK OUT pins (SMA connectors). The only problem is that i have no idee which pins belong to the DCM...and don't know how to connect the DCM's clock outputs to the DIFF CLK output-pins in order to measure them. So if anybody could tell me which bank and pin-number belongs to the DCM(s) i would be very happy :) Greetz, Mr.MArticle: 131406
Hi,
On some pretty obvious piece of VHDL (below)
QuartusII does not inferred any RAM !!!!!!
(whatever "width" value is...)
Any help how to convince QII to use
RAM and not LEs ???
(all ram options are set to ON...
and I've seen it working well on other occasions
so what Is wrong here ?)
many tks.
lc.
(I used QII7.0web ed.)
--snip--
type k_ram_type is array (0 to (2**width)-1)
of std_logic_vector(17 downto 0);
shared variable k_ram: k_ram_type;
begin
process(a_clk)
begin
if rising_edge(a_clk) then
if en_A='1' then
if wr_en_A='1' then
data_A_out <= k_ram(conv_integer(a_adr));
k_ram(conv_integer(a_adr)) := data_A_in;
else
data_A_out <= k_ram(conv_integer(a_adr));
end if;
end if;
end if;
end process;
--snip--
Article: 131407On Mon, 21 Apr 2008 04:56:57 -0700, ben@hometoolong.inv wrote: >But why is it necessary? Doesn't the normal FPGA configuration process >reset the DDR2 interface? I can't find any info on how to use this >input. The DDR memory itself will likely require an initialisation sequence - this is certainly the case for SDRAM - I would imagine this signal tells the controller to perfom this initialisation.Article: 131408
On 20 Apr., 00:13, Mike Treseler <mike_trese...@comcast.net> wrote: > Moikel wrote: > > I'm currently comparing Max Clock. Frequency, Number of Slices, Number > > of Bonded IOBs. > > I like Fmax, LUTs, and Flops. Yes, slices is meaningless. The number of slices can vary by a factor of two for the same synthesis result. Instead report DFFs and LUTs, and also note the number of inputs to a lut your target technology uses. Kolja SulimmaArticle: 131409
On Apr 21, 3:24 am, "Michael A. Terrell" <mike.terr...@earthlink.net> wrote: > John Larkin wrote: > > > On Sun, 20 Apr 2008 18:10:04 -0400, "Michael A. Terrell" > > <mike.terr...@earthlink.net> wrote: > > > >John Larkin wrote: > > > >> On Sun, 20 Apr 2008 17:33:16 -0400, "Michael A. Terrell" > > >> <mike.terr...@earthlink.net> wrote: > > > >> >John Larkin wrote: > > > >> >> A quad opamp doesn't have 1738 pins! > > > >> > That will only happen if Bloggs designs it. :( > > > >> Bloggs has several times stated that he doesn't design electronics. He > > >> hasn't stated what he actually does. > > > > He stated that he does absolutely nothing. It might be the only time > > >he has ever told the truth. > > > Sounds boring. No wonder he's usually bummed. > > No reason to live if you have nothing to do. :( > > --http://improve-usenet.org/index.html > > Use any search engine other than Google till they stop polluting USENET > with porn and junk commercial SPAM > > If you have broadband, your ISP may have a NNTP news server included in > your account:http://www.usenettools.net/ISP.htm I used to use a newsreader with the servers at RCN. But I can't get the reader to find the servers anymore. Actually, it seems to be an account validation thing and dealing with RCN support is such a pain that I am willing to put up with the SPAM until it becomes unbearable. When that happens I will do without newsgroups. A lot of the important stuff is handled in highly targeted forums anyway. I mainly come here to see what others are doing and having problems with and to ask an occasional question. I seem to recall that a question I asked a month or so ago resulted in a lot of crap being thrown around. That is almost as bad as the SPAM and no ISP can filter it!Article: 131410
Michael wrote: <snip> > > A-ha! I realized I could get rid of the edge checking and just compare > with my saved previous state. It synthesizes! Unfortunately, it gives > me some warnings during synthesization, and then (I believe due to the > warnings) it won't give me a programming file. The warnings are: > > the following signal(s) form a combinatorial loop: led<7>, enc_cnt<7>, > Maddsub_enc_cnt14. > > (for led<7> - led<0>) > > Then it gives me a bunch of errors during mapping, like this one: > > ERROR:MapLib:661 - LUT4 symbol "Maddsub_enc_cnt41" (output > signal=Maddsub_enc_cnt4) has input signal "Maddsub_enc_cnt" which > will be > trimmed. See the t > > > I'm so close now (I think!) Can anybody tell me what is wrong with my > code? I've never had a problem with mapping before - so this is very > odd for me. I've posted the full code below. Thanks so much! > > -Michael > > > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.numeric_std.all; > > entity hello_world is > port ( > clk, enc_a, enc_b : in std_logic; > switches : in std_logic_vector (3 downto 0); > led : out std_logic_vector (7 downto 0) > ); > end hello_world; > > architecture rtl of hello_world is > signal cnt : unsigned (30 downto 0); > signal encval : unsigned (7 downto 0); > signal enc_cnt : unsigned (7 downto 0); > signal prevstate : std_logic_vector (1 downto 0); > begin > process(clk) > begin > if rising_edge(clk) then > cnt <= cnt + 1; > encval <= "000000" & enc_b & enc_a; > end if; > end process; > > process(enc_a, enc_b) > begin > if prevstate(0) /= enc_a then > case prevstate is > when "00"=> > enc_cnt <= enc_cnt + 1; > when "01"=> > enc_cnt <= enc_cnt - 1; > when "10"=> > enc_cnt <= enc_cnt - 1; > when "11"=> > enc_cnt <= enc_cnt + 1; > when others => > enc_cnt <= enc_cnt; > end case; > else > case prevstate is > when "00"=> > enc_cnt <= enc_cnt - 1; > when "01"=> > enc_cnt <= enc_cnt + 1; > when "10"=> > enc_cnt <= enc_cnt + 1; > when "11"=> > enc_cnt <= enc_cnt - 1; > when others => > enc_cnt <= enc_cnt; > end case; > end if; > > prevstate(0) <= enc_a; > prevstate(1) <= enc_b; > end process; > > led <= std_logic_vector(cnt(30 downto 23)) when switches(0)='0' else > std_logic_vector(enc_cnt); > > end rtl; You almost have what you want but you will still have troubles because mechanical chatter can matter in a binary implementation. One way you CAN achieve your goals is to use Gray code counters, at least for the LSbits. I previously designed a 3-bit Gray code counter for a first stage of a very fast counter such that I only have 1 LUT of delay for each bit and was able to count at a clock frequency limited by the delay of a single LUT. My design produced the same combinatorial loops warning but for a stable combinatorial quadrature counter, those are expected warnings and should still produce a programming file. Even here, I used this first stage as a divide-by-8 prescaler rather than using the count directly because getting a 3-bit Gray counter to sync up with a multi-bit Gray or binary counter isn't trivial though it is doable with a little care. The key to getting a quadrature counter to work with a Gray code counter is to realize that when you are at a specific Gray count, only two bits can change: one for the forward direction, one for reverse. Effectively one channel of the quadrature counter can be slaved to the LSbit while the count determines which upper bit (and at what polarity) the other quadrature channel controls. When you transition between two upper bits being controlled by the one quadrature channel, the bits are both safe because the quadrature channel that controls those upper bits is in the middle, stable part of its cycle while the LSbit channel is transitioning the count, affecting which upper bit is controlled. When the Gray count is read, the value is (typically) registered in the clock domain twice such that if one bit is caught mid-transition then that value will be settled upon by the second register - only one register - as a defined value. If instead there are multiple registers fed by that one first-stage value, it's possible two paths could "see" different values for this asynchronously changing signal. If you can figure how to count in Gray and then how to change one bit (at a defined polarity) at a time for a given count, you will have an every-transition counter for full resolution and be asynchronous-friendly in your design. And you will get plenty of combinatorial-loop warnings for your design but you will be able to produce a programming file; they are just warnings, after all. - John_HArticle: 131411
"Tim Pope" <timpope.programmer@gmail.com> wrote in message news:601826a6-2169-4008-bcf6-cdd1e0afb9ee@s33g2000pri.googlegroups.com... > Hi All > > i am new to FPGA's and have picked up a celoxica rc1000pp (virtex > 2000e) cheap, the downside...no manuals or software. > i expected that (being an old bit of kit) the drivers and manuals > would be easy to get hold of....oh how i was wrong > > does anyone on this mailing list have any details on the board... i > know there is an old windows driver, source-code for an old linux > driver available. Celoxica was recently bought by Catalytic Inc (now renamed to AgilityDS). I would send them an email (support@..) to see if they can send you the drivers and perhaps the source code for it. Hans www.ht-lab.com > > i'm not really interested in handel-c but i've been told it was > possible to use vhdl and load it on there (source provided > apparently)...if someone has that source :-) > > also any and all documentation would be great (pdf's etc preferred) > > i jumped in at the deep end but the more docs and code i can get the > better (i will probably update the linux pci driver for latest kernel > and go from there...though i'll need the old source first ;-) > > if you can help then thanks very much in advance > > TimArticle: 131412
krw wrote: > In article <6PQOj.21063$%41.8783@nlpi064.nbdc.sbc.com>, > notthisjoergsch@removethispacbell.net says... >> John Larkin wrote: >>> On Sun, 20 Apr 2008 14:13:21 -0700, Joerg >>> <notthisjoergsch@removethispacbell.net> wrote: >>> >>>> John Larkin wrote: >>>>> On Sat, 19 Apr 2008 14:17:44 -0700, Joerg >>>>> <notthisjoergsch@removethispacbell.net> wrote: >>>>> >>>>>> Nico Coesel wrote: >>>>>>> Dave <dhschetz@gmail.com> wrote: >>>>>>> >>>>>>>> Does anybody out there have a good methodology for determining your >>>>>>>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >>>>>>>> The brute force method is fairly maddening. I'd be curious to hear if >>>>>>>> anybody has any 'tricks of the trade' here. >>>>>>> I start thinking about how the PCB should be routed the minute I start >>>>>>> to draw a schematic. I always draw components with their actual >>>>>>> pin-outs. This helps to group pins together and it helps to >>>>>>> troubleshoot the circuit when the prototype is on your bench (no need >>>>>>> to lookup the pinouts because they are in your diagram). >>>>>>> >>>>>> For quad opamps like the LM324 as well? That can make a schematic harder >>>>>> to read and will also cause a nightmare if the layouter wants to swap >>>>>> amp A with amp C and stuff like that. >>>>>> >>>>>> [...] >>>>> A quad opamp doesn't have 1738 pins! >>>>> >>>> Well, yes, I was just wondering about whether Nico really always draws >>>> the physical package. Looks like he doesn't for smaller stuff. >>>> >>>> With 1738 pins you can only hope that the FPGA has enough routing >>>> resources. That used to be a major pain in the early 90's. Don't know >>>> about nowadays since other guys design the parts with the big FPGAs. And >>>> I am glad I don't have to deal with BGA, at least not with large ones ... >>> The biggest ones we use are Sparten 3's with 456 balls on 1 mm >>> centers. We haven't had any routing problems so far, doing pretty >>> complex stuff at 128 MHz clock rates. Our in-house BGA soldering >>> yield, to date, is exactly 100%. BGAs seem to be a lot easier to >>> solder reliably than fine-pitch leaded parts. Easier to inspect, too, >>> since you can't inspect them at all. >>> >> The latter is a concern in my field (medical). We need to be able to >> inspect. The other concern is involuntary board flexing. Most of my >> designs have to sustain under tortures such as freighter pilots >> ploughing through a storm in the Carribean in airplanes as old as a DC-3 >> or a trucker in Africa who is lead-footing it over a few hundred miles >> of washboard road. >> > X-Rays? > They tend not to penetrate through metal so well and are frowned upon at the work place. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131413
Are you sure that Quartus supports shared variables for RAM insertion ?Article: 131414
On Apr 21, 3:24 am, "Michael A. Terrell" <mike.terr...@earthlink.net> wrote: > John Larkin wrote: > > No reason to live if you have nothing to do. :( > > --http://improve-usenet.org/index.html > > Use any search engine other than Google till they stop polluting USENET > with porn and junk commercial SPAM > > If you have broadband, your ISP may have a NNTP news server included in > your account:http://www.usenettools.net/ISP.htm What is the point of including a link to the "improve usenet" page? I don't see any useful information there. The page complains about a few things and offers no advice on what to do about any of it... counter to its stated purpose of being "an attempt to make Usenet participation a better experience for those who are clued as to what the Usenet medium is and how to use it". Instead of offering anything constructive, they even insult people that they should be trying to reach and convince... "most of the people who post to Usenet via the clunky Google Groups web interface are lusers or lamers". Do you think that this page has had any sort of positive influence on usenet? Does your posting the link help in any way?Article: 131415
Not sure, but if I use a regular variable instead the problem remains the same. No RAM inserted, only LE's lc ALuPin@web.de wrote: > Are you sure that Quartus supports shared variables for RAM insertion ?Article: 131416
rickman wrote: >> your account:http://www.usenettools.net/ISP.htm > > I used to use a newsreader with the servers at RCN. But I can't get > the reader to find the servers anymore. Actually, it seems to be an > account validation thing and dealing with RCN support is such a pain > that I am willing to put up with the SPAM until it becomes > unbearable. When that happens I will do without newsgroups. A lot of > the important stuff is handled in highly targeted forums anyway. I > mainly come here to see what others are doing and having problems with > and to ask an occasional question. I seem to recall that a question I > asked a month or so ago resulted in a lot of crap being thrown > around. That is almost as bad as the SPAM and no ISP can filter it! If you have an account with RCN, the news servers name is news.rcn.com It is connected to port 119 (as are all news servers). The authentication information is: your email account name (eg. blahdeblah@rcn.com), and your password is the same as the password for your email program. It really is quite simple. RCN does have a few news outages from time to time, but generally they are very reliable. -ChuckArticle: 131417
Hello. I have a problem with use opb_intc in my projekt In mhs: # External Interrupts PORT IrqSecond_pin = IrqSecond, DIR = I, SIGIS = Interrupt, SENSITIVITY = LEVEL_HIGH PORT IrqPci_pin = IrqPci, DIR = I, SIGIS = Interrupt, SENSITIVITY = LEVEL_HIGH PORT IrqFrame_pin = IrqFrame, DIR = I, SIGIS = Interrupt, SENSITIVITY = LEVEL_HIGH BEGIN ppc405 PARAMETER INSTANCE = ppc405_0 PARAMETER HW_VER = 2.00.c BUS_INTERFACE JTAGPPC = jtagppc_0_0 BUS_INTERFACE IPLB = plb BUS_INTERFACE DPLB = plb PORT PLBCLK = sys_clk_s PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ PORT RSTC405RESETCHIP = RSTC405RESETCHIP PORT RSTC405RESETCORE = RSTC405RESETCORE PORT RSTC405RESETSYS = RSTC405RESETSYS PORT CPMC405CLOCK = proc_clk_s PORT EICC405EXTINPUTIRQ = opb_intc_interrupt END BEGIN opb_iic PARAMETER INSTANCE = Generic_IIC_Bus PARAMETER HW_VER = 1.02.a PARAMETER C_CLK_FREQ = 100000000 PARAMETER C_BASEADDR = 0x40800000 PARAMETER C_HIGHADDR = 0x4080ffff BUS_INTERFACE SOPB = opb PORT Scl_O = fpga_0_Generic_IIC_Bus_Scl_O PORT Sda_I = fpga_0_Generic_IIC_Bus_Sda_I PORT Sda_O = fpga_0_Generic_IIC_Bus_Sda_O PORT IP2INTC_Irpt = irq_iic END BEGIN opb_intc PARAMETER INSTANCE = opb_intc_0 PARAMETER HW_VER = 1.00.c PARAMETER C_BASEADDR = 0x43e14000 PARAMETER C_HIGHADDR = 0x43e140ff BUS_INTERFACE SOPB = opb PORT Irq = opb_intc_interrupt PORT Intr = irq_iic & IrqFrame & IrqPci & IrqSecond END In mss: PARAMETER VERSION = 2.2.0 PARAMETER int_handler = ext_int_handler, int_port = IrqSecond PARAMETER int_handler = ext_int_handler, int_port = IrqPci PARAMETER int_handler = ext_int_handler, int_port = IrqFrame In programm: /* Initialize exception handling */ XExc_Init(); /* Register external interrupt handler */ XExc_RegisterHandler(XEXC_ID_NON_CRITICAL_INT, (XExceptionHandler)XIntc_DeviceInterruptHandler, (void *)0); /* Connect interrupt handler that will be called when an interrupt occurs */ XIntc_RegisterHandler(XPAR_OPB_INTC_0_BASEADDR,0, (XInterruptHandler)IrqSecondHandler, (void *)0); XIntc_RegisterHandler(XPAR_OPB_INTC_0_BASEADDR,1, (XInterruptHandler)IrqPciHandler, (void *)0); XIntc_RegisterHandler(XPAR_OPB_INTC_0_BASEADDR,2, (XInterruptHandler)IrqFrameHandler, (void *)0); XIntc_RegisterHandler(XPAR_OPB_INTC_0_BASEADDR,3, (XInterruptHandler)IrqIicHandler, (void *)0); /* Start the interrupt controller */ XIntc_mMasterEnable(XPAR_OPB_INTC_0_BASEADDR); /* Enable interrupts in the interrupt controller */ XIntc_mEnableIntr(XPAR_OPB_INTC_0_BASEADDR, 0x1|0x2|0x4|0x8); /* Enable PPC non-critical interrupts */ XExc_mEnableExceptions(XEXC_NON_CRITICAL); Where error?Article: 131418
On Apr 21, 8:53=A0am, Kolja Sulimma <ksuli...@googlemail.com> wrote: > > Instead report DFFs and LUTs, and also note the number of inputs to a > lut your target technology uses. > DFFs and LUTs are not necessarily good metrics either since they can be affected quite a bit by efforts to meet timing (i.e. register replication) and/or lack of efforts to optomize logic (if it doesn't entire fill up the device, synthesis might not try to do any better unless forced to in order to improve timing). KJArticle: 131419
On Apr 21, 8:41=A0am, LC <cupidoREM...@mail.ua.pt> wrote: > Hi, > > On some pretty obvious piece of VHDL (below) > QuartusII does not inferred any RAM !!!!!! > (whatever "width" value is...) > You didn't quite follow the template for inferring memory. > Any help how to convince QII to use > RAM and not LEs ??? > (all ram options are set to ON... > and I've seen it working well on other occasions > so what Is wrong here ?) > > many tks. > > lc. > > (I used QII7.0web ed.) > --snip-- > > type k_ram_type is array (0 to (2**width)-1) > =A0 =A0 =A0 =A0 of std_logic_vector(17 downto 0); > shared variable k_ram: k_ram_type; > > begin > > process(a_clk) > begin > =A0 =A0if rising_edge(a_clk) then > =A0 =A0 =A0 =A0 if en_A=3D'1' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if wr_en_A=3D'1' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 data_A_out <=3D k_ram(conv_integer(a_a= dr)); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 k_ram(conv_integer(a_adr)) :=3D data_A= _in; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 data_A_out <=3D k_ram(conv_integer(a_a= dr)); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 end if; > =A0 =A0 end if; > end process; > > --snip-- Remove the "if en_A=3D'1' then " and the corresponding "end if". You can't have a clock enable on the 'read' side. Refer back to the Quartus documentation for the supported templates that infer memory. Kevin JenningsArticle: 131420
On Apr 21, 5:11=A0am, Evan Lavelle <nos...@nospam.com> wrote:
> You don't need to know
> or write *any* HDL code to use Maia; if you can write vectors for your
> module, then you can verify it.
>
Not to be too much of a slug, but I'm kinda missing the point I think
of this tool....
Why would I want to write test vectors (Hint: I don't). Using a
language with control structures is far more concise and easier to
maintain.
If I did have to write test vectors I would probably use something to
generate those test vectors as an output file artifact from a
simulation run.
> // trivial complete testbench example: 4-bit counter with reset
> DUT {
> =A0 module counter(input CLK, RST; output [3:0] Q)
> =A0 create_clock CLK =A0 =A0 =A0 =A0 // define the clock
> =A0 [CLK, RST] -> [Q] =A0 =A0 =A0 =A0// define the test vector format}
>
> main() {
> =A0 [.C, 1] -> [0]; =A0 =A0 =A0 =A0 =A0// reset
> =A0 for(i=3D1; i <=3D 16; i++)
> =A0 =A0 [.C, 0] -> [i]; =A0 =A0 =A0 =A0// count, with rollover
>
Having flashbacks to generating test vectors in ABEL...something from
20 years ago.
KJ
Article: 131421You have my solution available at : http://www.alse-fr.com/English/ips.html There is a test bench and simulation script. As mentioned : don't forget to register A & B before hooking to the module. BertrandArticle: 131422
Well, this is a challenge. I am working on a design that uses 4 LUTs and 4 flip-flops, takes in raw A and B inputs plus a clock and outputs synchronously decoded CE and U/D signals to control a binary counter. There are 3 configuration options: 1, 2, or 4 counts per 360 degree contact cycle. And bounce is suppressed, and kept away from the counter :-) "Everything you always wanted to have in a quadrature detector'" PeterArticle: 131423
> On Apr 21, 5:11 am, Evan Lavelle <nos...@nospam.com> wrote:
>> You don't need to know
>> or write *any* HDL code to use Maia; if you can write vectors for your
>> module, then you can verify it.
KJ wrote:
> Not to be too much of a slug, but I'm kinda missing the point I think
> of this tool....
Maybe the intended audience is those
unmotivated to learn vhdl or verilog.
Sort of a testbench 'wizard' to go with
wizard generated code.
Not my cup of tea, but it might get someone started.
-- Mike Treseler
Article: 131424
"KJ" <kkjennings@sbcglobal.net> wrote in message
news:1b5f41df-e273-47c0-b309-460a94735b9e@x19g2000prg.googlegroups.com...
On Apr 21, 5:11 am, Evan Lavelle <nos...@nospam.com> wrote:
> You don't need to know
> or write *any* HDL code to use Maia; if you can write vectors for your
> module, then you can verify it.
>
>
>Not to be too much of a slug, but I'm kinda missing the point I think
>of this tool....
>
>Why would I want to write test vectors (Hint: I don't). Using a
>language with control structures is far more concise and easier to
>maintain.
>
>If I did have to write test vectors I would probably use something to
>generate those test vectors as an output file artifact from a
>simulation run.
If you look at tools like Mentor's inFact they do exactly that although they
don't create a vector file but an intelligent testbench instead. The inputs
are high-level rules and actions. These high-level rules are compiled into
testbench graphs which are then use to generate optimised vector sets.
For example to test a UART you write different rules for all the different
options like word size, parity type, number of stop bits, interrupt
sequence, read/write sequence etc. The compile will then use this info to
generate an optimised vector set that test all valid combinations (not 100%
sure on this one). I believe this is one step up from writing assertions and
feeding your design with constrained random data.
This is a trivial example but you can understand that with more rules this
becomes more and more powerful. From what I understand these tools are very
complex since they not only need to find the smartest set of testvectors but
also handle all the different constraints and constraint solvers is one area
which is still heavily being researched.
I would say kudos to Evan for attempting to develop a product like this and
making it freely available to the rest of us,
Hans
www.ht-lab.com
> // trivial complete testbench example: 4-bit counter with reset
> DUT {
> module counter(input CLK, RST; output [3:0] Q)
> create_clock CLK // define the clock
> [CLK, RST] -> [Q] // define the test vector format}
>
> main() {
> [.C, 1] -> [0]; // reset
> for(i=1; i <= 16; i++)
> [.C, 0] -> [i]; // count, with rollover
>
Having flashbacks to generating test vectors in ABEL...something from
20 years ago.
KJ
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