Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
quartus II sopc builder, jtag debugging mode, tri-state avalon bridge,
sdram, on-chip ram, etc
On Jan 29, 5:04 am, G=F3rski Adam
<gorskia@.................wp....................pl..................>
wrote:
> BigJames...@gmail.com pisze:
>
> > here is my codes. I want to verify the result and display at the end,
> > however I got like "cdcd", what's wrong? thanks
>
> > /*
> > * "Hello World" example.
> > *
> > * This example prints 'Hello from Nios II' to the STDOUT stream. It
> > runs on
> > * the Nios II 'standard', 'full_featured', 'fast', and 'low_cost'
> > example
> > * designs. It runs with or without the MicroC/OS-II RTOS and requires
> > a STDOUT
> > * device in your system's hardware.
> > * The memory footprint of this hosted application is ~69 kbytes by
> > default
> > * using the standard reference design.
> > *
> > * For a reduced footprint version of this template, and an
> > explanation of how
> > * to reduce the memory footprint for a given application, see the
> > * "small_hello_world" template.
> > *
> > */
>
> > #include <stdio.h>
> > #include <stdlib.h>
> > #include <sys/alt_dma.h>
> > #include "system.h"
>
> > static volatile int rx_done =3D 0;
>
> > /*
> > * Callback function that obtains notification that the data has
> > * been received.
> > */
> > static void done (void* handle, void* data)
> > {
> > rx_done++;
> > }
>
> > int main(int argc, char* argv[], char* envp[])
> > {
> > int rc;
> > static char buff[256]=3D"abcdefghijklmn\0";
> > alt_dma_txchan txchan;
> > alt_dma_rxchan rxchan;
>
> > void* tx_data =3D (void*) buff; /* pointer to data to
> > send */
> > void* rx_buffer =3D (void*) 0x01000000; /* on_chip_memory addr*/
>
> > /* Create the transmit channel */
> > if ((txchan =3D alt_dma_txchan_open("/dev/dma_0")) =3D=3D NULL)
> > {
> > printf ("Failed to open transmit channel\n");
> > exit (1);
> > }
>
> > /* Create the receive channel */
> > if ((rxchan =3Dalt_dma_rxchan_open("/dev/dma_0")) =3D=3D NULL)
> > {
> > printf ("Failed to open receive channel\n");
> > exit (1);
> > }
>
> > /* Post the transmit request */
> > if ((rc =3D alt_dma_txchan_send (txchan,tx_data,128,NULL,NULL)) < 0)
> > {
> > printf ("Failed to post transmit request, reason =3D %i\n", rc);
> > exit (1);
> > }
>
> > /* Post the receive request */
> > if ((rc =3D alt_dma_rxchan_prepare (rxchan,rx_buffer,128,done,NULL)) <=
> > 0)
> > {
> > printf ("Failed to post read request, reason =3D %i\n", rc);
> > exit (1);
> > }
>
> > /* wait for transfer to complete */
> > while (!rx_done);
> > printf ("Transfer successful!\n");
> > printf ("%s",(ONCHIP_MEMORY_0_BASE));
> > return 0;
> > }
>
> What is set in system configuration ?
>
> Adam
Article: 128526I have a Spartan3 Bank VCCO pins connected to 1.8V. Normally I use this bank to generate 1.8V push-pull signals but I needto drive out 3.3V signal on this bank. Can I drive out open drain output with external pull-up resistor to 3.3V on a 1.8V I/O bank? Thanks. CPArticle: 128527
Hi all, I would like to know how we can demodulate a BPSK signal with CORDIC algorithm. How can we (with CORDIC) make the phase acquisition and tracking due to an IQ conversion without a Costas Loop... Thanks...Article: 128528
<cpandya@yahoo.com> wrote in message news:02be1a91-ec9b-49a6-824b-b80b8daf1301@s13g2000prd.googlegroups.com... >I have a Spartan3 Bank VCCO pins connected to 1.8V. Normally I use > this bank to generate 1.8V push-pull signals but I needto drive out > 3.3V signal on this bank. Can I drive out open drain output with > external pull-up resistor to 3.3V on a 1.8V I/O bank? > > Thanks. > > CP There are diodes on each I/O that will prevent that I/O from going above VCCO or below GND by more than a "diode drop". If the resistor is large enough you won't do any damage, but you won't get the high level voltage you're expecting. BobArticle: 128529
Thank you, thank you! I removed swift.dll from the simulation startup, and that fixed my problem! (Unfortunately, the ActiveHDL evaluation edition limits sim sessions to 10us, so I can't see the whole sim.) "IT" <igortsapenko@gmail.com> wrote in message news:9adcd213-3227-40e5-98d0-44a570136c05@k39g2000hsf.googlegroups.com... > You have to load only one PLI library when you start simulation. In > your case you only need swift_lmtv.dll. The latter has internal > reference to the either libswift.dll or lmtv.dll that you have built > in Xilinx. Xilinx LMC_HOME variable has to point to the smartmodels > installation directory (Xilinx\smartmodel\nt\installed_nt) for > libswift/lmtv to be found. > > There is a nice tool to check dependencies inside your dll file. You > can get it from www.dependencywalker.com. Check if you have any links > broken in your swift_lmtv.dll.Article: 128530
"John McCaskill" <jhmccaskill@gmail.com> wrote in message news:28237eec-d43a-41b8-912e-1cbe741b55cf@t1g2000pra.googlegroups.com... > On Jan 28, 11:16 pm, "talkb" <no...@talkb.com> wrote: >> Ok, I double-checked our license-server's license.dat file. >> The commented section indicated our company is licensed for "Modelsim-PE >> Plus" >> >> As far as I can tell, the actual license-increments are just 2 items: >> 1) msimpevlog (Verilog) >> 2) msimpe (VHDL) >> >> Nothing else 'special' in the license-file. Perhaps Modelsim allows a >> Verilog+VHDL combo license to subsitute for a Smartmodel license? > > As luck would have it I just got a call from someone at Mentor > Graphics so I asked them about this. What they told me is that if you > are using only Verilog in your design, you do not need the extra > license for Smartmodels. If you are using any VHDL, you do need the > license. When I asked why, they said that they would have to ask > someone else and get back to me. And the plot thickens! :) I did not run any mixed VHDL+Verilog simulations using the Xilinx Smartmodels, (only pure Verilog). So I gues lucky for me, I didn't run into this problem. Do share when/if that contact returns with news!Article: 128531
On 28 Jan., 21:34, Ben Jackson <b...@ben.com> wrote: > >http://www.truedream.org/smile/MyFirstFlashFpgaCert.pdf > > ...you got FIRED for missing 3 days of work due to a mixup in vacation > scheduling? Wow. I wonder, too. Must have a strange boss. I thought you were still working in Germany (where it is not easy to get that fast out of the job). Antti: some :) :) :) for you and your book. bye ThomasArticle: 128532
hi all I want to work with xillinx edk and add an ethernet core to my design. I used hard-temac core and to connect this core to plb bus I must use plb-temac. but this core consume alot of slice. I want to create a new interface for hard-temac core. as I see the mpd file of this core it create a new bus interface to connect some of its port to it and this port will be connected to plb-temac port that connected to this new bus interface. I want to define a new bus interface in my interface but I don't know how I can do this. can anyone guid me what I must do? Thaks a lot in advance. Kind regardsArticle: 128533
in MHS : #********************************************************* BEGIN microblaze PARAMETER HW_VER = 7.00.b PARAMETER INSTANCE = microblaze_0 PARAMETER C_INTERCONNECT = 1 PARAMETER C_DEBUG_ENABLED = 1 BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE DPLB = mb_plb BUS_INTERFACE IPLB = mb_plb BUS_INTERFACE DOPB = mb_opb BUS_INTERFACE IOPB = mb_opb BUS_INTERFACE DEBUG = microblaze_0_dbg PORT MB_RESET = mb_reset END BEGIN plb_v46 PARAMETER INSTANCE = mb_plb PARAMETER HW_VER = 1.00.a PORT PLB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END BEGIN opb_v20 PARAMETER INSTANCE = mb_opb PARAMETER HW_VER = 1.10.c # PARAMETER C_EXT_RESET_HIGH = 0 PORT SYS_Rst = sys_rst_s PORT OPB_Clk = sys_clk_s END #********************************************************* But EDK swear: ERROR:MDT - IPNAME:microblaze INSTANCE:microblaze_0 - E:\Work\Xilinx\test\system.mhs line 58 - one of the following bus interfaces are assigned: DPLB:IPLB This is not allowed when DOPB is assigned! ERROR:MDT - IPNAME:microblaze INSTANCE:microblaze_0 - E:\Work\Xilinx\test\system.mhs line 58 - one of the following bus interfaces are assigned: DPLB:IPLB This is not allowed when IOPB is assigned! ERROR:MDT - IPNAME:microblaze INSTANCE:microblaze_0 - E:\Work\Xilinx\test\system.mhs line 58 - one of the following bus interfaces are assigned: DOPB:IOPB This is not allowed when DPLB is assigned! ERROR:MDT - IPNAME:microblaze INSTANCE:microblaze_0 - E:\Work\Xilinx\test\system.mhs line 58 - one of the following bus interfaces are assigned: DOPB:IOPB This is not allowed when IPLB is assigned! ERROR:MDT - Errors occured while creating Hardware System OPB I want use to connect mch_opb_sdramArticle: 128534
On Wed, 30 Jan 2008 00:16:52 -0800 (PST), axalay <axalay@gmail.com> wrote: <...> No you can connect only one of the buses. The solution is to connect plb to microblaze, and opb_plb bridge(s) to create an additional opb bus regards, ZaraArticle: 128535
If C_INTERCONNECT=1 connect PLB, if C_INTERCONNECT=0 connect OPB. I think that both buses are not connected to microblaseArticle: 128536
No, You can only have one of them. The parameter C_INTERCONNECT decide if PLB or OPB will be used. Göran "axalay" <axalay@gmail.com> wrote in message news:ab34725a-7385-4057-841b-cec3c5d014e6@v67g2000hse.googlegroups.com... > in MHS : > #********************************************************* > BEGIN microblaze > PARAMETER HW_VER = 7.00.b > PARAMETER INSTANCE = microblaze_0 > PARAMETER C_INTERCONNECT = 1 > PARAMETER C_DEBUG_ENABLED = 1 > BUS_INTERFACE DLMB = dlmb > BUS_INTERFACE ILMB = ilmb > BUS_INTERFACE DPLB = mb_plb > BUS_INTERFACE IPLB = mb_plb > BUS_INTERFACE DOPB = mb_opb > BUS_INTERFACE IOPB = mb_opb > BUS_INTERFACE DEBUG = microblaze_0_dbg > PORT MB_RESET = mb_reset > END > > BEGIN plb_v46 > PARAMETER INSTANCE = mb_plb > PARAMETER HW_VER = 1.00.a > PORT PLB_Clk = sys_clk_s > PORT SYS_Rst = sys_bus_reset > END > > BEGIN opb_v20 > PARAMETER INSTANCE = mb_opb > PARAMETER HW_VER = 1.10.c > # PARAMETER C_EXT_RESET_HIGH = 0 > PORT SYS_Rst = sys_rst_s > PORT OPB_Clk = sys_clk_s > END > #********************************************************* > > But EDK swear: > > ERROR:MDT - IPNAME:microblaze INSTANCE:microblaze_0 - > E:\Work\Xilinx\test\system.mhs line 58 - one of the following bus > interfaces > are assigned: > DPLB:IPLB > This is not allowed when DOPB is assigned! > ERROR:MDT - IPNAME:microblaze INSTANCE:microblaze_0 - > E:\Work\Xilinx\test\system.mhs line 58 - one of the following bus > interfaces > are assigned: > DPLB:IPLB > This is not allowed when IOPB is assigned! > ERROR:MDT - IPNAME:microblaze INSTANCE:microblaze_0 - > E:\Work\Xilinx\test\system.mhs line 58 - one of the following bus > interfaces > are assigned: > DOPB:IOPB > This is not allowed when DPLB is assigned! > ERROR:MDT - IPNAME:microblaze INSTANCE:microblaze_0 - > E:\Work\Xilinx\test\system.mhs line 58 - one of the following bus > interfaces > are assigned: > DOPB:IOPB > This is not allowed when IPLB is assigned! > ERROR:MDT - Errors occured while creating Hardware System > > OPB I want use to connect mch_opb_sdramArticle: 128537
Hi I have design that will PAR fine when chipscope is not included but when it is I get the following error :- The placement constraints of the IOBs app_rd_n and app_AD[7] makes this design unroutable due to a physical routing limitation. This device has a shared routing resource connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction means that these pairs of pins must be driven by the same signal or one of the signals will be unroutable. Before continuing please remove the placement constraints or move one of these IOBs to a new location. Has anyone had this problem and found a way around it. ThanksArticle: 128538
John McCaskill <jhmccaskill@gmail.com> writes: > As luck would have it I just got a call from someone at Mentor > Graphics so I asked them about this. What they told me is that if you > are using only Verilog in your design, you do not need the extra > license for Smartmodels. If you are using any VHDL, you do need the > license. When I asked why, they said that they would have to ask > someone else and get back to me. My guess is that with Verilog the "calls to external stuff" (PLI) is built into the core, with VHDL the Foreign Language Interface is an extra which is more simulator specific. And hence they can charge you for a more expensive license... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 128539
"maxascent" <maxascent@yahoo.co.uk> wrote in message news:8YCdnQSA7buT2D3a4p2dnAA@giganews.com... > > Hi > > I have design that will PAR fine when chipscope is not included but when > it is I get the following error :- > > The placement constraints of the IOBs app_rd_n and app_AD[7] makes this > design unroutable due to a physical routing limitation. This device has a > shared routing resource connecting the ICLK and OTCLK pins on pairs > of IOBs. This restriction means that these pairs of pins must be driven > by the same signal or one of the signals will be unroutable. Before > continuing please remove the placement constraints or move one of these > IOBs to a new location. > > Has anyone had this problem and found a way around it. > > Thanks Hi Jon, This is maybe because the tools have mapped FFs into a pair of IOBs that then require too many clocks for the routing resource available. The chipscope instantiation has probably added an extra IOB FF that's caused this problem. Try turning off the 'Pack I/O Registers/Latches into IOBs' option in the Map tool. HTH., Syms.Article: 128540
Hi all, I've something strange in my design... I think there is something I don't understand.. I've a clock distributed on a global clock network, It seems to be ok.. In the "Clock report" from the ISE PAR, I can read a "net skew" of 0.276ns and a max delay of 1.779ns (I'm using a virtex5 XC5VLX50). But when I use trce to look for timing violations, I found hold violations With a "data path delay" of 2.476, and my "max delay" for the clock ( 1.779ns ), it should work.. But trce reports a "positive clock path skew" equal to 6.898ns.. that's why I've some timing violations... My question is, how can I've a "positive clock path skew" greater than the "max delay" from the clock report ? Is it a consequence of the clock fanout (374 ) ? Is it because my clock is used in different clock regions ? Thanks for your answers, Best Regards, Michel.Article: 128541
Thanks Syms that has solved the problem. JonArticle: 128542
BigJamesLau@gmail.com pisze: > quartus II sopc builder, jtag debugging mode, tri-state avalon bridge, > sdram, on-chip ram, etc > Not in quartus. NIOS IDE -> Project -> System lib config AdamArticle: 128543
On Wed, 30 Jan 2008 09:40:13 +0000, Martin Thompson <martin.j.thompson@trw.com> wrote: >John McCaskill <jhmccaskill@gmail.com> writes: > >> As luck would have it I just got a call from someone at Mentor >> Graphics so I asked them about this. What they told me is that if you >> are using only Verilog in your design, you do not need the extra >> license for Smartmodels. If you are using any VHDL, you do need the >> license. When I asked why, they said that they would have to ask >> someone else and get back to me. > >My guess is that with Verilog the "calls to external stuff" (PLI) is >built into the core, with VHDL the Foreign Language Interface is an >extra which is more simulator specific. And hence they can charge you >for a more expensive license... I accidentally confirmed this yesterday in conversation with someone from Mentor's UK distributor (Saros). SmartModels are accessed from VHDL through the "Swift Interface" and this is the [reason|excuse] for the extra license charge. I believe the dual-language license also allows access from VHDL (or Verilog) without additional charge. - BrianArticle: 128544
On Tue, 29 Jan 2008 14:56:56 -0000, "Symon" <symon_brewer@hotmail.com> wrote: >"Brian Drummond" <brian_drummond@btconnect.com> wrote in message >news:s6fup350dvj91v096p3hrdtbj1qa2015ka@4ax.com... >> On Tue, 29 Jan 2008 11:51:45 -0000, "Symon" <symon_brewer@hotmail.com> >> wrote: >> >>>Guys, >>>I saw this and thought of you... >>>http://forums.xilinx.com/xlnx/board/message?board.id=ISE&thread.id=1196&view=by_date_ascending&page=1 >>>HTH., Syms. >> >> In your opinion, how are the Xilinx forums shaping up as a useful tool for >> exchanging information? >> >> - Brian > >Hi Brian, >No idea, I only went there because it was the solitary hit for >'Downloader.Swizzor xilinx'! >Cheers, Syms. That probably answers the question actually. I poked around and didn't see very much of interest. Maybe occasionally useful but who needs another daily timesink? - BrianArticle: 128545
On Wed, 30 Jan 2008 02:25:35 -0800 (PST), michel.talon@gmail.com wrote: >Hi all, > >I've something strange in my design... I think there is something I >don't understand.. > >I've a clock distributed on a global clock network, It seems to be >ok.. >In the "Clock report" from the ISE PAR, I can read a "net skew" of >0.276ns and a max delay of 1.779ns (I'm using a virtex5 XC5VLX50). >But when I use trce to look for timing violations, I found hold >violations >With a "data path delay" of 2.476, and my "max delay" for the clock >( 1.779ns ), it should work.. >But trce reports a "positive clock path skew" equal to 6.898ns.. >that's why I've some timing violations... Is the clock multiplied or divided in a DCM? I have been somewhat confused by (e.g) 3.4 ns skews relative to a 2x clock output, being reported as a 6.8ns skew relative to the original clock... - BrianArticle: 128546
On 30 jan, 14:33, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Wed, 30 Jan 2008 02:25:35 -0800 (PST), michel.ta...@gmail.com wrote: > >Hi all, > > >I've something strange in my design... I think there is something I > >don't understand.. > > >I've a clock distributed on a global clock network, It seems to be > >ok.. > >In the "Clock report" from the ISE PAR, I can read a "net skew" of > >0.276ns and a max delay of 1.779ns (I'm using a virtex5 XC5VLX50). > >But when I use trce to look for timing violations, I found hold > >violations > >With a "data path delay" of 2.476, and my "max delay" for the clock > >( 1.779ns ), it should work.. > >But trce reports a "positive clock path skew" equal to 6.898ns.. > >that's why I've some timing violations... > > Is the clock multiplied or divided in a DCM? I have been somewhat confused by > (e.g) 3.4 ns skews relative to a 2x clock output, being reported as a 6.8ns skew > relative to the original clock... > > - Brian First, thanks, but the clock is divided using a counter ( because frequency is too low for using DCM). The original source clock is 48MHz, and after counter, I obtain a 2MHz clock which is distributed accross the global clock network MichelArticle: 128547
On Jan 30, 8:22 am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Tue, 29 Jan 2008 14:56:56 -0000, "Symon" <symon_bre...@hotmail.com> wrote: > >"Brian Drummond" <brian_drumm...@btconnect.com> wrote in message > >news:s6fup350dvj91v096p3hrdtbj1qa2015ka@4ax.com... > >> On Tue, 29 Jan 2008 11:51:45 -0000, "Symon" <symon_bre...@hotmail.com> > >> wrote: > > >>>Guys, > >>>I saw this and thought of you... > >>>http://forums.xilinx.com/xlnx/board/message?board.id=ISE&thread.id=11... > >>>HTH., Syms. > > >> In your opinion, how are the Xilinx forums shaping up as a useful tool for > >> exchanging information? > > >> - Brian > > >Hi Brian, > >No idea, I only went there because it was the solitary hit for > >'Downloader.Swizzor xilinx'! > >Cheers, Syms. > > That probably answers the question actually. I poked around and didn't see very > much of interest. Maybe occasionally useful but who needs another daily > timesink? > > - Brian I think you'll find a lot of posts by Xilinx users who aren't familiar with comp.arch.fpga, and since the new forum site has taken away the portal to c.a.f they are not likely to find it as quickly as they used to. My biggest gripe with the Xilinx forums is the excessive compartmentalizing and lack of a "latest posts" view. There are many other supporters of "latest post" view in the forums, but so far the site hasn't been updated to include it. In the meantime my guess is that people unaware of c.a.f will post on the Xilinx forums, and those who know of c.a.f will continue to post here for a quicker response from a broader user base. Regards, GaborArticle: 128548
On Jan 30, 12:11=A0am, "BobW" <nimby_NEEDS...@roadrunner.com> wrote: > <cpan...@yahoo.com> wrote in message > > news:02be1a91-ec9b-49a6-824b-b80b8daf1301@s13g2000prd.googlegroups.com... > > >I have a Spartan3 Bank VCCO pins connected to 1.8V. =A0Normally I use > > this bank to generate 1.8V push-pull signals but I needto drive out > > 3.3V signal on this bank. =A0Can I drive out open drain output with > > external pull-up resistor to 3.3V on a 1.8V I/O bank? > > > Thanks. > > > CP > > There are diodes on each I/O that will prevent that I/O from going above > VCCO or below GND by more than a "diode drop". > > If the resistor is large enough you won't do any damage, but you won't get= > the high level voltage you're expecting. > > Bob Hi, I was thiking that I use these outputs as static signals but even with a week pullup (100KOhm), it seem that the high voltage will still not reach to 3.3V unless, I use external voltage translator from 1.8 to 3.3 Thanks. CPArticle: 128549
<michel.talon@gmail.com> wrote in message news:b6463e24-298a-4d03-afc1-569147a515a4@e6g2000prf.googlegroups.com... > > First, thanks, > but the clock is divided using a counter ( because frequency is too > low for using DCM). The original source clock is 48MHz, and after > counter, I obtain a 2MHz clock which is distributed accross the global > clock network > > Michel Hi Michel, Don't do that. Use the 48MHz clock for clocking everything. Generate a clock enable signal that is high for one clock cycle out of 24. Use the clock enable for the FFs which you want to clock at 2MHz. HTH., Syms.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z