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Hi,
I am currently working on a microblaze v6.00 core on FPGA and am
developing an algorithm. This is what I am doing
1) matlab on PC sends data to microblaze (FPGA) via UART. RS232
hardware handshaking is deployed here.
2) the algorithm runs on microblaze to process the input data
3) microblaze sends the data back to matlab on PC.
the setup I am working on works perfectly on a previous FPGA board.
I have just migrated the setup to another FPGA board for FPGA resource
expansion reasons. However, microblaze no longer sends the data back
to PC. Here are some other details
1) I have ensured that the board is able to send data back and forth
from PC to microblaze via UART in both directions in matlab. thus code
like this works:
int main() {
get_params(); //get data from UART using blocking statements
return_result(); //return results back to PC via UART.
}
2) the C code which doesnt work however looks like this in normal
operation unless I am in debug mode. :(
int main(){
get_params(); //get data from UART using blocking statements
start_algo(); //to start algo
return_result(); //return results back to PC via UART.
}
void start_algo(){
// I inserted a breakpoint around here.
...the rest of the algo....
}
when I use a debugger to debug, by inserting a breakpoint somewhere up
in the start_algo() function. Whenever I do that, the return_result()
function works just fine and returns the expected data correctly.
However, normal operation (without use of a debugger) just fails to
work. I have been working on this for quite a while and am clueless
how else further to debug.
any suggestions would really help.
thanks in advance!
Chris
Article: 128926On Feb 9, 10:46=A0am, morphiend <morphi...@gmail.com> wrote: > On Feb 8, 11:05 am, Mike Treseler <mike_trese...@comcast.net> wrote: > > > Clemens wrote: > > > I put a timing constraint in the UCF File where i asked for a minimum > > > frequency of 35 MHz (29 ns) but unfortuatenly XST tells me that > > > the ratio was not met and the actual ratio is 38 ns. I have already > > > optimized for speed, it there any way to tell the tool it should > > > sythesis it for more than 35 MHz forgetting about any area constraints= ? > > > It sounds like synthesis has done its best. > > I would find the slow nets and pipeline them. > > > =A0 =A0 =A0 =A0 =A0-- Mike Treseler > > There are other things that can be done. > > One of the first ones is to use the Timing Analyzer from ISE. This > tool will give you some good ideas to try and make your design work. > It will also let you see exactly how you're failing the timing on that > clock. > > Another option is to try multi-pass map/place-and-route. I say both > because as of the 9.1 version of the tools, you have to perform MAP > and PAR at the same cost-table value for it to work as expected. If > you're solely using ISE, this can be enabled from one of the menu's, > somewhere. I do most of my work in EDK and I have a script that I use > to perform multi-pass place and route. If you're interested, I could > post it. > > Another option that was introduced in the 9.1 version of the ISE tools > is called the xplorer script. This is a more advanced version of multi- > pass place and route (aka mppr). Previously, mppr just changed the > cost table value and as such the placing of the design was affected. > Now with the new xplorer script, it not only performs cost table > changes, but trying advanced options for different types of algorithms > for specific problems. > > Odds are using timing analyzer is all you need to do, and hopefully > won't need to start worrying about mppr or xplorer yet. Those are > usually used when trying to achieve higher frequencies than the one > you mentioned (>100MHz fabric speeds). > > -- Mike Hi Mike, Possible to post the mppr and xplorer script? thanks in advance! ChrisArticle: 128927
On Feb 10, 5:20 pm, chrisde...@gmail.com wrote:
> Hi,
> I am currently working on a microblaze v6.00 core on FPGA and am
> developing an algorithm. This is what I am doing
>
> 1) matlab on PC sends data to microblaze (FPGA) via UART. RS232
> hardware handshaking is deployed here.
> 2) the algorithm runs on microblaze to process the input data
> 3) microblaze sends the data back to matlab on PC.
>
> the setup I am working on works perfectly on a previous FPGA board.
> I have just migrated the setup to another FPGA board for FPGA resource
> expansion reasons. However, microblaze no longer sends the data back
> to PC. Here are some other details
>
> 1) I have ensured that the board is able to send data back and forth
> from PC to microblaze via UART in both directions in matlab. thus code
> like this works:
> int main() {
> get_params(); //get data from UART using blocking statements
> return_result(); //return results back to PC via UART.
>
> }
>
> 2) the C code which doesnt work however looks like this in normal
> operation unless I am in debug mode. :(
>
> int main(){
> get_params(); //get data from UART using blocking statements
> start_algo(); //to start algo
> return_result(); //return results back to PC via UART.
>
> }
>
> void start_algo(){
> // I inserted a breakpoint around here.
> ...the rest of the algo....
>
> }
>
> when I use a debugger to debug, by inserting a breakpoint somewhere up
> in the start_algo() function. Whenever I do that, the return_result()
> function works just fine and returns the expected data correctly.
>
> However, normal operation (without use of a debugger) just fails to
> work. I have been working on this for quite a while and am clueless
> how else further to debug.
>
> any suggestions would really help.
>
> thanks in advance!
> Chris
Well I would first look at compiler optimizations. Some time debug
operation has NO optimizations while 'release' has some.
Look at the code produces with and with out. If it's not IDENTICAL
then that a good place to look.
Then break points might give hardware a chance to ketch up. Try debug
with no breakpoints. That should also yield clues.
Switch to Altera and NIOS. (Just kiddine).
keep us posted.
george
Article: 128928Hi, I have designed a 3-bit counter in Xilinx ISE Webpack software and am trying to download VHDL codes to Spartan 3A FPGA starter kit. Can anyone tell me how to download my codes to FPGA. I am a beginner so i would prefer a detailed answer. Thanks Anas.Article: 128929
Mark McDougall wrote:
> I'm actually starting to use blocks more often now, to avoid long lists of
> signals in the entity declaration that are hard to find in the code. If
> there's a functional block that I don't want to instantiate as another
> nested entity, I'll use a block and define any local signals that have no
> scope outside the function.
An alternative is to use variable data structures
each with a per-tick update procedure.
> I guess I should also mention that my original background is software, so
> perhaps I'm coming in with a different mind-set.
My original background is hardware,
but I have grown fond of vhdl functions,
procedures and structured variables.
You never know what someone is going to like ;)
> Feel free to disagree, but I doubt you'll change my mind. I've seen enough
> code now (good and bad) to know what I do and don't like... ;)
I guess I prefer full structural or full procedural.
I'll take an instance over a block.
But don't change your mind on my account.
I think Andy would back you up.
-- Mike Treseler
Article: 128930anas_waris@hotmail.com wrote: >I have designed a 3-bit counter in Xilinx ISE Webpack software and am >trying to download VHDL codes to Spartan 3A FPGA starter kit. Can >anyone tell me how to download my codes to FPGA. I am a beginner so i >would prefer a detailed answer. Thanks You need to use the Xilinx ISE Webpack to convert the VHDL (or Verilog) source into a bitstream file (.bit). Then you use either parallell adapter or usb cable to download the bitstream to the Spartan 3A FPGA starter kit. This can be done with the "Impact" application within Xilinx ISE Webpack. If you want any more help you should state: Operating system. Graphical or commandline user interface. Transfer hardware, parallell or usb.Article: 128931
On 2008-02-07, maverick <sheikh.m.farhan@gmail.com> wrote: >============================================== > Virtex 2 Pro support in higher versions of ISE: >=============================================== > I have ML310 board with Virtex 2Pro xc2vp30 on it. ISE 7.1 has the > support for the particular family and deivce however, I dont see the > same part appearing in ISE 8.1 or ISE 9.2. Has the part been > discontinued? If not, how can I add the library for the particular > device in ISE 8.1 or ISE 9.2. You should still have XC2VP30 support in ISE 9.2. (I think it is even included in the webpack version of ISE 9.2 now.) However, I have heard rumors that EDK 9.2 doesn't support XC2VP* devices but I haven't verified it myself since I'm not a big user of EDK. /AndreasArticle: 128932
On Feb 11, 10:44=A0am, anas_wa...@hotmail.com wrote: > Hi, > > I have designed a 3-bit counter in Xilinx ISE Webpack software and am > trying to download VHDL codes to Spartan 3A FPGA starter kit. Can > anyone tell me how to download my codes to FPGA. I am a beginner so i > would prefer a detailed answer. Thanks > > Anas. Hi, Anas. 1st step, Synthesize the code, double click the synthesize command, 2nd step, assign pins in PACE which is found under user constraints command 3rd step: double click implement design. 4th step: double click on config bitstream. Since the last time I used Spartan Starter kit was quite a while ago, I would suggest that mayb you take about 1/2 an hr to go through the help tab/ tutorial on ISE which gives very detail steps on the process especially the last part which involves downloading the bitstream into the kit using iMPACT. You can skip the simulation parts though in that tutorial. Of course you might have to prepare yourself for any syntax errors of the sort when you go through all the process I have said just now. Wish you luck.. Regards, BryanArticle: 128933
On Feb 10, 10:50 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > kian.zar...@gmail.com wrote: > > # ** Error: fftk4.vhd(37): Library unisim not found. > > # ** Error: fftk4.vhd(38): (vcom-1136) Unknown identifier "unisim". > > what should i do? > > http://groups.google.com/groups/search?q=modelsim+unisim+library I think you have not compiled libraries in xilinx keeping target browser as modelsim. you can do this by selecting the project's fpga package in (on left top browser), in properties u can assign target browser. After u do this when u highlight the package in browser u'll see compile hdl libraries in the window below. compile it and libraries will be compiled in installed XILINX folder(search tht) change the the pref .tcl if ur confident about procedure to add libraries with path or in modelsim u can add libraries just mention the path. after u do this u shld see all the sim libraries (unisim, primsim and coresim) in the modelsim library window(below work library)Article: 128934
Saw this on Slashdot. http://csg.csail.mit.edu.nyud.net/oshd/index.html Quote:- Projects H.264: HD quality H.264 baseline profile decoder. OFDM: OFDM transceiver (transmitter and receiver), highly parameterized to cover 802.11a (WiFi), 802.16 (WiMax) and others in the future. Support for 802.15 (WUSB) is currently being worked on. 802.11a: 802.11a WiFi transmitterArticle: 128935
GMM50 wrote:
> On Feb 10, 5:20 pm, chrisde...@gmail.com wrote:
>> Hi,
>> I am currently working on a microblaze v6.00 core on FPGA and am
>> developing an algorithm. This is what I am doing
>>
>> 1) matlab on PC sends data to microblaze (FPGA) via UART. RS232
>> hardware handshaking is deployed here.
>> 2) the algorithm runs on microblaze to process the input data
>> 3) microblaze sends the data back to matlab on PC.
>>
>> the setup I am working on works perfectly on a previous FPGA board.
>> I have just migrated the setup to another FPGA board for FPGA resource
>> expansion reasons. However, microblaze no longer sends the data back
>> to PC. Here are some other details
>>
>> 1) I have ensured that the board is able to send data back and forth
>> from PC to microblaze via UART in both directions in matlab. thus code
>> like this works:
>> int main() {
>> get_params(); //get data from UART using blocking statements
>> return_result(); //return results back to PC via UART.
>>
>> }
>>
>> 2) the C code which doesnt work however looks like this in normal
>> operation unless I am in debug mode. :(
>>
>> int main(){
>> get_params(); //get data from UART using blocking statements
>> start_algo(); //to start algo
>> return_result(); //return results back to PC via UART.
>>
>> }
>>
>> void start_algo(){
>> // I inserted a breakpoint around here.
>> ...the rest of the algo....
>>
>> }
>>
>> when I use a debugger to debug, by inserting a breakpoint somewhere up
>> in the start_algo() function. Whenever I do that, the return_result()
>> function works just fine and returns the expected data correctly.
>>
>> However, normal operation (without use of a debugger) just fails to
>> work. I have been working on this for quite a while and am clueless
>> how else further to debug.
>>
>> any suggestions would really help.
>>
>> thanks in advance!
>> Chris
>
> Well I would first look at compiler optimizations. Some time debug
> operation has NO optimizations while 'release' has some.
> Look at the code produces with and with out. If it's not IDENTICAL
> then that a good place to look.
>
Code that works when optimisations are turned off, and that fails when
optimisations are turned on, is incorrect code - look for things like
missing "volatile" declarations.
That said, playing with the optimisation settings might give you a clue
as to what is going wrong.
> Then break points might give hardware a chance to ketch up. Try debug
> with no breakpoints. That should also yield clues.
>
> Switch to Altera and NIOS. (Just kiddine).
>
> keep us posted.
>
> george
Article: 128936
Hello all,
I am selling a one-year old Celoxica RC340 Expert board.
This board is from Celoxica, the well-know ESL provider.
http://www.celoxica.com
Key features
- Virtex-4 4VLX160-10-4
- Dual Gigabit Ethernet MAC/PHY
- 4 banks x 2M x 36bits ZBT SRAM providing a total of 32Mbytes
- DIMM socket for user provided SDRAM memory
- Dual DVI in & out
- Dual composite in
- Dual S-Video in & out
- Dual VGA out
- AC97 audio
- SPDIF digital audio
-SDCARD
- Microprocessor controller for
- USB port management
- FPGA configuration/reconfiguration
- SDCard management
- Dual RS232 ports
- PS2 Keyboard & Mouse ports
- 16x4 iluuminated LCD
- 4 switches
- 8 white LED
- 50 pins expansion connector
- JTAG connector
- 1024x768 TFT display
More details here : http://www.celoxica.com/products/rc340/default.asp
Contact me for offers.
Best regards.
Article: 128937Hi I finally have successfully sythesised my design, unfortunately the critical path seems to be quite long so that i have a low frequency. Can anybody tell me whats the best way to identify the critical path? I used the Xilinx toolsuite, and there is a timing analyser so probably this one is the best bet?Article: 128938
I have a question about a conversion of an unsigned 10-bit vector to signed 8 bit vector. What is the best : signed_data(7 downto 0) <= STD_LOGIC_VECTOR(to_signed(to_integer(unsigned(unsigned_data)), 8)); or if ( unsigned_data = "00000000" ) then signed_data <= "10000001"; else signed_data <= (not unsigned_data(9)) & unsigned_data(8 downto 0); end if; tk.Article: 128939
"Clemens" <Clemens12@yahoo.com> wrote in message news:fopcju$hsj$1@aioe.org... > Hi > > I finally have successfully sythesised my design, unfortunately the > critical path seems to be quite long so that i have a low frequency. > Can anybody tell me whats the best way to identify the critical path? > I used the Xilinx toolsuite, and there is a timing analyser so probably > this one is the best bet? Yes.Article: 128940
"LilacSkin" <lpaulo07@iseb.fr> wrote in message news:6f2aa7d9-1627-46e8-b67e-423491be6791@i12g2000prf.googlegroups.com... >I have a question about a conversion of an unsigned 10-bit vector to > signed 8 bit vector. > What is the best : > > tk. http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdfArticle: 128941
Hi All , I have am having problems interfacing my custom IP with uBlaze using FSL. I am using the older version of uBlaze (version 4.00.a) and the FSL bus that I am using is version 2.11.a. Is there a imcompatability between the above versions, cause when I use version 7.00.a of uBlaze to test with a idct module provided with an application note it seems to work , but not with 4.00.a. BR rateArticle: 128942
On Feb 10, 9:44=A0pm, anas_wa...@hotmail.com wrote: > Hi, > > I have designed a 3-bit counter in Xilinx ISE Webpack software and am > trying to download VHDL codes to Spartan 3A FPGA starter kit. Can > anyone tell me how to download my codes to FPGA. I am a beginner so i > would prefer a detailed answer. Thanks > > Anas. Hi, This tutorial is a good one to get you started, just do as it says, but replace Device Family, Package and Speed Grade according to your FPGA. http://toolbox.xilinx.com/docsan/xilinx6/books/docs/qst/qst.pdf All the best. Pallavi.Article: 128943
On 11 Feb., 12:48, LilacSkin <lpaul...@iseb.fr> wrote: > I have a question about a conversion of an unsigned 10-bit vector to > signed 8 bit vector. u(7) <= '0'; u(6 downto 0) <= s(6 downto 0); Kolja SulimmaArticle: 128944
On 11 f=E9v, 13:46, "comp.arch.fpga" <ksuli...@googlemail.com> wrote: > On 11 Feb., 12:48, LilacSkin <lpaul...@iseb.fr> wrote: > > > I have a question about a conversion of an unsigned 10-bit vector to > > signed 8 bit vector. > > u(7) <=3D '0'; > u(6 downto 0) <=3D s(6 downto 0); > > Kolja Sulimma unsigned =3D> signedArticle: 128945
On Mon, 11 Feb 2008 04:46:52 -0800 (PST), "comp.arch.fpga"
<ksulimma@googlemail.com> wrote:
>On 11 Feb., 12:48, LilacSkin <lpaul...@iseb.fr> wrote:
>> I have a question about a conversion of an unsigned 10-bit vector to
>> signed 8 bit vector.
>
>u(7) <= '0';
>u(6 downto 0) <= s(6 downto 0);
(where 's' is the 10-bit unsigned source, and 'u' is the
8-bit unsigned target, presumably.)
Or, if you want saturating behaviour instead of truncation:
signed_8(7) <= '0';
if unsigned_10(9 downto 7) = "000" then
--- within range, 7 least-significant bits are OK
signed_8(6 downto 0) <= unsigned_10(6 downto 0);
else
--- over-range, saturate to largest possible value
signed_8(6 downto 0) <= (others => '1');
end if;
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 128946What I want to do is : unsigned min: 0000000000 => signed min: 1 000001 => integer min : -127 unsigned max: 1111111111 => signed max: 0 1111111 => integer max : 127Article: 128947
On Mon, 11 Feb 2008 05:06:54 -0800 (PST), LilacSkin <lpaulo07@iseb.fr> wrote: >What I want to do is : > >unsigned min: 0000000000 => signed min: 1 000001 => integer min : >-127 >unsigned max: 1111111111 => signed max: 0 1111111 => integer max : 127 You didn't tell us that :-) Do you also want linear scaling between these two endpoints? I guess so. Let's start again. You have unsigned input U in the range [0,1023]. You have signed output S in the range [-127, +127]. I don't know why you choose to exclude -128, but hey, that's OK. So what do you want to do? S = U/4 - 127 is pretty close, I think, if U/4 is taken to mean the whole-number part of the result (throw away the fraction). But unfortunately, 1020/4 = 255 and 255-127 = 128, so you'll get +128 rather than +127 as the upper limit. If you can accept -128 as the lower limit (this is the true minimum value of a signed 8-bit) then you can do S = U/4 - 128 and all is well. Now, U/4 is simply the eight most significant bits of U; and -128 is easily done by just flipping the MSB; so S <= (not U(9)) & U(8 downto 2); will do the job. Now will you finally listen to your tutors and understand that THE MOST IMPORTANT THING IS A GOOD SPECIFICATION? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 128948
On 11 f=E9v, 14:44, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Mon, 11 Feb 2008 05:06:54 -0800 (PST),
>
> LilacSkin <lpaul...@iseb.fr> wrote:
> >What I want to do is :
>
> >unsigned min: 0000000000 =3D> signed min: 1 000001 =3D> integer min :
> >-127
> >unsigned max: 1111111111 =3D> signed max: 0 1111111 =3D> integer max : 12=
7
>
> You didn't tell us that :-)
>
> Do you also want linear scaling between these two endpoints?
> I guess so. Let's start again.
>
> You have unsigned input U in the range [0,1023].
>
> You have signed output S in the range [-127, +127].
> I don't know why you choose to exclude -128, but hey,
> that's OK.
>
> So what do you want to do?
>
> S =3D U/4 - 127
>
> is pretty close, I think, if U/4 is taken to mean the
> whole-number part of the result (throw away the fraction).
> But unfortunately, 1020/4 =3D 255 and 255-127 =3D 128, so you'll
> get +128 rather than +127 as the upper limit. If you can
> accept -128 as the lower limit (this is the true minimum
> value of a signed 8-bit) then you can do
>
> S =3D U/4 - 128
>
> and all is well. Now, U/4 is simply the eight most significant
> bits of U; and -128 is easily done by just flipping the MSB; so
>
> S <=3D (not U(9)) & U(8 downto 2);
>
> will do the job.
>
> Now will you finally listen to your tutors and understand
> that THE MOST IMPORTANT THING IS A GOOD SPECIFICATION?
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.
so, I return to my first message, that is correct :
if ( unsigned_data =3D "00000000" ) then
signed_data <=3D "10000001";
else
signed_data <=3D (not unsigned_data(9)) & unsigned_data(8
downto 0);
end if;
Article: 128949Hi all, I've a problem.. :) I have to divide a 48MHz clock to obtain a clock with differents frequencies : 100KHz, 500KHz, 1 MHz or 2 MHz. First I used flips flops to make a frequency divider, I obtained the good frequencies, but I had skew between my master clock (48MHz) and my divided clock. So, I tried to use a DCM to divide frequency and to deskew divided clock using the CLKFB input. But, the problem is the lower limit of the DCM output frequency (1MHz) .. So, if anyone have an idea ? Thanks by advance, Best regards, Michel.
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