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"Dwayne Dilbeck" <ddilbeck@yahoo.com> wrote in message news:13tdjb1pr0od7cd@corp.supernews.com... > Video 3b - At the end you recomend that your viewers purchase a Digilent > board. You should add the reason for this recomendation. That reason being > that future videos will be easier to follow if they purchase the digilent > board. Althouhg the videos can be used with a non- digilent board. > Hi Dwayne, In video 3b, we do take a quick look at other boards including Xess, Trenz, Enterpoint, KNJN & the list at fpga-faq. The reason I recommend Digilent is that because, in my opinion only, they are excellent value boards. I do say that in the videos, but I probably should more clearly state the reason for the recommendation. You are right, it doesn't matter which board you have. The course is intended to be generic. So, for example, in video 13 where you enter I/O pad constraints, instead of looking in the Digilent Board Manual, you look in your own FPGA board manual to find out which pins the LEDs etc. are connected on you board. The video course should be equally easy to follow, independent of which board you have. By the way, another board that I didn't look at in the videos and I would have liked to include is the DLP Design Spartan-3E board called DLP-FPGA http://www.dlpdesign.com/ Kind regards, Anthony The BurchED Getting Started With Xilinx FPGAs Video Guide http://www.BurchED.comArticle: 129976
Hi,
Some IP vendors gives the complexity of the device in terms of "LCs
(Logic Cells)".
How can I calcuate Logic cells from information available in Map
report?
**********
Logic Utilization:
Number of Slice Flip Flops: 4,288 out of 84,352 5%
Number of 4 input LUTs: 7,880 out of 84,352 9%
Logic Distribution:
Number of occupied Slices: 5,150 out of
42,176 12%
Number of Slices containing only related logic: 5,150 out of
5,150 100%
Number of Slices containing unrelated logic: 0 out of
5,150 0%
*See NOTES below for an explanation of the effects of unrelated
logic
Total Number of 4 input LUTs: 8,119 out of 84,352 9%
Number used as logic: 7,880
Number used as a route-thru: 159
Number used for Dual Port RAMs: 80
(Two LUTs used per Dual Port RAM)
Number of bonded IOBs: 500 out of 576 86%
Number of BUFG/BUFGCTRLs: 5 out of 32 15%
Number used as BUFGs: 5
Number used as BUFGCTRLs: 0
**************
Thanks in advance,
Muthu
Article: 129977Tony Burch <tony@burched.com.au> wrote: >"Dwayne Dilbeck" <ddilbeck@yahoo.com> wrote in message >news:13tdjb1pr0od7cd@corp.supernews.com... >> Video 3b - At the end you recomend that your viewers purchase a Digilent >> board. You should add the reason for this recomendation. That reason being >> that future videos will be easier to follow if they purchase the digilent >> board. Althouhg the videos can be used with a non- digilent board. >> >Hi Dwayne, >In video 3b, we do take a quick look at other boards including Xess, Trenz, >Enterpoint, KNJN & the list at fpga-faq. The reason I recommend Digilent is >that because, in my opinion only, they are excellent value boards. I do say >that in the videos, but I probably should more clearly state the reason for >the recommendation. I think enterpoint.co.uk products like the Craignell, Broaddown etc.. is worthwhile to mention. They are good value for the money.Article: 129978
On Mar 12, 2:34 am, sky46...@trline4.org wrote: > satyam <satyam.dwiv...@gmail.com> wrote: > >I want to interface matlab with the Xilinx Virtex-II pro board. Intent > >is to give input from matlab to the FPGA and to read the ouput of FPGA > >in matlab. > >Problem is in interfacing speed. I need high speed interface, of the > >order of 2 mega bits per second (Mbps). Seems RS-232 will be > >inadequate for my purpose. From Documents interface through ethernet > >seems to be a viable option but I am not sure. To summarize I want > >answers and suggestions on following: > >1). FPGA to PC communication by ethernet ? > > Yes works. > > >2). What can be the maximum speed ? > > 1000Mbps depending on your ethernet chip(s). > > >3). How to transfer data on ethernet by matlab ? > > C socket programming > > >4). Is it possible to write inputs (60 Mega bits) to some memory on > >FPGA board and then read it from there to do the computation ? > > If your ethernet PHY manages 100 Mbps in full duplex, then yes. > > >Please let me know if you have any suggestion for me. > > Do you need realtime or synchronous operation? > > Btw, there's lots of good stuff to be found via the google force luke ;) Dear Dave and sky46, thank you for responding. Seems Matlab has something in intrument control toolbox. I need to explore this. How about ethernet core for FPGA. The core provided by xilinx is too expensive to buy. Have found an ethernet from opencore website. Trying to make it work.Article: 129979
Hi, I am loooking for a VME 2 Ghz clock/sync generator board. I find that: -VMETRO XCLK1 -Pentek 6890 Is there a board mixture of the two : clock generator + synchronous trigger @2Ghz ? Thanks!Article: 129980
Until I am waiting for work place to be free (one of the boards running OK and going for test), I want to ask for another old problem. VLX25, configuration memory AT17F16, loading trough FT245. From 6 boards 100% was working fine, and after some testing to customers more than 50% come back with similar fail - FPGA stop to load up from config memory, there is higher power consumption more than usual for unload chip(but not excessive) and JTAG can not found FPGA. Holding reset of flash and even remove the flash from board does not help in any way. There is also some ADC's and ASIC outside which also can be a problem, but it will be different to remove them without destroyng board... Any idea? -- Message posted using http://www.talkaboutelectronicequipment.com/group/comp.arch.fpga/ More information at http://www.talkaboutelectronicequipment.com/faq.htmlArticle: 129981
The Pentek has a delivery time of 10 weeks starting at a price of 5k$. At that price and time scale you might be able to find someone who configures the MGTs of any XC5VLXT evaluation board to perform that function. While the jitter specified for the MGT outputs is a lot higher (10ps IIRC) you should be aware that that value is for random data patterns. If you output a periodic clock the value should be significantly lower. Kolja Sulimma On 12 Mrz., 09:58, LilacSkin <lpaul...@iseb.fr> wrote: > Hi, > > I am loooking for a VME 2 Ghz clock/sync generator board. > I find that: > > -VMETRO XCLK1 > -Pentek 6890 > > Is there a board mixture of the two : clock generator + synchronous > trigger @2Ghz ? > > Thanks!Article: 129982
Until recently comparing 4-LUTs was the way to go. (Except for pathological cases) Now Virtex-5 with its 6-LUTs makes life more complicated. Kolja On 12 Mrz., 04:54, muthu...@gmail.com wrote: > Hi, > Some IP vendors gives the complexity of the device in terms of "LCs > (Logic Cells)". > How can I calcuate Logic cells from information available in Map > report? > > ********** > Logic Utilization: > Number of Slice Flip Flops: 4,288 out of 84,352 5% > Number of 4 input LUTs: 7,880 out of 84,352 9% > Logic Distribution: > Number of occupied Slices: 5,150 out of > 42,176 12% > Number of Slices containing only related logic: 5,150 out of > 5,150 100% > Number of Slices containing unrelated logic: 0 out of > 5,150 0% > *See NOTES below for an explanation of the effects of unrelated > logic > Total Number of 4 input LUTs: 8,119 out of 84,352 9% > Number used as logic: 7,880 > Number used as a route-thru: 159 > Number used for Dual Port RAMs: 80 > (Two LUTs used per Dual Port RAM) > Number of bonded IOBs: 500 out of 576 86% > Number of BUFG/BUFGCTRLs: 5 out of 32 15% > Number used as BUFGs: 5 > Number used as BUFGCTRLs: 0 > ************** > > Thanks in advance, > MuthuArticle: 129983
"Marc Reinig" <Marco@newsgroups.nospam> writes: > I need some references of where systolic arrays have actually been used in > equipment or instruments. I remember from my student time Systola 1024 boards. Afaik there were some papers done with real applications (e.g. DNA Sequencing). I am too lazy to dig that old stuff out, but google "Systola 1024" should reveal some stuff. FlorianArticle: 129984
On 12 mar, 10:16, Kolja Sulimma <ksuli...@googlemail.com> wrote: > The Pentek has a delivery time of 10 weeks starting at a price of 5k$. > > At that price and time scale you might be able to find someone who > configures the MGTs > of any XC5VLXT evaluation board to perform that function. > > While the jitter specified for the MGT outputs is a lot higher (10ps > IIRC) you should be aware > that that value is for random data patterns. If you output a periodic > clock the value should be > significantly lower. > > Kolja Sulimma > > On 12 Mrz., 09:58, LilacSkin <lpaul...@iseb.fr> wrote: > > > Hi, > > > I am loooking for a VME 2 Ghz clock/sync generator board. > > I find that: > > > -VMETRO XCLK1 > > -Pentek 6890 > > > Is there a board mixture of the two : clock generator + synchronous > > trigger @2Ghz ? > > > Thanks! I need slow jitter clocks ! In fact what I need is: -A 2Ghz slow jitter clock generator with a internal 10 Mhz ref or external : XCLK1 VMETRO -8 trigger signals synchronised with a 2 Ghz clock : Pentek 6890 (software/hard input) -in a VME looks like ECSG-1RHSCT MERCURY board. One solution is to plug the XCLK1 VMETRO on the Pentek 6890. But I don't need know if pentek can personalized their boards in order to put a PMC carrier.Article: 129985
Hi. Got this board. Two questions. 1. Is it possible to use this board as prototype of some USB device without any solder rewiring? 2. Is it possible to have, let's say, nios2-terminal.exe on computer side, computer connected to board by USB and have *something* but not Nios2 to communicate with nios2-terminal.exe? In any words, it's possible to use JTAG wire as RS232 port without using Nios2 CPU?Article: 129986
On 27 Feb., 09:33, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > I've seen tools that map into Wide AND. OR (ie CPLD cells), but not > ones that go a step further and use multiple layers of logic, with > intermediate merge nodes. Hmm. Any modern Synthesis will do that. Try Xilinx XST for example. In VHDL define an array with data and use an integer to index that array. Depending on the synthesizer options either a BRAM or combinational logic will be created. The results will not be very good for general data. You can easily proof that most tables can't be implemented with less than 2**N gates for N inputs. However, many useful tables show structure that allows at least some optimizations. Kolja SulimmaArticle: 129987
I finally recieved a reference manual from Altera about the syntax of ADF. (Although it lacks truth tables, which forces me to make some assumptions) If any one needs a copy of this, let me know. One thing I saw was that the T flip flops have inputs. Why?!?Article: 129988
On Mar 12, 7:56=A0am, CTSportPilot <girm...@gmail.com> wrote: > I finally recieved a reference manual from Altera about the syntax of > ADF. =A0(Although it lacks truth tables, which forces me to make some > assumptions) =A0If any one needs a copy of this, you can contact me. > > One thing I saw was that the T flip flops have inputs. =A0Why?!? Sorry about the reply to my own message. I should have known the T input wsas the toggle control. Bleck!Article: 129989
Peter Alfke wrote: > On Mar 11, 7:19 am, "Symon" <symon_bre...@hotmail.com> wrote: >> Hi Paul, >> Yeah, if you look at your code, you're trying to do an asynchronous >> read. I suggest you try simulating your design and also a design >> where you instantiate a block ram. You'll be able to compare and see >> clearly what the block ram does. >> HTH., Syms. > > This is not the first time that someone has tried to read the BRAM > asynchronously. I have posted many times, and also inserted a sentence > into our documentation that "nothing happens without a clock". > Any ideas how we can spread this important (and non-obvious) > information even better and wider??? > Peter Alfke, Xilinx Applications Hi Peter, When the synthesis software itself warns the user "The RAM <XYZ> will be implemented on LUTs because you have described an asynchronous read" and they still don't get it, I'm struggling to see what would be of further help? Cheers, Syms.Article: 129990
On Mar 10, 5:22 am, jshrini.v...@gmail.com wrote: > 1. every virtex series is having maximum frequency where we can use in > some of higher end applications,so virtex, virtexII, virtex-E, and > virtex-II Pro all serieses are having their Max frequency based on > upgradations. So xilinx will design on what kind of basis to enhance > the frequency in higer versions of these serieses and is that every > logic( wether they are combinational or sequential type) having same > kind of frequency(what Max frequency of FPGA is having).? Howdy Sreeni, BTW, not everything gets faster in newer generations. That may have been true through V2Pro, but when we took our pipelined 311 MHz design to V4 certain things did get slower - I believe one of the biggest was related to LUT-RAM's. Going from V4 to V5, we took another F-max hit, this time related to a huge (bad) change in timing for the mode that we are running the BRAM's in (the original design didn't have registered outputs, and it would be a big deal to change it), and surprisingly, routing. We have 3.1 ns to work with, and we have way too many routes that are 2.5 to 3.5 ns. Part of this could likely be fixed with improvement to the tools - one path I was inspecting last night looked like register duplication would fix it - yet the tools weren't inserting duplicate registers. Lastly, also related to tools: they seem to do better if you don't give them a grossly over-large part to work with. Pick a part close to the size you need (in terms of LUTs). MarcArticle: 129991
On 12 Mrz., 10:29, LilacSkin <lpaul...@iseb.fr> wrote: > I need slow jitter clocks ! You probably mean low jitter. > In fact what I need is: > -A 2Ghz slow jitter clock generator with a internal 10 Mhz ref or > external : XCLK1 VMETRO > -8 trigger signals synchronised with a 2 Ghz clock : Pentek 6890 > (software/hard input) > -in a VME looks like ECSG-1RHSCT MERCURY board. This board will do that http://www.xilinx.com/products/devkits/HW-V5-ML52X-UNI-G.htm You need an engineer to configure the FPGA and you need to build a case to fit it into a VME crate if that really is that important for you. Kolja SulimmaArticle: 129992
On Mar 11, 3:53=A0pm, mikechin2...@gmail.com wrote: > We have two of these boards (with the LX50 ES), and both failed the > DDR memory test with a build from the Base System Builder. We > downloaded the test designs from the Avnet Design Resource Center, and > these would sporadically fail. > > We looked at the datasheet for the MT47H16M16BG DDR2, and noticed that > the acceptable frequency range for the DDR is between 125MHz and > 200MHz. The BSB design uses 125MHz, and according to our FAE, the test > design uses 200MHz. Apparently our boards are marginal at both these > extremes. We modified the clock generator in the BSB design to set the > clock to 133MHz and 150MHz, both of these designs passed the memory > test. > > As an aside, when I recompiled my EDK libraries for 9.2, I told it not > to recompile any deprecated cores. Now it looks like there are only > PLB cores availible, is Xilinx phasing out support for OPB? > > We are using EDK/ISE 9.2 with the latest web updates. All Avnet boards go through a functional test prior to shipment. The functional test for this board is available under "V5LX50 Evaluation Test Files" at https://www.em.avnet.com/common/filetree/0,2740,RID%253D0%2526CID%253D43794%= 2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526SRT%253D1%2526LID%253D= 32232%2526PVW%253D%2526PNT%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html You could try this test. If you have found some marginality with your boards, then please send your test case to technical.support@avnet.com. See the following Xilinx Answer Record for the status of OPB: http://www.xilinx.com/support/answers/29567.htm BryanArticle: 129993
Anyone know if Xilinx plans to support the Pipelined Divider for the V5? Is there an equivalent available, buried in some other Xilinx core? Thanks!Article: 129994
hi
i have a question on how to infer a block ram with mismatched ports.
as far as i found out with google and the xilinx manuals this is how
to infer block ram with matching ports in read first mode:
architecture syn of spi_memory_dp is
type ram_type is array (63 downto 0) of std_logic_vector(15 downto
0);
shared variable RAM : ram_type;
begin
process (CLKA)
begin
if CLKA'event and CLKA = '1' then
if WEA = '1' then
RAM(conv_integer(ADDRA)) := DIA;
end if;
DOA <= RAM(conv_integer(ADDRA));
end if;
end process;
process (CLKB)
begin
if CLKB'event and CLKB = '1' then
if WEB = '1' then
RAM(conv_integer(ADDRB)) := DIB;
end if;
DOB <= RAM(conv_integer(ADDRB));
end if;
end process;
end syn;
could somebody help me out how to modify this so that the data width
on port A is 32 bits and on port B 8 bits.
sorry but i could not find an example for this or figure it out
myself.
also is my example state of the art or should i change something?
thanks
urban.
Article: 129995On Mar 12, 10:05=A0am, "u_stad...@yahoo.de" <u_stad...@yahoo.de> wrote: > hi > > i have a question on how to infer a block ram with mismatched ports. > as far as i found out with google and the xilinx manuals this is how > to infer block ram with matching ports in read first mode: > > architecture syn of spi_memory_dp is > =A0 =A0 =A0 =A0 type ram_type is array (63 downto 0) of std_logic_vector(1= 5 downto > 0); > =A0 =A0 =A0 =A0 shared variable RAM : ram_type; > begin > =A0 =A0 =A0 =A0 process (CLKA) > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if CLKA'event and CLKA =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if WEA =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 RAM(conv_i= nteger(ADDRA)) :=3D DIA; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DOA <=3D R= AM(conv_integer(ADDRA)); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 end process; > > =A0 =A0 =A0 =A0 process (CLKB) > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if CLKB'event and CLKB =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if WEB =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 RAM(conv_i= nteger(ADDRB)) :=3D DIB; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DOB <=3D R= AM(conv_integer(ADDRB)); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 end process; > end syn; > > could somebody help me out how to modify this so that the data width > on port A is 32 bits and on port B 8 bits. > sorry but i could not find an example for this or figure it out > myself. > also is my example state of the art or should i change something? > > thanks > urban. I don't believe port width mismatches can be inferred yet through any synthesis tool. I asked about the capability a few years ago with the Synplicity synthesis products and found the support was not present and not planned. If you want native port mismatches, you'll probably have to instantiate your memory blocks. - John_HArticle: 129996
On Mar 12, 7:05 am, Bryan <bryan.fletc...@avnet.com> wrote: > All Avnet boards go through a functional test prior to shipment. The > functional test for this board is available under "V5LX50 Evaluation > Test Files" athttps://www.em.avnet.com/common/filetree/0,2740,RID%253D0%2526CID%253... That's exactly what I did. I followed the instructions in the User Guide about programming the PROM with the functional test bit file. I get the prompt and various test option choices, they all seem to work except the DDR memory test. I am trying to get our FAE to come out and see this for himself. Thanks for the tip re OPB, we've had misgivings about the Xilinx implementation ever since we had sporadic and unfixable problems with multiple OPB masters. The same designs morphed into PLB masters seem fine. MikeArticle: 129997
On Mar 12, 3:42 am, sdf <drop...@gmail.com> wrote: > Hi. > Got this board. > Two questions. > 1. Is it possible to use this board as prototype of some USB device > without any solder rewiring? > 2. Is it possible to have, let's say, nios2-terminal.exe on computer > side, computer connected to board by USB and have *something* but not > Nios2 to communicate with nios2-terminal.exe? In any words, it's > possible to use JTAG wire as RS232 port without using Nios2 CPU? 1: No. The USB port is only for programming. 2: No. Well, not really no, but you would need to replicate the way Altera/NIOS tunnels the serial port through JTAG, and I think it's highly unlikely that you will find documentation on that. Sorry.Article: 129998
Is 32 bit Xilinx ISE Webpack compatible with 64 bit ChipScope Pro? ISE isn't seeing it when I try to add new source. I originally had the 32 bit ChipScope installed. ISE could see that and I was able to add a Chipscope module to my project. I uninstalled the 32 bit chipscope and installed the 64 bit version, ISE cannot see it now. Any idea what's going on? Thanks, DaleArticle: 129999
Hello, At the moment I am designing a PCIe Card with Spartan 3E 1200 -5 and Xilinx PIPE Core. The firmware is almost done, but I have observed that from time to time a completion is missing for a DMA MEM32 Read request. It seems like the PC doesn't answer my request, what I do not believe. So for example I request 3 packets with TAG 2, 3 and 4 and as mentioned before sometimes the PC answers only with 2 completions -> maybe TAG 3 and 4. I care for transmit buffers as well as for FC credits. I have also tracked the addresses to verify that no unsupported address has been targeted. From the core point of view everything seems to be normal. So has somebody an idea why a read request will not be answered? I thank you guys very much for your help in advance. Nico Presser
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