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On Mar 8, 6:18 am, sdf <drop...@gmail.com> wrote: > Hi. > Analysis and Synthesis for Cyclone III is SO slow.. One my design with > about 30000 ALUTs was analysed and synthesed more than 12 hours and I > finally breaked it. Target device was set to EP3C25F324 (from Cyclone > III FPGA Starter Kit). > The same design analysed and synthesed for Stratix II EP2S60 less than > for one hour. My computer is Intel Core Duo 2.40GHz and 2Gb of RAM. > Is this OK? Am I forgot to turn on/off something in Quartus? Cyclones (I, II, III) doesn't use ALUT, but regular LUTs. Altera estimates an ALUT to be equivalent to 2.5 LUTs, thus you're asking for 75,000 LUTs in a 24,624 LUT device. Assuming this is not just a trivial typo, it's totally expected to take a long time to synthesize when the device is full. As a general rule however, turning off all the advanced synthesize and fitter options will speed up the process. Also, aggressive timing constraints will force both to work harder. TommyArticle: 129901
On Mar 7, 11:36 am, n08W10+mg...@cl.cam.ac.uk (Markus Kuhn) wrote:
> Using strace suggests that things go wrong soon after
> some font-related activity, i.e. soon after the system call
>
> writev(20, [{"-\0\24\0_\0 \1B\0\0\0-adobe-helvetica-bol"..., 92}], 1) = 92
>
> whereas under openSUSE 10.2 it calls instead
>
> write(19, "-\0\24\0x\0 \1B\0\0\0-adobe-helvetica-bol"..., 92) = 92
>
> at the same location, suggestion that there have been
> some changes in libraries.
First, I understand that SUSE 10.3 has more issues than Readers
Digest, but
ignoring that, the above file descriptor difference is unlikely to be
the issue.
You should look back further in the trace to see which file/pipe/
socket/etc
the descriptor correspond to.
You could also copy over from 10.2 the libraries that Quartus and
subprograms
needs and use LD_LIBRARY_PATH to point it to them.
My solution to this general problem is to run Quartus inside a VMware
VM,
and bring the VM along as I moved through an assortment of Linux
distribution
and Mac OS X.
Regards,
Tommy
Article: 129902hi groups I notice that www.opencores.org is down ... the very moment i need jop core... does anybody know if there is a mirror available somewhere ?Article: 129903
On Mar 9, 1:03=A0am, Tommy Thorn <tommy.th...@gmail.com> wrote: > Cyclones (I, II, III) doesn't use ALUT, but regular LUTs. Altera > estimates > an ALUT to be equivalent to 2.5 LUTs, thus you're asking for 75,000 > LUTs > in a 24,624 LUT device. Assuming this is not just a trivial typo, it's > totally > expected to take a long time to synthesize when the device is full. Ah, now I understand the difference between Cyclone and Stratix. Thank you for your reply.Article: 129904
Hi Kyprianos,
Thank you so much for your invaluable suggestions and help. It
actually worked. Now I can use ICAP and I'm reading data from CF and
load it to ICAP.
I'm planning to put a complete kind of tutorial for those who want to
do the same thing and pass on the favor I've been given by people like
you. I'm also recommending everyone who is trying to do the same to
read your paper "Methodology and Experimental Setup for the
Determination of System-level Dynamic Reconfiguration Overhead" if
they want to do dynamic reconfiguration through ICAP.
Best wishes,
Amir
On Mar 2, 5:13 pm, kyprianos <kpapa...@mhl.tuc.gr> wrote:
> On Mar 2, 4:24 am, Xesium <amirhossein.gholamip...@gmail.com> wrote:
>
> > Hi Kyprianos,
> > Thanks a lot for your comments. I checked to make sure that persist
> > bit is also not set. I also checked the base and high address in
> > xparameters.h file and they are as I had set them before. I'm actually
> > configuring my device using parallel cable 4 and through JTAG (I
> > guess!). I wasn't desynchronizing before using ICAP but now I tried
> > doing that to make sure that I'm not doing anything wrong.
>
> Let me clear this. You load the initial configuration through the
> JTAG.
> As you first load the data from JTAG you should set up the
> configuration
> mode pins as M2M1M0=101. Then XHwIcap_CommandDesync() allows you
> to transit to the ICAP.
> Also try the function XHwIcap_DeviceWrite() instead of
> XHwIcap_DeviceWriteFrame().
> The same stands for read, i.e. use XHwIcap_Device instead of
> XHwIcap_DeviceReadFrame().
>
> Did you also do assign OPB_Clk to sys_clk_s?
>
>
>
> > I'm not
> > sure how I can verify ICAP's correct configuration, but I actually
> > print ICAP's base address (using putnum(my_icap.BaseAddress);
> > statement) to make sure that it is the same as what I'd set before and
> > it is actually the same! However the result for me is still the same!
> > I tried changing the Major and Minor address that I'm writing to.
> > Nothing really changes if I just read it. But when I try writing to it
> > (just writing an arbitrary value (0xFFFFFFFF) to some address in the
> > storage buffer!) and then reading it exactly as the following code,
> > sometimes the output of DeviceReadFrame method is that the device is
> > busy and just then it gives me some numbers that some of them actually
> > are not 0. However it never happens that I actually read the same
> > value that I'm writing! I'm wondering, for example in your case, how
> > is the content of the storage buffer when you read back the
> > configuration? Is it mostly 0 and a few of them are non-zero?
> > Should I be reading words or bytes? Because I realized that when I'm
> > reading from compact flash I'm actually reading in bytes not words!
> > when I'm writing to the storage buffer of ICAP should I be writing in
> > bytes or in words? If it should be in words then it means that I have
> > manipulate the data I'm reading from Compact Flash!
>
> The writing to the storage buffer is executed in a word by word
> fashion. When the buffer is full it sends the data to the ICAP port,
> all with one function
> call, and then continues copying. When it is finished copying and
> there is still data in the
> buffer, it writes it to ICAP and the function finishes.
> This is due to the API provided with the opb_hwicap (at least for the
> EDK 7.1i with
> which we conducted the experiments)
> Therefore, yes! you should manipulate the data you transfer from the
> Compact Flash.
> This depends on the API provided with the compact
> flash driver which can only read ASCII character data types from a
> file. This fact
> introduces extra programming effort: The characters that compose a 32
> bit
> word have to be read and combined to form the 32 bit word-number.
> A typical configuration with bitsreams from the compact flash consists
> of the
> following steps:
> -Open the bitstream file stored in the compact flash, identify and
> read the header information,
> -Read a data chunk equal to a multiple of a compact flash sector i.e.
> x 512 bytes,
> -Synthesize a 32-bit ICAP word from every 4 bytes of the data chunk,
> -Load the synthesized word into the ICAP BRAM storage buffer
> .....
>
> > Well that's another problem but for now I can't get the ICAP work and
> > appreciate any suggestion and comment!
> > For now I'll try installing ISE and EDK 9.2 instead of 8.2 and am
> > keeping my fingers crossed that may work!
>
> I can't say anything about ISE+EDK 9.2. We have conducted experiments
> only
> using ISE+EDK 7.1i (for difference-based performance evaluation) and
> ISE 9.1i.02 (for module-based application development)
>
> I hope this help. Let me know about the progress
>
> Good luck,
> Kyprianos
>
> > Thanks a lot,
>
> > Amir
>
> > My code is as follows:
>
> > XHwIcap my_icap;
>
> > XStatus icap_stat;
>
> > icap_stat = XHwIcap_Initialize(&my_icap,
> > XPAR_OPB_HWICAP_0_DEVICE_ID, XHI_READ_DEVICEID_FROM_ICAP);
>
> > if(icap_stat != XST_SUCCESS)
> > print("\n There is something wrong in initializing the ICAP!!
> > \n");
>
> > icap_stat = XHwIcap_CommandDesync(&my_icap);
>
> > if(icap_stat != XST_SUCCESS)
> > print("\n Desynchronization was not successful!\n");
>
> > XHwIcap_StorageBufferWrite(&my_icap, 25, 0xffffffff);
>
> > icap_stat = XHwIcap_DeviceWriteFrame(&my_icap, XHI_FAR_CLB_BLOCK,
> > 20, 32);
>
> > print("A frame has been written to the device\n");
>
> > if(icap_stat != XST_SUCCESS)
> > print("There is something wrong in writing to the device!");
>
> > Xuint32 frame_content;
>
> > icap_stat = XHwIcap_DeviceReadFrame(&my_icap, XHI_FAR_CLB_BLOCK,
> > 20, 32);
>
> > print("The same frame is read from the configuration\n");
>
> > if(icap_stat != XST_SUCCESS)
> > print("\n There is something wrong in reading a frame with col =
> > 5 and lut_bit = 3!!!!!\n");
>
> > if(icap_stat == XST_DEVICE_BUSY)
> > print("\n Device is busy right now!\n");
>
> > if(icap_stat == XST_BUFFER_TOO_SMALL)
> > print("BUFFER is TOO SMULL!\n");
>
> > if(icap_stat == XST_INVALID_PARAM)
> > print("XST_INVALID_PARAM!\n");
>
> > for(i = 0; i < my_icap.WordsPerFrame; i++)
> > {
> > print("word number");
> > putnum(i+1);
> > print(" is equal to: ");
> > frame_content = XHwIcap_StorageBufferRead(&my_icap, i);
> > putnum(frame_content);
> > putchar('\n');
> > }
>
> > On Feb 29, 8:29 pm, kyprianos <kpapa...@mhl.tuc.gr> wrote:
>
> > > > >Microblaze. In bitgen.ut file I have set the value of mode pins
> > > > > (M2M1M0) to 1 (PULLUP). So it is not set on 101 which is JTAG mode. As
> > > > >well the base address and high address of my HWICAP is 0x42000000 and
> > > > >0x42000fff as mentioned in the datasheet of HWICAP. Initially my OPB
>
> > > Amir,
>
> > > In which way to you load the initial configuration? Do you load it
> > > through the ICAP and you don't use
> > > ICAP at all?Did you check the Persist option?
> > > As a second thought check the ICAP configuration. Has it been
> > > configured appropriately? Have the base address and the high address
> > > been added in the xparameters.h file?
>
> > > Take care,
> > > Kyprianos
Article: 129905On 8 Mar, 15:49, Fei Liu <fei....@gmail.com> wrote: > On Mar 8, 9:31 am, lm317t <lm3...@gmail.com> wrote:> Unfortunately you need a local oscillator, several voltage regulators, > > and a config prom or other way of sending the bitstream on power up. > > You can get 3 pcb's for $51 from expresspcb.com If you're in a hurry > > you could also make your own with either UV sensitized PCB's or the > > toner transfer method, but that takes practice. > > Hi Brian > Thanks for your knowledgable reply. I only started learning fpga > very recently and I don't have the tools or experience to do PCB fab > myself at all. > > The expressPCB option is very attractive. So I can order the > boards from expressPCB assuming I can come up with a schematic that > can accommodate my FPGA-3 chip, and a DB9 RS232 serial connection chp. > I assume the PCB will be able to provide a oscillator and voltage > regulator (through schematics) and can then be powered by batteries or > power supply. > > Is there a book or URL that I can learn things like this. I have > read 'Art of Electronics' but it's more of a theoretical treatment of > these subjects. > > > FPGA's are great for generating and receiving high bandwidth timing > > critical signals or computationally intense applications. If you just > > need simple logic (what more do you need for a doorbell?) use a MCU > > like the AVR Atmega series or a Microchip PIC. Most have the option > > of internal oscillators or external osc/crystals, and only require one > > voltage regulator. > > I will look into these options. I am more interested in some hands on > experience at the moment. FPGA just feels too much programming. I have > done enough software programing. I will have a bit more hands on > experience/fun with electronics before going back to programming > again, albeit programming the FPGA hardware. > > Fei Why not just buy one of the $99 Spartan 3 Starter Kits sold by Digilent. That has everything you need on it for a door bell, and lots more. LeonArticle: 129906
On Mar 8, 6:53 pm, sdf <drop...@gmail.com> wrote: > On Mar 9, 1:03 am, Tommy Thorn <tommy.th...@gmail.com> wrote: > > > Cyclones (I, II, III) doesn't use ALUT, but regular LUTs. Altera > > estimates > > an ALUT to be equivalent to 2.5 LUTs, thus you're asking for 75,000 > > LUTs > > in a 24,624 LUT device. Assuming this is not just a trivial typo, it's > > totally > > expected to take a long time to synthesize when the device is full. > > Ah, now I understand the difference between Cyclone and Stratix. > Thank you for your reply. Not quite! Only Stratix II, III, GX II, and Arria GX uses the new structure. (BTW, they are called ALM, whereas the "old" cells were LE). Off-topic: ALM are IMO the most interesting thing that has happened in the FPGA world in years, but I haven't had opportunity to use them yet. Functionally Virtex 5's LUT6 are a strict subset of the ALM (modulo the SRL32 part), but on paper, the ALM is much more powerful and flexible. In the real world everything depends on what the design software does with them. TommyArticle: 129907
On Mar 9, 6:51=A0pm, Tommy Thorn <tommy.th...@gmail.com> wrote: > Off-topic: > ALM are IMO the most interesting thing that has happened in the FPGA > world in years, but I haven't had opportunity to use them yet. > Functionally > Virtex 5's LUT6 are a strict subset of the ALM (modulo the SRL32 > part), > but on paper, the ALM is much more powerful and flexible. In the real > world everything depends on what the design software does with them. Another question is, when it will be possible to program FPGA at low- level, without synthesis and fitting, just like low-level coders downgrading to x86 assembler in past.. I believe, there're some people who eventually wish to try this, if it will be possible.Article: 129908
Symon wrote:
>
> Google data2mem
> HTH., Syms.
It helped, many thanks, and for those, that, by chance, might be reading
this thread I will write a bit about what I did.
First of all the authoritative documentation of data2mem seems to be
http://toolbox.xilinx.com/docsan/xilinx92/books/docs/d2m/d2m.pdf
One could wish for more examples than given in this doc, which I first
put aside as quite indigestible (maybe I was just too tired). But
finally I read it, and after reading through some examples given on the
web and in newsgroup discussions it was much better understandable.
To google efficiently it was necessary to use the search-words
address_space
bus_block
which are keywords in in the data2mem input .bmm file.
For german readers there is a short but useful explanation at
http://www.mikrocontroller.net/articles/T51-Core
(be warned: there is the typo ADDRESS_BLOCK instead of the correct
ADDRESS_SPACE in the example .bmm file shown there).
The essence is, that the syntax to use is
data2mem -bm bmmfile_bd.bmm -bt project.bit -bd newdata.mem -o b final.bit
the files have the following meaning;
1)
project.bit is (to fix the ideas) the output of the ISE-workflow, that
is a .bit file that when loaded into the fpga performs its inteded
configuration. Block RAM contents are included in it. So it is
conceivable to modify project.bit in such a way, that only the content
of the BRAMs change. This is what data2mem does (when called in the
abovementioned way)
2)
newdata.mem is a file in a certain format that provides the new data to
go into (a selected set of) the BRAMs. It is more or less a Verilog .mem
file, consisting of a sequence of whitespace separated elements, that
are either @hexnumber or hexnumber. For example
@0000 12 13 1A @000B 12345F @2FCD 23 24 345D ..
might be such a file (of course probably not a very useful one)
3)
final.bit is just the modified .bit file with the contents of the
selected BRAMs changed.
Use impact to transfer it to the fpga and the fpga should work as with
the original project.bit and the contents of the selected BRAMs changed.
4)
Now to the file bmmfile_bd.bmm. Of course you have noticed, that files
1) and 2) are not sufficient to generate 3). What is missing is a
description, how to shuffle the bits from 2) (newdata.mem) into 3)
(final.bit). This description is provided by the .bmm file.
In my case the very simple situation, analogous to the example in the
data2mem User Guide applied. I had 4 RAMB_16_9 which were addressed as a
32bit wide memory with an address range of 2K words. Address range in
words was 0x000 to 0x800 and therefore in bytes 0x000 to 0x1fff (this is
of course a trivial observation, but the numbers reappear below)
Pictorially
********** ********** ********* ***********
* * * * * * * *
* r3 * * r2 * * r1 * * r0 *
********** ********** ********* ***********
r3 contained the highest byte in every word, r0 the lowest. That is, the
bytes, say at byte-address 0, 1, 2, 3 go in r0, r1, r2, r3 at
word-address 0.
If your setup is similar, you can copy from the following explanations.
The file bmmfile_bd.bmm that I used was (actually its name was
cpu_ram_bd.bmm)
ADDRESS_SPACE cpu_ram RAMB16 [0x00000000:0x00001FFF]
BUS_BLOCK
main_mem_A/gldata_ram3 [31:24] LOC = X0Y1;
main_mem_A/gldata_ram2 [23:16] LOC = X1Y5;
main_mem_A/gldata_ram1 [15:8] LOC = X1Y2;
main_mem_A/gldata_ram0 [7:0] LOC = X0Y5;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
You see here in an obvious way the BRAMs called r3,r2,r1,r0 reappearing
with their full instance names. The equations LOC = X0Y1; and so on of
course give the physical location of the respective BRAM in the final
layout. How did I find these out? The answer (using the ISE workflow,
which I do) is: I added as a new source to the project the following
file cpu_ram.bmm:
ADDRESS_SPACE cpu_ram RAMB16 [0x0000:0x1fff]
BUS_BLOCK
main_mem_A/gldata_ram3 [31:24];
main_mem_A/gldata_ram2 [23:16];
main_mem_A/gldata_ram1 [15:8];
main_mem_A/gldata_ram0 [7:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
Now starting the usual flow *including generating the .bit file*, the
following happens: From the file cpu_ram.bmm *without LOC information*
the file cpu_ram_bd.bmm *with the correct LOC information for the design
synthesized* is generated. Generating the .bit file is mandatory, as
first at this stage the modified _bd.bmm file is generated (the
extension _bd is invariably appended).
I will not delve too much into the syntax of .bmm files and the possible
ways to specify RAM layouts. In the case above you will recognize the
address range, that my 4 RAMs provide collectively in bytes (0x0000 up
to 0x1fff) and you will recognize selectors behind the instance names,
that obviously convey the idea that byte (i+4*x) is in gldata_rami (i=0..3).
The concrete file newdata.mem which I used had the form:
//@00000000
12345678
EA080100
980B0100
00000000
//@00000010
00000000
00000000
00000000
00000000
//@00000020
...
....
//@00001ff0
00000000
00000000
00000000
00000000
There are a lot different ways to describe the same data using the
format conventions of a .mem file. But if I understand everything right,
the somewhat redundant form above is equivalent to the shortened one
@000000 12 34 56 78 EA 0A 01 00 ...
(please write a correction, if I am mistaken in that, as I am not
totally sure about it)
Hoping that these explanations will be somewhat useful to future users
of data2mem, I conclude with
Greetings
Jürgen
--
Jürgen Böhm www.aviduratas.de
"At a time when so many scholars in the world are calculating, is it not
desirable that some, who can, dream ?" R. Thom
Article: 129909For those of you interested in research on the development of FPGA CAD and architecture, I am pleased to announce the release of new version of VPR, Version 5.0 Beta. This is a CAD tool suite targeting hypothetical FPGA architectures that enables both FPGA architecture and CAD exploration research. Its primary functionality is to provide packing (clustering), placement, routing and timing analysis for FPGA architectures described by an architecture description file. Building on the widely-used VPR 4.30, VPR 5.0 adds three important new features: 1. Single-Driver Routing Architecture (also known as Direct-Drive or Unidirectional routing architectures) now commonly used in major commercial FPGAs. 2. Heterogeneous logic blocks - the ability to describe different hard blocks, in addition to the regular soft logic. A new form of architecture description file permits this. 3. A wide range of transistor-optimized design files, spanning architecture, different area-delay tradeoffs, and IC processes down to 22nm, based on the Arizona PTM process models. For each logical architecture, we provide different electrical designs modeling the different IC processes *and* different transistor-sizing goals with respect to the importance of area and delay. In addition, in an attempt to maintain VPR's legendary software quality, we include regression tests that allow the developer the ability to test changes for correctness and quality. Also, we are providing an open source front-end CAD flow from Verilog to the T-Vpack input step. It begins with ODIN (for Verilog parsing and elaboration), passes through a modified version of Berkeley's ABC logic synthesis (thanks to Alan Mishchenko for support of ABC) that permits heterogenous structures to pass through, unhurt. Download Location: http://www.eecg.utoronto.ca/vpr The license for T-VPACK and VPR is the same as that granted previously: non-commercial, not-for-profit use (see the download page for details). The license of the front-end ODIN CAD flow is open source. As this is a Beta release, we are interested to receive feedback and bug reports. Please send those to vpr@eecg.utoronto.ca. We intend to produce a non-Beta release in the near future, incorporating feedback and problem reports. We also hope to engage in longer-range improvements to this software and are interested in suggestions on that front. CREDITS: In addition to the people listed above, this new release is the result of many people's work, including the original author, Vaughn Betz, who set a very high standard of quality that is hard to meet. Sandy Marquardt wrote the original timing-driving packing and placement. Andy Ye created the first version of the single-driver routing, which Mark Fang improved. Danny Paladino's research influenced the architecture description work incorporated here. Russ Tessier helped begin this project when he was visiting Toronto, and Mark Fang and Andrew Ling contributed to that early work. Ted Campbell was instrumental in the new heterogeneous block and routing architecture work. Ian Kuon's research and efforts contributed the new architecture files describing a wide range of architectures, in different processes and optimized for different target area and performance. Jason Luu and Peter Jamieson were key developers instrumental in the development and release of this version of the software. Jonathan Rose -------------------------------------- Jonathan Rose, Professor and Chair The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto 10 King's College Rd, Toronto, Ontario CANADA M5S 3G4 --------------------------------------Article: 129910
Tommy wrote:
>> Virtex 5's LUT6 are a strict subset of the ALM (modulo the SRL32
>> part),
>> but on paper, the ALM is much more powerful and flexible. In the real
>> world everything depends on what the design software does with them.
Quartus seems to use them rationally.
sdf wrote:
> Another question is, when it will be possible to program FPGA at low-
> level, without synthesis and fitting, just like low-level coders
> downgrading to x86 assembler in past..
Long past, and the analogy is weak since
assembly language was once standard practice
and it is still supported with tools.
I suppose I could make a netlist of LUTs and flops
instead of vhdl synthesis, but I see no way to
do manual place+route or static timing for fpgas.
> I believe, there're some people who eventually wish to try this, if it
> will be possible.
I've never met such a person.
-- Mike Treseler
Article: 129911Fei Liu wrote: > Hello, > > Not knowing better, I purchased a couple of these chips and now > realize they are 'not simulation ready'. Is there a way for me to use > these chips through breadboard or wiring? Or they are only supposed to > be part of a PCB board? In which case, can I order PCB boards using > chips? How do I do it? > > Also it seems to me it's way too expensive to build special purpose > IC device such as a door bell etc with fpga boards. FPGA boards are > general purpose device, like computers in a sense. At this end of the scale, you could also look at CPLD Boards. CPLDs give similar tool flows to FPGA, and learning, but simpler devices and lower cost eval PCBs. Altera have DK-MAXII-1270N Atmel have ATF15XX-DK3, includes ZIF socket & ISP cable, Lattice have LCMXO256C-S-EV Xilinx have Coolrunner II HW-CRII-SK-G, and optional HW-CRII-PM-ACC-G If you want to learn FPGA as well, then the Altera/Xilinx flow is probably preferable, as the same tools can target either CPLD/FPGA device family. Xilinx CPLD board looks the cheapest. -jgArticle: 129912
rponsard@gmail.com <rponsard@gmail.com> wrote: >hi groups >I notice that www.opencores.org is down ... the very moment i need jop >core... >does anybody know if there is a mirror available somewhere ? Still down.. Anyone knows what's going on..?Article: 129913
I am trying to contact Jeung Joon Lee to ask him about his SDRAM IP on his web site - http://www.cmosexod.com/ All three emails I found for him bounce. jlee@cmosexod.com cmosexod@ix.netcom.com joon.lee@quantum.com Does anyone on this list have a current email address for him? GlennArticle: 129914
Hi all, the following strange thing with Virtex - on the input I have base 24MHz, DCM generates 32MHz internally, and on one of the outputs should have 8MHz (32/4). It is a previosly designed product, so it sohud work fine, but unfortunately it makes these problems. In several cases, DCM stop work and on the output I have stable 6MHz ( base 24MHz/4). Testing with different version of firmware and different frequencies reveal the same problem. Some of the chips switch between working and wrong condition as they want. Date code of chips is 0545, stepping grade A1. Thanks for any help or info for cure or similar problems? -- Message posted using http://www.talkaboutelectronicequipment.com/group/comp.arch.fpga/ More information at http://www.talkaboutelectronicequipment.com/faq.htmlArticle: 129915
Hi, to all i am new to this group which a great place to share and find the more discussions environment. so my question is on xilinx virtex series FPGA's 1. every virtex series is having maximum frequency where we can use in some of higher end applications,so virtex, virtexII, virtex-E, and virtex-II Pro all serieses are having their Max frequency based on upgradations. So xilinx will design on what kind of basis to enhance the frequency in higer versions of these serieses and is that every logic( wether they are combinational or sequential type) having same kind of frequency(what Max frequency of FPGA is having).? May this question in easier one,...but if any one having a good answer...it will be a great thing. regards, Sreeni, Moog,IncArticle: 129916
On Mar 10, 5:22 am, jshrini.v...@gmail.com wrote: > Hi, > to all i am new to this group which a great place to share and find > the more discussions environment. > > so my question is on xilinx virtex series FPGA's > > 1. every virtex series is having maximum frequency where we can use in > some of higher end applications,so virtex, virtexII, virtex-E, and > virtex-II Pro all serieses are having their Max frequency based on > upgradations. So xilinx will design on what kind of basis to enhance > the frequency in higer versions of these serieses and is that every > logic( wether they are combinational or sequential type) having same > kind of frequency(what Max frequency of FPGA is having).? > > May this question in easier one,...but if any one having a good > answer...it will be a great thing. > > regards, > Sreeni, > Moog,Inc Speed enhancements in newer generation FPGA's come from 2 sources. The first is process enhancements (usually reduced geometry) which is something developed mostly by the fabrication partner and to some extent "tweaked" by Xilinx. Reduced geometry generally results in better speed as well as increased density. The second is architecture enhancements. These have additional impact on device speed that can be carried over to further process generations. The original Virtex series gained a great deal of speed in its routing for example over the previous generations of Xilinx FPGA which had passive routing connections. Virtex 5 has increased the LUT size to 6-inputs which can reduce logic levels in complex designs. Process enhancements generally affect all of the chip timing parameters, while architecture enhancements can affect only some timing parameters, or some more than others. For example increasing the LUT size doesn't generally affect the maximum toggle rate of the fabric flip-flops. Depending on what you do with the FPGA some architecture enhancements can make a tremendous difference in performance, for example the addition of DSP48 for signal-processing applications. These same enhancements may make no difference at all to other designs that implement a lot of random state-machines. I'm sure Austin can point out a number of other improvements over time in the Virtex series, as well as a sense of where more speed enhancements may come from in future generations. Regards, GaborArticle: 129917
"Gabor" <gabor@alacron.com> wrote in message news:ef6b6505-5146-450f-b6cf-b66c5f0cc70e@59g2000hsb.googlegroups.com... > Speed enhancements in newer generation FPGA's come from 2 sources. > The first is process enhancements (usually reduced geometry) which > is something developed mostly by the fabrication partner and to > some extent "tweaked" by Xilinx. Reduced geometry generally > results in better speed as well as increased density. > It is also possible to get process-enhancement driven performance increase without any physical design changes, such as geometry shrinks. When a vendor offers multiple speed-grades of the same part, as Xilinx do, all the parts are built the same and then sorted at test. As one gets better at making the parts it can be the case that enough are faster than the fastest part marketed to introduce a new faster version. This used to be a big thing a few years ago, but I suspect these days the variation is less because of tighter control over processes from the outset.Article: 129918
sky465nm@trline5.org wrote: > rponsard@gmail.com <rponsard@gmail.com> wrote: > >hi groups > >I notice that www.opencores.org is down ... the very moment i need jop > >core... > >does anybody know if there is a mirror available somewhere ? > Still down.. > Anyone knows what's going on..? Now online again. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 129919
Roger, Any problem: website, software, hardware. AustinArticle: 129920
Grubi, So, 24 MHz in, CLKFX is 32 MHz out (M=3, D=2), with a CLKDV out, with DIV=3? The CLKFB should be connected to CLK0 (for least jitter on the feedback). What is the source of the 24 MHz? Has it changed from the last build? Then the CLKFX runs for awhile,and than stops working, that is usually excessive jitter on the input, or a missing pulse on the input (a glitch). Have you looked at the status bits (CLKIN_STOPPED, LOCKED, etc)? AustinArticle: 129921
Antti, Did you that Xilinx is the youngest (newest) successful PLD company? All of the other successful PLD companies are older than we are. I also like to comment that Xilinx is the "biggest little company I have ever worked for." The meaning of this statement is that although we have more than 3,000 employees now, around the world, everyone acts in a way that benefits the whole (which is more like a small company). If you read in FPGA Journal the interview with Wim and Moshe, you will see what I mean. By the way, having talked with Wim many times, and having met and talked with Moshe, we are very fortunate that Xilinx has (had) such great management. I wish SiliconBlue good luck, it is a really tough business (as evidenced by all the failures of PLD companies in the last 24 years). AustinArticle: 129922
On 2$B7n(B27$BF|(B, $B>e8a(B9$B;~(B53$BJ,(B, John Williams <jwilli...@itee.uq.edu.au> wrote:
> Hi Huang,
>
> grant0920 wrote:
> > I have successfully integrated the ICAP driver to our Linux on the PPC
> > on the ML310 board. But now I had a problem about the ICAP driver. My
> > combinational circuits, such as the very simple adder design and the
> > subtractor design, can successfully be partially reconfigured by the
> > ICAP driver, but the sequential circuit cannot be. Are there any
> > things that I have to consider, such the hardware design? Thanks!
>
> The impact programming tool can download partial bitstreams just like
> the ICAP driver. So, test your partials there. If they work in impact,
> but not through ICAP + Linux driver, then it's pretty strange.
>
> It's most likely an issue with the bitstreams themselves - double check
> how you generated them, and try the partial-reconfig mailing list or
> other sources of help on the subject (this newsgroup!).
>
> Since you have problems with sequential but not combinational circuits,
> my first guess would be a reset or clocking problem in your crossing
> from fixed -> reconfigurable partitions.
>
> Regards,
>
> John
Dear John:
All my partial bittstreams can work in the impact tool. I am not
sure what are the reset or clock problems that you menetioned? Does it
mean that the HDLs of my hardware designs need to be remodified its
reset and clock signals? I followed the EAPR flow so I used a global
buffer to connect the clock signal for the PR design. The reset signal
is connected to the PR design through the busmacro. Is it right? Or
are there other rules that I have to consider? Or does the hwicap APIs
that are provied by Xilinx need to be corrected somewhere? Thanks!
Best Regards,
Hunag
Article: 129923Don't forget progress in characterization. Often you do not know exactly how fast all the pathes in your design are over all operating conditions. IBM stated up to 30% deviation from SPICE simulation to measured chip in some cases at the ISPD2001 conference. This is especially true for SOI circuits were switching speed depends on the signal history. Within the lifetime of a product the understanding of the device timing improves and tighter values can be published. Therefore you sometimes can sometimes improve the guaranteed performance of a design just by downloading a new speedfile. Also: Depending on your design style software improvements in the design tools can have a positive effect on timing. Kolja SulimmaArticle: 129924
On Mar 10, 7:49=A0am, austin <aus...@xilinx.com> wrote: > Antti, > > Did you that Xilinx is the youngest (newest) successful PLD company? > All of the other successful PLD companies are older than we are. > > I also like to comment that Xilinx is the "biggest little company I have > ever worked for." =A0The meaning of this statement is that although we > have more than 3,000 employees now, around the world, everyone acts in a > way that benefits the whole (which is more like a small company). =A0If > you read in FPGA Journal the interview with Wim and Moshe, you will see > what I mean. > > By the way, having talked with Wim many times, and having met and talked > =A0with Moshe, we are very fortunate that Xilinx has (had) such great > management. > > I wish SiliconBlue good luck, it is a really tough business (as > evidenced by all the failures of PLD companies in the last 24 years). > > Austin Austin - do you refute Antti's post without actually disagreeing? If you consider SiliconBlue to be a younger (newer) PLD company than Xilinx, the issue is just one of success. Antti's point seems to be that their tool development wouldn't be hampered by the legacy of any successful PLD company that's 20 years or more in age. I love Xilinx. And I often fight with arcane tools. It doesn't change the lure of the silicon and raw capabilities. I appreciate small company mentality, but there's only so much that can be done against the history of millions of lines of code. - John_H
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