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Hai jonathan, U have not given comments for my questions... regards, faza On Jun 5, 7:55=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Thu, 5 Jun 2008 14:25:33 +0100, "Symon" wrote: > >Ha, that reminds me of a DSP course some of us attended in the mid-eighti= es. > >The lecturer chap tried to convince us that DSP was the only way to make > >linear phase filters. Sadly for him, several of us knew how our colour > >tellys extracted the chrominace signal! > > Putting to one side for the moment the universal hazards of > appearing in public - undone fly-zips, remains of yesterday's > supper on the tie, iridescent facial pustules, and the like - > there are two obvious ways a trainer or lecturer can make > a complete idiot of themselves: > (1) simply getting something completely wrong - hard to > =A0 =A0 avoid in a training course of several days' duration, > =A0 =A0 human frailty being what it is; > (2) assuming that the audience/students/clients know > =A0 =A0 less than the trainer does. > > These days, my preferred response to (2) is simply to enjoy > the fact that whenever I deliver a class I learn a bunch > of interesting stuff from the students. =A0I hope they don't > mind too much, given that they're paying :-) =A0In any case, > a certain humility is in order; most of us know quite a > lot about some things, but embarrassingly little about > other things. =A0I reckon it'll be time to give up when I > find myself no longer willing to learn from students. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Article: 132701
On Jun 4, 4:45=A0pm, "Symon" <symon_bre...@hotmail.com> wrote: > http://www.edn.com/article/CA6566989.html I had a job offer from Xilinx Albuquerque last year. One of the positives touted was the company had never had a layoff. Sorry to see that is no longer true. Good company, products and people. Hopefully this is a one-time thing.Article: 132702
On Thu, 5 Jun 2008 08:51:55 -0700 (PDT), faza wrote: >U have not given comments for my questions... That's because you have me completely baffled. You tell us you need 2.5G samples/sec but you have a 250MHz clock frequency. I responded by pointing out that this implies ten samples per clock, which is something that seems to me to be completely obvious. You responded that you have one sample per clock. Consider this example: Someone says to me that they want advice on how to build a staircase. In particular, they want the staircase to rise by 30 metres, and to have exactly 15 steps. I point out that this would require each step to be 2 metres high, and the response comes back "Each step is to be 20cm high". How do I respond intelligently to that? I think I am entitled to my confusion. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 132703
rickman wrote: > There are just some posts that are better left without responses. I > think Frank's was one of those. I don't see what was wrong with my post, I just explained why big companies needs new people all the time. And Peter's comment is right: a company can't stop hire people, because if someone like Peter would leave the company, someone from accounting can't replace him. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 132704
"rickman" <gnuarm@gmail.com> wrote in message news:3253a340-9804-4fd5-b6d8-df9dd706ae86@c58g2000hsc.googlegroups.com... [snip] > Independant of the UI issues, a program really shouldn't crash when it > reads a data file... of any nature. Of course that is a theoretical > goal and can be difficult to achieve in practice. But certainly > crashing on startup without visible error messages is not a good thing > either. I had to start it from a DOS box to get anything useful from > it... maybe that is more of a Java issue... and don't get me started > complaining about Java. Does *anything* written in Java actually > work? > I suggest that any program for Windows Vista that uses Java should start with a check to see if Java is even installed, and if so, whether the version installed is suitable for what the program needs. My version of Vista came without Java, and the Microsoft version is no longer available. I installed the Sun version, but still have problems with getting all the programs that use Java to run correctly. http://www.java.com/en/Article: 132705
On Jun 5, 12:09 pm, Frank Buss <f...@frank-buss.de> wrote: > rickman wrote: > > There are just some posts that are better left without responses. I > > think Frank's was one of those. > > I don't see what was wrong with my post, I just explained why big companies > needs new people all the time. And Peter's comment is right: a company > can't stop hire people, because if someone like Peter would leave the > company, someone from accounting can't replace him. > > -- > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de I don't think there was anything "wrong" with your post. I just don't think that Peter's response was at all helpful to Xilinx and I don't know that it "needed" a response at all. You stated an observation. Xilinx has its reasons for what it did. Since none of us know what those reasons were, including Peter most likely, there is no point in trying to justify or condemn Xilinx for not meeting our expectations. I would rather condemn Xilinx for its marketing decisions if anything. They certainly don't meet my expectations there... ;^) But to your argument, I don't agree. It is very often that a company will simply put out a hiring freeze rather than a layoff, partly because it is much cheaper! Layoffs mean an immediate reduction in paychecks, but at the expense of several weeks of severance pay and potentially higher unemployment insurance rates. A hiring freeze costs next to nothing and does allow for filling positions that are the exception. Let's face it, this is not the government, they will do what makes the most sense to them including violating their own rules if needed. Although you can't replace Peter with someone from accounting (at least we can assume that) I am sure that Xilinx has any number of good engineers who *can* take over his duties. Yes, I expect there will be some loss of productivity in the company overall, but that is the goal, to reduce productivity (as little as possible) to bring expenses in line with expected revenue. If I had to guess, I would say that the layoffs were not in reaction to a bad quarter, but because of the darkening clouds on the horizon of coming quarters. A company can always ride out a single quarter or even a single year. It is the long term perspective that causes layoffs. Perhaps Xilinx senses a change of sea state... a new paradigm coming? RickArticle: 132706
Just forget about that example...pls tell how sampling frequency decides the Fclk in wat factor they are related and why? say for simple case: fc=3D5khz fs=3D8khz taps=3D16 fclk=3D? (considering my current design) pls clarify.. regards, faz On Jun 5, 9:04=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Thu, 5 Jun 2008 08:51:55 -0700 (PDT), faza wrote: > >U have not given comments for my questions... > > That's because you have me completely baffled. > > You tell us you need 2.5G samples/sec but you have a > 250MHz clock frequency. =A0I responded by pointing out > that this implies ten samples per clock, which is > something that seems to me to be completely obvious. =A0 > You responded that you have one sample per clock. > > Consider this example: =A0Someone says to me that > they want advice on how to build a staircase. > In particular, they want the staircase to > rise by 30 metres, and to have exactly 15 steps. > I point out that this would require each step > to be 2 metres high, and the response comes > back "Each step is to be 20cm high". > How do I respond intelligently to that? > > I think I am entitled to my confusion. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Article: 132707
On Jun 5, 9:14 am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Wed, 4 Jun 2008 12:44:03 -0700 (PDT), rickman <gnu...@gmail.com> > > Do you work in the NHS, or for one of their equipment suppliers? > All the CUI references (includinghttp://www.mscui.net/seem to be > associated with the health care sector. > I think what rickman was trying to remember was the 'Common User Access' or 'CUA' developed by IBM. http://en.wikipedia.org/wiki/Common_User_Access KJArticle: 132708
"Robert Miles" <robertmiles@bellsouthNOSPAM.net> wrote in message news:_tU1k.736$RY.138@bignews8.bellsouth.net... > > "rickman" <gnuarm@gmail.com> wrote in message > news:3253a340-9804-4fd5-b6d8-df9dd706ae86@c58g2000hsc.googlegroups.com... > [snip] >> Independant of the UI issues, a program really shouldn't crash when it >> reads a data file... of any nature. Of course that is a theoretical >> goal and can be difficult to achieve in practice. But certainly >> crashing on startup without visible error messages is not a good thing >> either. I had to start it from a DOS box to get anything useful from >> it... maybe that is more of a Java issue... and don't get me started >> complaining about Java. Does *anything* written in Java actually >> work? >> > I suggest that any program for Windows Vista that uses Java should > start with a check to see if Java is even installed, and if so, whether > the version installed is suitable for what the program needs. My version > of Vista came without Java, and the Microsoft version is no longer > available. I installed the Sun version, but still have problems with > getting > all the programs that use Java to run correctly. > > http://www.java.com/en/ > When getting the URL for that last message, I noticed that Sun now has a version of Java newer than the one I had before, and decided to install this update. The Google Toolbar program is offered at the same site, so I thought I'd let you know that if you're using the Windows Mail program that comes with Vista, you should avoid installing the Google Toolbar program unless you want to see what problems it causes in Windows Mail, although it often doesn't cause them immediately. Web sites that offer to let you do Google searches don't cause the same problems.Article: 132709
> If you are going to do multi-channel audio, Xilinx may have the > advantage that you can use the LUTs as 16x1 memory instead of > flipflops. If you want to process up to 16 channels, you can use luts > as temporary storage for filter results etc. The space savings can be > huge. For the FIR I will probably use some BRAM but I was looking into this the other day and I really like the tiny FIFOs you can make with the Xilinx parts. Very useful for me ! I can instantiate one FIFO per channel using very little slices and it greatly simplifies my data flow. And the SRLs are nice to make audio I²S encoders, too.Article: 132710
On Jun 5, 9:14 am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Wed, 4 Jun 2008 12:44:03 -0700 (PDT), rickman <gnu...@gmail.com> > > Do you work in the NHS, or for one of their equipment suppliers? > All the CUI references (includinghttp://www.mscui.net/seem to be > associated with the health care sector. > I think what rickman was trying to remember was the 'Common User Access' or 'CUA' developed by IBM. http://en.wikipedia.org/wiki/Common_User_Access KJArticle: 132711
hi folks You may have noticed that I've been struggling to explain some rather basic stuff about FIR filters to someone here. I've run out of puff, and wish to sign off by recommending some good books. Nowadays I do less DSP design than I used to. The small amount of theory I need comes straight out of my head, and the textbooks on my bookshelf are looking pretty elderly. So I need a bit of help in recommending some introductory reading. What are your favourite up-to-date texts or URLs on DSP and digital filtering that we could recommend to our friend Fazulu? Preferably something with an FPGA implementation bias rather than software. Courses too: Xilinx have a class on DSP implementation techniques; that might be helpful. One of my favourites was www.dspedia.com but that seems to be dead now. Any others? Thanks in advance for getting me off the hook :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 132712
On Jun 5, 12:53 pm, KJ <kkjenni...@sbcglobal.net> wrote: > On Jun 5, 9:14 am, Brian Drummond <brian_drumm...@btconnect.com> > wrote:> On Wed, 4 Jun 2008 12:44:03 -0700 (PDT), rickman <gnu...@gmail.com> > > > Do you work in the NHS, or for one of their equipment suppliers? > > All the CUI references (includinghttp://www.mscui.net/seemto be > > associated with the health care sector. > > I think what rickman was trying to remember was the 'Common User > Access' or 'CUA' developed by IBM. > > http://en.wikipedia.org/wiki/Common_User_Access > > KJ I had the initials right, but the name wrong. The wiki article you link to calls it... Windows Consistent User Interface standard (CUI), Notice the wiki note that CUA has never had significant impact on Unix terminal applications. That explains a lot of why people don't tend to migrate between Windows and *nix. I know that most open source programs that I have tried seemed to me to have a bizarre user interface. I know that I am more sensitive to this sort of thing than most people, but once I see something that works well, I really, really hate to go back to poor practices. For the most part any new program should try to emulate the UI of the other common programs out there, only altering features if it *really* has a positive impact.Article: 132713
Hi Parag, Aiken, thanks for your inputs. They are very helpful. Hi Parag, when i mean clock generator, i mean the EDK clock generator module which generates clocks on board the FPGA using DCMs, deriving clocks based on what the user wants. will look at ML505 and ML506 reference designs. thanks again ChrisArticle: 132714
The cost/benefit winner: Steven Smith's complete text on line: http://www.dspguide.com/. And in commode-friendly format at Amazon: http://www.amazon.com/Scientist-Engineers-Digital-Signal-Processing/dp/0966017633 I'm partial to Lyon's conversational style. I often wonder if my elderly grandmother, whose technical background seems to predate flint and stone, can grasp the essence simply by sleeping with this wonderful book under her pillow. http://www.amazon.com/Understanding-Digital-Signal-Processing-2nd/dp/0131089897 MATLAB, by The MathWorks: http://www.mathworks.com/. Very little related reading for DSP, but a necessary tool for exploration and understanding. For some specialized MATLAB hand holding: http://www.amazon.com/Digital-Signal-Processing-Bookware-Companion/dp/0495073113 Which works best with Proakis's: http://www.amazon.com/Digital-Signal-Processing-John-Proakis/dp/0131873741 ... and the companion self-study guide: http://www.amazon.com/Self-Study-Guide-Digial-Signal-Processing/dp/0131432397 Xilinx's SystemGenerator User Guide is also highly recommended reading, depending on how you plan to implement the design, of course. "Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message news:8n6g44151k7l4gpf0d3ugicepo6ki93fev@4ax.com... > hi folks > > You may have noticed that I've been struggling to explain > some rather basic stuff about FIR filters to someone here. > I've run out of puff, and wish to sign off by recommending > some good books. > > Nowadays I do less DSP design than I used to. The small > amount of theory I need comes straight out of my head, and > the textbooks on my bookshelf are looking pretty elderly. > So I need a bit of help in recommending some introductory > reading. What are your favourite up-to-date texts or URLs > on DSP and digital filtering that we could recommend to > our friend Fazulu? Preferably something with an FPGA > implementation bias rather than software. > > Courses too: Xilinx have a class on DSP implementation > techniques; that might be helpful. One of my favourites > was www.dspedia.com but that seems to be dead now. Any others? > > Thanks in advance for getting me off the hook :-) > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.bromley@MYCOMPANY.com > http://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Article: 132715
On Jun 5, 1:11 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > hi folks > > You may have noticed that I've been struggling to explain > some rather basic stuff about FIR filters to someone here. > I've run out of puff, and wish to sign off by recommending > some good books. > > Nowadays I do less DSP design than I used to. The small > amount of theory I need comes straight out of my head, and > the textbooks on my bookshelf are looking pretty elderly. > So I need a bit of help in recommending some introductory > reading. What are your favourite up-to-date texts or URLs > on DSP and digital filtering that we could recommend to > our friend Fazulu? Preferably something with an FPGA > implementation bias rather than software. > > Courses too: Xilinx have a class on DSP implementation > techniques; that might be helpful. One of my favourites > waswww.dspedia.combut that seems to be dead now. Any others? > > Thanks in advance for getting me off the hook :-) > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. The bible we use was published by Analog Devices as "Digital Signal Processing in VLSI" by Richard J. Higgins, but is is clearly not FPGA-centric. However it's a great reference for learning the algorithms. regards, GaborArticle: 132716
On Thu, 5 Jun 2008 09:42:36 -0700 (PDT), faza <fazulu.vlsi@gmail.com> wrote: >Just forget about that example...pls tell how sampling frequency >decides the Fclk in wat factor they are related and why? sheesh... just *think about it* for five minutes... PROBLEM STATEMENT ~~~~~~~~~~~~~~~~~~ Every time the FPGA's clock ticks, it can do something. Once per sample, you get a new input data item for your filter and you need to spit out a new result from the output of your filter. It isn't as easy as this if you are doing interpolation or decimation, but let's not worry about that extra complication right now. So... POSSIBLE OUTCOMES ~~~~~~~~~~~~~~~~~ If you can deal with one input data item on each clock tick - the obvious, simple, common case - then you need to run the clock at exactly Fsample. If you can deal with N input data items on each clock tick, then you can run the clock at Fsample/N. In practice that's likely to be quite difficult, but it is definitely possible if you have some way to gather up N input samples and deliver them to the FPGA in a single hit. If you choose to do the processing a little bit at a time, and as a result you need M clock ticks to deal with each data sample, then you need to run the clock at M x Fsample. This might allow you to get away with fewer multipliers than filter taps, or perhaps use bit-serial arithmetic, or some other resource-saving tricks. Obviously, if Fsample is rather slow (as it would be for audio) and Fclk can be much higher, then this is likely to be the right way to proceed - use fewer multipliers, and do each filter sample over several clock cycles. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ What parts of that are difficult, or non-obvious? ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Oh, and by the way... > say for simple case: > fc=5khz > fs=8khz > taps=16 > fclk=? (considering my current design) You can't build a low-pass filter with 5kHz cutoff and 8kHz sampling frequency, thanks to a little theorem from a bloke called Nyquist. This doesn't Bode well, does it? :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 132717
On Thu, 5 Jun 2008 12:36:12 -0500, "MikeWhy" wrote: [lots of bibliography] Wow, that was quick for such a comprehensive list. Thanks. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 132718
Hi, I am working with FPGAs and trying to take advantage of the parallelism that is available in them. My design is in Verilog HDL and my design is using a lot of resources in the FPGA - ~ 80 % of the available LABs (or LEs or ALE), ~50% of Interconnect and ~80% of available on-chip memory. Also I am required to run this design at very high clock rate - almost equal to on chip memory clock rate. With this high utilization, its becoming very difficult to meet high timing requirements !! So, my question is regarding Verilog HDL coding - Is there any recommended coding style which improves timing closure (or in other words makes it easier for the tools to meet timing ) ?? If yes, please point me to the right location. Thanks in advance. JeDiArticle: 132719
On 5 Jun, 16:39, austin <aus...@xilinx.com> wrote: > Gabor, > > I believe they have a new memory technology, where they can OTP the > device, and then even after that, they can reload a bitstream into SRAM. > > Thus, you may prototype by just downloading streams until it is correct, > and then do the OTP step to "freeze" that stream in place. > > This avoids the traditional OTP (fuse) problem of wasting parts until > you get it right. =A0It also allows you to test the parts before you ship > them (unlike fuse FPGAs). > > They have a number of ex-X employees working there. Perhaps they will take on some more, now that Xilinx is laying off staff. 8-) LeonArticle: 132720
Leon, Seriously, it is an opportunity for any company in the FPGA/PLD business (no joke here). If you are expert in FPGA design, test, verification, programming (anything), then there is not a lot of places where you could go that would use all of your skills. As long as they honor their agreement not to disclose proprietary or confidential information, then they are OK to go... It may seem odd, but we have employees who have gone to another FPGA company, and then come back. Sometimes more than once! Austin Leon wrote: > On 5 Jun, 16:39, austin <aus...@xilinx.com> wrote: >> Gabor, >> >> I believe they have a new memory technology, where they can OTP the >> device, and then even after that, they can reload a bitstream into SRAM. >> >> Thus, you may prototype by just downloading streams until it is correct, >> and then do the OTP step to "freeze" that stream in place. >> >> This avoids the traditional OTP (fuse) problem of wasting parts until >> you get it right. It also allows you to test the parts before you ship >> them (unlike fuse FPGAs). >> >> They have a number of ex-X employees working there. > > Perhaps they will take on some more, now that Xilinx is laying off > staff. 8-) > > LeonArticle: 132721
On Jun 5, 2:44 pm, austin <aus...@xilinx.com> wrote: > Leon, > > It may seem odd, but we have employees who have gone to another FPGA > company, and then come back. Sometimes more than once! That reminds me of the old Volvo commercial where the guy is talking to his neighbor about the new Volvo he bought. The neighbor says about his own car (some American Belchfire 2000 type thing), "I've bought 12 of them in the last 18 years! If they weren't so good, why would I buy so many?" RickArticle: 132722
On Jun 4, 2:31 pm, ghel...@gmail.com wrote: > On Jun 4, 11:14 am, paragon.j...@gmail.com wrote: > > > Does anybody know if it is possible to directly instantiate a Xilinx > > Fifo Generator asynchronous fifo in VHDL? I have a design that > > requires the use of them, and I think it would be easier to not to > > have to keep track of different coregen cores as opposed to just > > having it written into the VHDL. I've seen other xilinx cores that > > allow this (dds compiler, for instance) but the fifo generator user > > guide doesn't say anything about it. > > > Thanks. > > Yes, and it's pretty easy. > > Look at what coregen creates. You'll see a template with a bunch a > parameters added. > > I have been successful instantiating the template and modifying the > parameters myself, without the use of coregen. > > Good luck, > G. Have you done this for synthesizeable code? I'm interested in being able to synthesize the fifos. Thanks for your help.Article: 132723
PFC schrieb: > > [...] > Duhhhhhhhhh > I missed the fact that the "free" NIOS was not free, thanks for > pointing this out ! > How about some core developed by the free hardware community like OpenRISC? PhilippArticle: 132724
"PFC" <lists@peufeu.com> wrote in message news:op.ub9x8di9cigqcu@apollo13.peufeu.com... I have an escape route. If I include FireWire in the project (which now seems likely), then I can use the ARM7 cpu which is in the DICE FireWire chip. I would have to connect its bus to the FPGA, using lots of pins, but there are enough pins to do this. I think this is going to be the simplest way to pass the licensing minefield. ========== If you're going that route, the Atmel AP7 Cortex M3 has dual Ethernet MII/RMII MAC, USB 2.0 PHY, LCD/TFT, yada yada (all the makings of a WinCE device). I don't recall seeing 1394 in its feature list, however. $25 single quantity. No licensing of "core" issues, obviously. Development tools are open source GCC. Some applications benefit less from FPGA capabilities than other, more traditional solutions. Your project description can fit this slot.
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