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iCE65 Ultra-Low Power FPGAs wrote: > SiliconBlue Pioneers New FPGA Technology for Handheld, Ultra-Low Power > Applications > > Monday, SiliconBlue(tm) announced a revolutionary new class of > single-chip, ultra low-power FPGA devices that set a new industry > standard for price, power and space along with unprecedented ASIC-like > logic capacity for battery-powered, handheld consumer applications. > Manufactured on TSMC's 65nm LP (low-power) standard CMOS process, the > new single-chip iCE(tm) family of FPGAs incorporate the company's > proprietary NVCM (Non-Volatile Configuration Memory) technology, > eliminating external flash PROM costs while making it easy-to-use. > > For more information, please visit www.siliconbluetech.com > > Press Release: http://www.siliconbluetech.com/docs/press/news060208.htm > > Brochure: http://www.siliconbluetech.com/media/iCE65Brochure.pdf > > iCE for Handhelds: http://www.siliconbluetech.com/ice_handhelds.html > > iCE Die Products: http://www.siliconbluetech.com/ice_vendors.html > > iCECUBE Design Software: http://www.siliconbluetech.com/designtools.html > > iCEman65 Evaluation Kit: > http://www.siliconbluetech.com/iCEman65/index.html Price of the iCEman65 Evaluation Kit ( & SW?) Errata sheet for the E.S. silicon ? Schedule for final silicon and production release ? Device Programming times ? ( Special programmer needed ? ) Device programming yields ? -jgArticle: 132751
(top-posting... muahahahahah) Thanks for, umm... joining the conversation? I wonder if mr. sales -AT- siliconblue.com (?) even knew there was a discussion here about them. Perhaps there could have been comments about how many customers have received the iCEman65 eval kits or when devices might be available to people like those who frequent this newsgroup. - John_H iCE65 Ultra-Low Power FPGAs wrote: > SiliconBlue Pioneers New FPGA Technology for Handheld, Ultra-Low Power > Applications > > Monday, SiliconBlue(tm) announced a revolutionary new class of > single-chip, ultra low-power FPGA devices that set a new industry > standard for price, power and space along with unprecedented ASIC-like > logic capacity for battery-powered, handheld consumer applications. > Manufactured on TSMC's 65nm LP (low-power) standard CMOS process, the > new single-chip iCE(tm) family of FPGAs incorporate the company's > proprietary NVCM (Non-Volatile Configuration Memory) technology, > eliminating external flash PROM costs while making it easy-to-use. > > For more information, please visit www.siliconbluetech.com > > Press Release: http://www.siliconbluetech.com/docs/press/news060208.htm > > Brochure: http://www.siliconbluetech.com/media/iCE65Brochure.pdf > > iCE for Handhelds: http://www.siliconbluetech.com/ice_handhelds.html > > iCE Die Products: http://www.siliconbluetech.com/ice_vendors.html > > iCECUBE Design Software: http://www.siliconbluetech.com/designtools.html > > iCEman65 Evaluation Kit: > http://www.siliconbluetech.com/iCEman65/index.htmlArticle: 132752
> This is also an area where Microsoft have completely lost the plot. > Since Windows 95 every major release of Windows has been accompanied > by a new interface. Applications are even worse - I don't know > how many style of toolbar have been played with over the last 15 > years. Microsoft always make great play of the new interface but > who exactly does it benefit? Users are forced to learn new interfaces > every upgrade and application developers are forced to 'upgrade' > their programs with the new UI or risk being considered outdated. > > The only people I can see benefiting are Microsoft themseleves (it > provides a very obvious reason to upgrade, even if it does lack > clear benefits) and hardware manufacturers (the upgrade needs newer > faster hardware). For all the talk of enhancing the user's experience > it seems obvious to me that MS don't give a shit about users. All > that matters is ensuring that the revenue keeps coming in from > repeated meaningless upgrades. > An excellent example of this is Office 2007. The UI for all the major applications have been changed completely with Ribbon bars, etc. It takes ages to work out where on earth really simple things are and they are now buried in (even more) obscure locations. Microsoft's advertising will have you believe "easy" but I disagree. AndrewArticle: 132753
rickman wrote: > On Jun 5, 9:14 am, Brian Drummond <brian_drumm...@btconnect.com> > wrote: >> On Wed, 4 Jun 2008 12:44:03 -0700 (PDT), rickman <gnu...@gmail.com> >> wrote: <snip> >>> I spent about 5 minutes working with this program before I gave up. >>> My reason is not the problem posted below, but because of the user >>> interface decisions made. I don't know why every new program has to >>> reinvent something about the user interface. There is a standard call >>> Common User Interface (CUI) that is even documented by Microsoft, >>> IIRC. >> Do you work in the NHS, or for one of their equipment suppliers? >> All the CUI references (includinghttp://www.mscui.net/seem to be >> associated with the health care sector. > > I have no idea what you are talking about... I am an electronic > design engineer and have never worked in the health care sector. What > exactly is NHS? Is that a government agency or a company? BTW, I > typoed above "call" should have been "called". CUI is a windows > standard as far as I know. I guess maybe it is more general, but I > have only heard the term used in the context of Windows. > I'm guessing (from your time zone) that you're in the USA. The "NHS" is the British "National Health Service". To people from the UK, "medical", "health care", and "NHS" are synonymous - the private health care is a very small minority there (mostly for people who want to pay for comfier beds and better food, or vanity surgery).Article: 132754
Dave Pollum wrote; > Digilent (www.digilentinc.com) makes the Xilinx FPGA starter boards, > and they have low-cost JTAG programming cables that work with Xilinx's > iMPACT. Digilent's parallel cable works, because it's a clone of the Xilinx Parallel Cable III. Digilent's USB cable does NOT work with Impact, ChipScope, etc.Article: 132755
"MikeWhy" <boat042-nospam@yahoo.com> writes: > I'm partial to Lyon's conversational style. I often wonder if my > elderly grandmother, whose technical background seems to predate flint > and stone, can grasp the essence simply by sleeping with this > wonderful book under her > pillow. http://www.amazon.com/Understanding-Digital-Signal-Processing-2nd/dp/0131089897 Seconded, I'm always reclaiming my copy from colleagues! And, for later on, he edited "Streamlining Digital Signal Processing", which is full of practical nuggets. http://www.amazon.com/Streamlining-Digital-Signal-Processing-Guidebook/dp/0470131578 And lurk of news:comp.dsp ! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 132756
Eric Smith <eric@brouhaha.com> wrote: > Dave Pollum wrote; > > Digilent (www.digilentinc.com) makes the Xilinx FPGA starter boards, > > and they have low-cost JTAG programming cables that work with Xilinx's > > iMPACT. > Digilent's parallel cable works, because it's a clone of the Xilinx > Parallel Cable III. > Digilent's USB cable does NOT work with Impact, ChipScope, etc. It's a pity, that Xilinx doesn't open their JTAG Api. Many FPGA boards have a USB Chip like the FT2232 or FX2 to do data communication. JTAG protocoll could easily be handled by them too. But to use Impact and or Chipscope, you have to provide an extra JTAG input for a XILINX-known cable adapter. Silly! -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 132757
In comp.arch.fpga, Thomas Stanka <usenet_nospam_valid@stanka-web.de> wrote: > On 4 Jun., 23:16, Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid> wrote: > >> This works in both pre- and post-synthesis simulation and also in real >> hardware. There is now an 8-bit comparator found for the compare line >> and no more warning about constant values. >> >> So my question is: Is there a problem with comparing and updating a >> value in the same state (clock)? > > No as a general problem. The code shown is IMHO synthesisable. OK, thanks. This is what I believed as well but started doubting after this experience. I use the single bit compare and update in a number of places and have not had problems with those. There should not be a fundamental problem between single-bit and multi- bit compare operations. > Only strange thing I see is lastval beeing updatet again at the > falling edge of clock, but the code shown here should work right. Sorry about that, that was a mistake in the example, the update should have been inside the "if rising_edge(clock) then". > However I would change this code in case of trouble, as this code > might easily mask problems resulting from other parts of the design > (eg. if you have a module where clk and data change their order in > timing). > > It might be also possible, that Xst struggles with this code even if > it the overall design is correct. > Try if other tools behave well with this code. At the moment I only have access to Xst for synthesis, so I can't try that. I have now split up the compare and update in several states and this has solved the problem. As the performance of this statemachine is not critical, I will leave it like that. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)Article: 132758
> On Jun 5, 11:47 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > >> I can think of a few obvious reasons why Xilinx would fire and hire >> at the same time. One, they probably cleared-out some of the middle >> management fluff that comes with a company of Xilinx's size. This >> would explain why they are still trying to hire for technical >> positions. Two, new hires tend to be cheaper than veteran employees >> are. Three, new hires, on AVERAGE, are more productive than more >> established employees. >> > I have never heard this before. Where did you get this info? I would > expect just the opposite. New hires are very unproductive for some > period of time while they adjust to the unique methods of a different > company and they learn all of the corporate culture. I am always > amazed at how much of the knowledge in a company is passed on by oral > tradition. If you shipped off all of the current employees and > replaced them with new, most companies would cease to exist. Maybe > that is a bit extreme, but I know of a company that had more than half > the employees with less than 1 year of tenure. It was a real cluster > ****. No one knew anything for sure and it always took way too long > to get anything done because it was always pulled in 10 different > directions from no one knowing what to expect from the others. I knew my statements would be contentious due to their brashness. In the real world, it's not that simple, and my comments really pertain to companies in the growth (R&D) phase. A company keeps its most experienced people around to teach and lead the new hires. That way, stuff gets done and ideas flow from the top directly to the bottom (no middle-men to muddle things up). Yes, a company will have reduced productivity for a couple of months, but will have an overall increased productivity in the long term. All at a lower cost, leading to increased profits. Doing this also allows for a change of "corporate culture", if required. After a few months, the new hires will be at the same place in current projects that the fired employees were. The difference is new hires, generally younger, have more time to put into the job and feel they have more to prove, and hence work harder. More established workers, generally, have families and a sense of entitlement. This means they tend to work less (and less efficiently), have other stuff to think about than their work problems, and aren't motivated to expand their knowledge base. In my work interning and consulting, I've found that I can get up to speed on the culture, tools, development process, etc. in less than three months. I also found that longer-term workers spent more time not working (talking, internet, ...) and were less likely to adopt new design processes or learn new technologies. Of course, there are exceptions to every rule, ala Peter and Austin, but I'm mainly writing about mid-level workers. > >> Four, new people bring >> new ideas; Xilinx already has the good ideas from the people they >> fired. > I don't agree with this either. Most "new" ideas are not brought with > people, they are created in response to the need of a situation. If > your statement were true, then all those people fired would be > bringing "new" ideas to the next companies they joined. > >> Five, firing can be used to eliminate the replication of ideas and >> services provided by a company's work force. Why does Austin need x >> employees who only know a strict subset of what he knows? He may >> have to do more work, but the company should save money in the end. >> > Yes, that is a valid point. Surely Austin can't do the work of the > people laid off around him, but the work that doesn't get done is > likely less of an impact on the company than the dollars saved... at > least in the short term. In the long run, this sort of thinking can > cause the loss of customers and lowered revenues. > > Rick > Lost revenues aren't necessarily bad. If it costs a company more money than it makes to get the revenue, lose the revenues and gain the net profit. All of this is the beauty of the capitalist system, it's too bad most CEOs and government leaders doesn't understand how to use it. If done right, in the end, the layoffs will be good for not only the company but for those fired. If forces both the company and those fired to re-evaluate their position in the market, resulting in better products and more motivated, possibly better trained employees. ---Matthew HicksArticle: 132759
So Jim wasn't too far off then.Article: 132760
control_state_v is being assigned to as a variable. It should be a signal.Article: 132761
Sorry for the non-digestive mistake made by me... as fs>=2fm and 0<fc<fs/2 If you can deal with one input data item on each clock tick - the obvious, simple, common case - then you need to run the clock at exactly Fsample. I am not using xilinx core generator FIR compiler where i need to specify sampling frequency and clock frequency while generation..But i have coded the design..I am expecting coefficients and input sample generated before hands with the parameters of the filter in such case why should i consider the sampling frequency which is the part of filter coefficients generation... pls clarify it... regards, faza MikeWhy wrote: > "John_H" <newsgroup@johnhandwork.com> wrote in message > news:f9cf11ec-b05f-48f6-b576-786738cbe6f1@k13g2000hse.googlegroups.com... > > It appears you *aren't* "pretty clear about ... > > I hesitate to say anything here. I agree with all you said, except in tone, > with which I can't disagree more. And while I cherish intellectual > curiosity, I also am in no position to even toy with volunteering to be an > online mentor. So, ... > > > If you had an idea of the scope and knew the underlying fundamentals, > > I'd encourage you. You are starting from SO FAR off from where you > > need to be that I'd encourage taking up a very different pursuit. > > Perhaps a summer of reading up on signal processing? > > > > Good luck in wherever life takes you, > > Addressed elsewhere in this NG today, I believe. Good luck, Faza.Article: 132762
On 2008-06-05 19:11:29 +0200, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> said: > hi folks > > You may have noticed that I've been struggling to explain > some rather basic stuff about FIR filters to someone here. > I've run out of puff, and wish to sign off by recommending > some good books. > > Nowadays I do less DSP design than I used to. The small > amount of theory I need comes straight out of my head, and > the textbooks on my bookshelf are looking pretty elderly. > So I need a bit of help in recommending some introductory > reading. What are your favourite up-to-date texts or URLs > on DSP and digital filtering that we could recommend to > our friend Fazulu? Preferably something with an FPGA > implementation bias rather than software. > > Courses too: Xilinx have a class on DSP implementation > techniques; that might be helpful. One of my favourites > was www.dspedia.com but that seems to be dead now. Any others? > > Thanks in advance for getting me off the hook :-) Here is another one. It's called "Digital Signal Processing with Field Programmable Gate Arrays". Guess about the content :) I found the link at the Page of Ray Andraka. http://www.amazon.com/gp/product/3540726128/ref=cm_cr_pr_product_top -- Regards, Maik H. insert_my_first_name_here@elektronensturm.deArticle: 132763
> Come to think of it, I would like such a device if paired with a > mid-size Spartan, something on the WebPack supported-device list. A > development platform with broad connectivity options using free and open > source tools sounds very, very appealing. Even the relatively large > S3ADSP 1800 can take advantage of offloading some functions to a real > MPU, filling some of the ground between it and the 3400, and avoiding > EDK licensing. That's pushing toward a LinuxCE with onboard FPGA. IOW, > fpga for the masses. Hmmm... Actually there is this nice board : http://dspfpga.com/index.php?option=com_content&task=view&id=23&Itemid=42&lang=en Still a bit expensive, though (about €450 with the 1600E and the CPU)Article: 132764
Uwe Bonnes wrote: > Eric Smith <eric@brouhaha.com> wrote: > > >>Dave Pollum wrote; >> >>>Digilent (www.digilentinc.com) makes the Xilinx FPGA starter boards, >>>and they have low-cost JTAG programming cables that work with Xilinx's >>>iMPACT. > > >>Digilent's parallel cable works, because it's a clone of the Xilinx >>Parallel Cable III. > > >>Digilent's USB cable does NOT work with Impact, ChipScope, etc. > > > It's a pity, that Xilinx doesn't open their JTAG Api. Many FPGA boards have > a USB Chip like the FT2232 or FX2 to do data communication. JTAG protocoll > could easily be handled by them too. But to use Impact and or Chipscope, you > have to provide an extra JTAG input for a XILINX-known cable adapter. > > Silly! Weren't there rumblings from within the depths of Xilinx about making that portion of the tool chain open-source ?. Makes sense, given the very wide range of programming combinations that exist, and in many cases Xilinx is NOT the only device. Is the person handling that still there ? -jgArticle: 132765
In comp.arch.fpga, RCIngham <robert.ingham@gmail.com> wrote: > control_state_v is being assigned to as a variable. It should be a signal. > Why should that be a signal? control_state_v is my state variable and is declared (not visible in the fragments) and used only in the clocked process. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)Article: 132766
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message news:8n6g44151k7l4gpf0d3ugicepo6ki93fev@4ax.com... > hi folks > > You may have noticed that I've been struggling to explain > some rather basic stuff about FIR filters to someone here. > I've run out of puff, and wish to sign off by recommending > some good books. > Hi Jonathan, There are some free ones listed here... http://www.dspguru.com/info/books/online.htm HTH., Syms. p.s. The books I learnt from include:- Crochiere and Rabiner 1983 Crochiere, R., and L. R. Rabiner. 1983. Multirate Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, Inc. Rabiner and Gold 1975 Rabiner, L. R., and B. Gold. 1975. Theory and Application of Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, Inc. Dunno if they're still in print though.Article: 132767
"krw" <krw@att.bizzzzzzzzzz> wrote in message news:MPG.22b23bc9da169c14989ce4@news.individual.net... > In article <4b62488d7f5738ca9575348d78d8@news.ks.uiuc.edu>, mdhicks2 > @uiuc.edu says... >> I can think of a few obvious reasons why Xilinx would fire and hire at >> the >> same time. One, they probably cleared-out some of the middle management >> fluff that comes with a company of Xilinx's size. This would explain why >> they are still trying to hire for technical positions. Two, new hires >> tend >> to be cheaper than veteran employees are. Three, new hires, on AVERAGE, >> are more productive than more established employees. Four, new people >> bring >> new ideas; Xilinx already has the good ideas from the people they fired. >> Five, firing can be used to eliminate the replication of ideas and >> services >> provided by a company's work force. Why does Austin need x employees who >> only know a strict subset of what he knows? He may have to do more work, >> but the company should save money in the end. > > Three, four, and five are the most repulsive *excuses* for a layoff > I have ever heard! ...and two is close. > > -- > Keith ...and even 'one' is repulsive, especially if it was posted by a student with time in the workplace. However, I'm sure Matthew is sharing his vast experience of layoffs in industry from his .edu email address. Otherwise, IMO, he'd be a complete dick for publicly kicking 250 folks going through some temporary bad luck. Syms.Article: 132768
"Symon" <symon_brewer@hotmail.com> wrote in message news:g2b858$re5$1@aioe.org... > with time in the workplace. I meant 'without'.Article: 132769
On Jun 2, 2:58 pm, timinganalyzer <timinganaly...@gmail.com> wrote: > There are 3 editions planned. The Free Edition(FE), the Standard > Edition(SE), > and the Professional Edition(PE). > > You can download the Free Edition now and read all about the > TimingAnalyzer at: > > www.timing-diagrams.com > > Comments and feedback are welcome at > > supp...@timing-diagrams.com Very, very interesting. Thanks Bye JackArticle: 132770
Hey, Have a look at www.mvd-fpga.com they have IP cores which will allow you to use the ethernet interfaces very easilly. Regards, Pat "AchatesAVC" <AchatesAVC@gmail.com> a écrit dans le message de news:93a5add5-3221-49e4-83d1-b27cee18a6d2@59g2000hsb.googlegroups.com... > First of all let me apologize for any thing of things I"m ignorant > about here. Up until very recenty my programming experience was > limited to higher level programming language: Python, PHP, Perl, hell > at this point I'd consider C high level. > > Anyway. > > I'm trying to use a Xilinx XUPV2P board to send data over ethernet. > The board uses the intel LXT972alc to control the PHY and provide a > MII interface. > > What I attempted to do was to build a valid packet, assert enable on > the pin labeled TX_ENABLE and feed that packet nibble by nibble to the > intel chip. > > The packet itself is UDP datagram using IP. I put in the preamble, > ethernet header, IP header, UDP header, data and checksum. I used the > Ethernet broadcast address. > > To try to test his out I thought I would plug my computer and the > board into a router. I have a C program that I wrote which picks up > and prints UDP packets sent to the appropriate port. I put the IP > address of my computer as when plugged into the router and tried to > send the packets there. However, no data seems to be getting through. > Furthermore, the absence of link up lights on both the router and the > board seem to indicate that the bord is not able to link to the > router. > > For reference I programmed this in Verilog (which I learned about 2 > weeks ago). > > If anyone could provide me with advice I would much appreciate. > > Thanks, > ---AchatesAVCArticle: 132771
On 5 Jun., 14:57, Gabor <ga...@alacron.com> wrote: > On Jun 5, 6:10 am, jid...@hotmail.com wrote: > > > I think the the problem lays on the TDO signal. The rising edge on TDO > > is abnormally slow and flat on the first pulse, here:http://img239.imageshack.us/my.php?image=jtagtdoprommh2.png. The TDO > > signal is connected directly from PROM to a Xilinx JTAG USB cable. > > Does somebody know why the signal is so flat? > > > Thanks, > > > JJ > > Any chance that the power was still coming up when you acquired the > trace on your 'scope? No, that wasnt the case. I found out something interesting. When I touch the TDO signal with the oscillscope probe, the ID check and programming works!!!! And I think the probe induced a small parallel capacitance to GND that made this work. I have never found anything on this on xilinx application notes. The question is now what capacitance value is the best? JJArticle: 132772
> No, that wasnt the case. > I found out something interesting. When I touch the TDO signal with > the oscillscope probe, the ID check and programming works!!!! And I > think the probe induced a small parallel capacitance to GND that made > this work. I have never found anything on this on xilinx application > notes. The question is now what capacitance value is the best? > > JJ I don't know if that's going to help but I literally spent days on making the JTAG work and : http://audio.peufeu.com/node/68 This was after going through 3 flat cables which actually ALL were defective, lol. The 4th cable is starting to die, too. Sometimes I have to fold it just the right way to make contact. I need to get some more connectors. There must be some curse on those. Also if you see funky waveforms on TDO this may be because when the chip's JTAG is idle, its output is tristated, but when it's active, its output is actively driving the cable. So, when it switches from active drive to tristate, it leaves only the pullup trying to fight with the cable capacitance. Hence you can see those waveforms on the scope. I don't think it's a problem though. Xilinx oh Xilinx please put schmitt triggers on the TCK input...Article: 132773
> ...and even 'one' is repulsive, especially if it was posted by a student > with time in the workplace. However, I'm sure Matthew is sharing his vast > experience of layoffs in industry from his .edu email address. Otherwise, > IMO, he'd be a complete dick for publicly kicking 250 folks going through > some temporary bad luck. > Syms. No I think he's a layoff lawyer.Article: 132774
> No, that wasnt the case. > I found out something interesting. When I touch the TDO signal with > the oscillscope probe, the ID check and programming works!!!! And I > think the probe induced a small parallel capacitance to GND that made > this work. I have never found anything on this on xilinx application > notes. The question is now what capacitance value is the best? Oh yeah I forgot : last time this happened to me it was because the pressure I exerted while probing did restore the contact in the faulty flat cable connector...
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