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<cpld.fpga.asic@gmail.com> wrote in message news:80fc5390-d10b-43a9-89c7-0c2770a996b5@k13g2000hse.googlegroups.com... > Automotive Temperature +100 deg C+ FPGA's -- who's parts are available > from Distributor stock? > > Am really interested in -40 to +125 deg C solutions that are > Automotive grade or Similar -- A quick trawl reveals Digikey have all these Altera parts in stock - I4 suffix - which are guaranteed -55C +125C parts EP2S60F1020I4 EP2S60F1020I4N EP2S60F484I4 EP2S60F672I4 EP2S90F1020I4 EP2S90F1508I4 probably a load more but can't be arsed to look. IckyArticle: 133001
Will you actually buy parts? As in tens of thousands? If so, contact your Xilinx FAE. We have both M grade (-55 to +125C), and automotive grade. The parts meet the applicable automotive and military standards. AustinArticle: 133002
MikeWhy wrote: > "Symon" <symon_brewer@hotmail.com> wrote in message > news:g2r74u$bbm$1@aioe.org... >> Spelling 'what' as 'wat' apparently "makes you look like a >> semi-literate boob" to save one entire keystroke, especially as you >> piss away the saving by using three question marks when one will do >> just fine. > > Ironically, it is precisely that which keeps me from writing him off > completely. There's an outside chance he's some jr. high school kid > feeling his way into the deep end. But, as you say, I'm still waiting > for the right questions. > Hi Mike, OK, that's cool, I see the point you are making. OTOH, (you knew this was coming!) I see you are relatively new here, and I'd be delighted to be told of someone who started off on this newsgroup as 'slightly irritating' and progressed as far as being 'not quite as irritating as you used to be'. In my sad middle aged cynicism, even the usenet nutters aren't what they used to be! Cheers, Syms.Article: 133003
On Jun 12, 1:14 pm, timinganalyzer <timinganaly...@gmail.com> wrote: > On Jun 11, 12:26 pm, rickman <gnu...@gmail.com> wrote: > > > > > On Jun 8, 10:00 pm, timinganalyzer <timinganaly...@gmail.com> wrote: > > > > Hello All, > > > > A new version beta 0.83 is now available. The following changes and > > > additions have occurred. > > > > * Improved Image Preview Display. > > > * Context sensitive popup menus to edit objects. > > > * Path set in image save dialog works. > > > * Metric paper sizes added to image preview. > > > * Lower case z, and x now work bus value combobox in toolbar. > > > * Move signals up and down commands now respect any space in > > > diagrams used for Text. > > > * Objects attached to any signal being deleted are deleted > > > automatically. > > > * Save file now includes some more error checking before saving > > > objects. > > > * Delays can not be added to DigitalClocks. > > > > You can download the Free Edition now and read all about the > > > TimingAnalyzer at: > > > >www.timing-diagrams.com > > > > ---------------------------------------------------------------------------------------------------------------------------------------- > > > > The TimingAnalyzer can be used to quickly and easily draw timing > > > diagrams. Signals, clocks, buses, delays, constraints, and states are > > > easily added from the GUI. > > > > It can also be used to quickly do a timing analysis and check for > > > timing faults. Minimum, typical, and worst case analysis can be > > > performed. Delays and constraints are easily specified and changed to > > > see if faster clocks or slower parts can be used without any timing > > > faults. > > > > There are 3 editions planned. The Free Edition(FE), a Standard > > > Edition(SE), and the Professional Edition(PE). > > > You asked for suggestions... I suggest that you spend some time > > working on the docs. I don't mean the full up, detailed manual. I > > mean come up with something that lets a beginner produce some simple > > diagrams quickly. Leave out the fancy features and just explain the > > basics of how this program is intended to be used. I think you feel > > the program is simple, but it is not. Maybe once you get the user > > over the initial hump, it is easy. But that initial hum is > > significant. > > > You have several ways of getting documentation or help. I could only > > find one that worked. In particular, you have a menu item in the > > program that opens a link in the web browser... to an empty page. I > > understand that this is a placeholder, but why have a placeholder that > > only frustrates the user? Grey out the menu item to anything that is > > not implemented or that does not work. No point in having users go > > down dead ends. > > > Rick > > The documentation in the application works. > > Help Menu -> User Manual > > It is very limited in scope but has the basics. There is also an step > by step example. > > I know the documentation page on the website is empty. I'm looking > for help, beta testing and things like documentation. Anyone > interested in helping, please let me know. > > I will try to improve the docs with each new release. > > Thanks, > Dan I know you are working on the docs and everything else. My point is that it is not a good practice to provide a link to an empty web page. Instead of doing that, you should gray out the link that points to it so people don't waste time looking where there is no help. That's all. I'm not trying to complain about things. You asked for suggestions and I am offering one. I think it is a pretty obvious principle to not provide menu items that aren't currently working. Wait until there is something to read, then give them a link to access. Good luck with it. RickArticle: 133004
On Mon, 19 May 2008 15:10:34 -0700 (PDT), Aiken <aikenpang@gmail.com> wrote: >input: Asynchronous, non-fix width, non-fix frequeny(but equal or >smaller than 30 Mhz), something like random fast signal coming in. >System clock is only 40MHz, What do you mean by non-fix width? Are you referring to a single signal line with a pulse width that is at least 33 ns wide (1/30MHz), but variable, or do you mean multiple signal lines, and you aren't sure how many signal lines? >What can I latch the "rising" edge of the input and synchronize it and >don't get into big trouble of Metastability? The standard approach to handling a single asyc signal is to pass it through a two stage synchronizer. Both FFs are clocked by the 40 MHz, both on the same edge. >Since the input freq is very near the System clock and Asynchronous >don't have a clock signal coming in. >is it possible that connecting the input signal directly to FF clock >then following with a negative clk edge FF then positive clk edge FF? >will it make any trouble and how to solve it? Your signal should go to the D of the first of 2 FFs described above. Clocking on alternate edges is not nearly as good as both FFs in the synchronizer clocked by the same edge. While it saves 1/2 a cycle of latency, it seems a silly optimization for a signal that is asynchronous. http://www.fpga-faq.org/FAQ_Pages/0017_Tell_me_about_metastables.htm Philip Freidin =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 133005
On Jun 12, 9:25 am, "Symon" <symon_bre...@hotmail.com> wrote: > Alan Nishioka wrote: > > On Jun 12, 8:14 am, ni <nbg2...@gmail.com> wrote: > >> I get the following error with chipscope analyzer whenever I do the > >> intialize chain. > >> ERROR: Socket Open Failed. localhost/127.0.0.1:50001 > >> localhost > >> java.net.ConnectException: Connection refused > >> ERROR: Failed to detect cable. > >> Try to open a specific cable from the 'JTAG Chain' menu > > >> IMPACT is able to initialize the chain successfully. > > > It looks like a network connection is failing. Are you sure you are > > not being blocked by your firewall? > > > Alan Nishioka > > Hi Alan, > > I don't think that's it.http://en.wikipedia.org/wiki/Localhost > > Did the OP try turning his computer off and on again? ;-) > > Cheers, Syms. Zone Alarm can block this sort of access and cause this sort of problem. It causes similar problems with the Xilinx simulator. Alan NishiokaArticle: 133006
"Symon" <symon_brewer@hotmail.com> wrote in message news:g2qofh$l0h$1@aioe.org... > "PFC" <lists@peufeu.com> wrote in message > news:op.uclqjtafcigqcu@apollo13.peufeu.com... >> >> Rant : Why is it that the very complicated things like FPGAs, work the >> first time, but the simple things, like JTAG, don't ? > > It's perhaps because some designers think that because JTAG is a 'slow' > bus compared to the hundreds of MHz on the other I/O pins, they don't do > proper SI design on the JTAG signals. They think it's a 'simple thing' to > just wire it up. If they do the simulation, it works first time, every > time. > HTH., Syms. You are absolutely correct, Symon. The edge rates of some buffers used for TCK can cause big problems if TCK is not treated like any other clock. TCK should be distributed and terminated like any other clock. The data signals (TDI/TDO, TMS) are much more forgiving because they're updated on one edge and read on the other of TCK, so setup/hold times are easily met for reasonable TCK frequencies without any special attention. However, get TCK wrong and it won't work at any frequency (I have found this out the hard way and have learned my lesson). Bob -- == NOTE: I automatically delete all Google Group posts due to uncontrolled SPAM ==Article: 133007
Philip Freidin wrote: > On Mon, 19 May 2008 15:10:34 -0700 (PDT), Aiken <aikenpang@gmail.com> wrote: >>Since the input freq is very near the System clock and Asynchronous >>don't have a clock signal coming in. >>is it possible that connecting the input signal directly to FF clock >>then following with a negative clk edge FF then positive clk edge FF? >>will it make any trouble and how to solve it? > > > Your signal should go to the D of the first of 2 FFs described above. > Clocking on alternate edges is not nearly as good as both FFs in the > synchronizer clocked by the same edge. While it saves 1/2 a cycle of > latency, it seems a silly optimization for a signal that is asynchronous. True, but dual edges might have other merit, if there is ever a chance the OP needs to catch a pulse under 33ns, and under 25ns too. Dual edges can resolve close to 12.5ns, and a Glitch catcher, could allow you to catch pulses even shorter, ( but only time defined to the nearest 12.5ns time slot) -jgArticle: 133008
>On May 19, 11:24 pm, Peter Alfke <al...@sbcglobal.net> wrote: > >My situation is that ....the "30MHz" doesn't mean it is 30MHz, it mean >that the min time different between two signal will be =( 1/30Mhz). In >income signal don't have a clock domain, it just "Happen". > Remember the Nyquist sampling criterion. If the minimum "pulse width" is 33ns (= 1/30MHz), that is roughly equivalent to a 15MHz maximum signal frequency, so 40MHz sampling is OK.Article: 133009
I do not have a zone alarm running on the system. Its a linux based system and has multiple installations of ISe (8.1,9.1) I will try cleaning it up and then try again. Thanks, D On Jun 13, 1:38 am, Alan Nishioka <a...@nishioka.com> wrote: > On Jun 12, 9:25 am, "Symon" <symon_bre...@hotmail.com> wrote: > > > > > Alan Nishioka wrote: > > > On Jun 12, 8:14 am, ni <nbg2...@gmail.com> wrote: > > >> I get the following error with chipscope analyzer whenever I do the > > >> intialize chain. > > >> ERROR: Socket Open Failed. localhost/127.0.0.1:50001 > > >> localhost > > >> java.net.ConnectException: Connection refused > > >> ERROR: Failed to detect cable. > > >> Try to open a specific cable from the 'JTAG Chain' menu > > > >> IMPACT is able to initialize the chain successfully. > > > > It looks like a network connection is failing. Are you sure you are > > > not being blocked by your firewall? > > > > Alan Nishioka > > > Hi Alan, > > > I don't think that's it.http://en.wikipedia.org/wiki/Localhost > > > Did the OP try turning his computer off and on again? ;-) > > > Cheers, Syms. > > Zone Alarm can block this sort of access and cause this sort of > problem. It causes similar problems with the Xilinx simulator. > > Alan NishiokaArticle: 133010
On Jun 12, 9:28 am, Henry Wong <he...@stuffedcow.net.nospam> wrote: > Tommy Thorn wrote: > > On Jun 11, 12:20 am, Henry Wong <he...@stuffedcow.net.nospam> wrote: > Indeed. I'd think that's a bug, one I hope won't get fixed. :) > > I filed a report thinking the GUI setting was broken, and got the > response that parallel compiles are now disabled. > > http://www.altera.com/b/quartus-ii-80.html > They've recently buried a line here suggesting you need the subscription > edition. Curious. I don't know why the fitter would report more than one processor used if it didn't. However I can't say I care much. The benefit was way too little to be measurable. The multi-core DSE is a much more important feature IMO. TommyArticle: 133011
Charles Xavier wrote: > If anyone has attempted to download anything in the 8GB range, you'll > find that well.. if you're missing enough parts of the file, the par2 > recovery can be a painful, painful process taking up to three hours in > some cases. > The XBOX 360 doesn't play x.264 and all the good movies are in x.264. > Converting from x.264 to h.264 could be done offboard on an FPGA I have a hard time believing that those are the "two most annoying problems on usenet". I've been using Usenet since 1984, and I've never personally encountered either problem. I've never tried to download an 8GB file from Usenet, and don't have any clue why anyone would want to do such a thing. There are much better ways to distributed 8GB files. But if I *did* want to download an 8GB file from Usenet, I can't imagine that waiting three hours for a reconstruction of missing pieces would really bother me that much. There's never been a single thing that I've needed from Usenet so urgently that it couldn't have waited three more hours. I watch a fair number of movies, but I've never had any problem with x.264. It sounds like you just need better player software. That has nothing to do with Usenet. Since it doesn't appear that there is any real problem here, it also doesn't appear that there is any need for an FPGA-based "solution".Article: 133012
I am running some xmp file provided by the manufacturer. The flow for generating bit file was smooth using 7.1 and 8.1 versions of ISE/XPS. I used to generate a netlist using xps. then run export to project navigator . run ngcbuild -i system.ngc system_all.ngc run the chipscope inserter on ngc file and then open the exported ise file which contained the ngc and the bmm files only. Now in 9.2 there is no way to export the file to projectnavigator. It exports all the vhd files and then the system.ucf also generates error indicating the hierarchy of the entities in ucf wile not present. Is there a way to switch to the old style of flow using 9.2? Some cores are not available in 8.1 and are only available in 9.2 and hence I need to use 9.2. I would really appreciate any help on this. -D so thatArticle: 133013
"faza" <fazulu.vlsi@gmail.com> wrote in message news:c800af32-4508-4576-812f-21f2050e033b@u6g2000prc.googlegroups.com... Hai, Can anyone explain how FIR filter implemented in real time application....Wat is the role of software supporting the hardware??? ======== I haven't audited the course contents, but I believe this might help: http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/6-341Fall-2005/CourseHome/index.htm Good luck.Article: 133014
I'm currently using GALs (16V8-18V8-22V10), but my current board requires 4 GALs and I would like to replace them with one CPLD which would also replace 4 other general ICs. I've never had the guts to try CPLD because I thought they were complicated to learn, hard to solder and most of all, impossible to programm without some $$$. Now I think different, but am unsure... I've choosen xilinx's XC95-36-72-108 to work with. I've read some examples of VHDL and I think it suits me. Non-SMD PLCC socket will make it easy to solder. Now, programming.. Is it true that all I need is a FREE Webpack software and a simple JTAG cable??? Will the Webpack only produce the fusemap or does it also contain the software to actually burn the chip? If the burn software is not contained in the Webpack- where do I get it from? Or that is where the $$$ comes in? Current version of Webpack is huge for my modem (2.25Gb) but maybe I'll get the version 7.1i - what do you guys think of that version with XC95-36-72-108 in mind? The last question (for now, sure) is: how are CPLDs programmed, with JTAG or something else? Everybody says that it uses JTAG, but I've found a PDF that says different: google for "XILINX PROGRAMMER QUALIFICATION SPECIFICATION" That PDF is using address bus(A0-A13), data bus(D0-D3), and several signals (TSTEN, PGMEN, VFYEN, TS0-TS3, AD_STB) to burn the XC9500 family.Article: 133015
> I've never had the guts to try CPLD because I thought > they were complicated to learn, hard to solder and > most of all, impossible to programm without some $$$. Welcome ;) I have never done CPLDs (I went straight from 74HC to FPGAs lol) but CPLDs are similar (simpler) and it isn't that hard if you have the hardware mind. When I say it's simple, I mean once you learn the tools, doing simple things is simple, solving a hard problem is still hard of course, but having infinite reprogrammability still makes it much easier than doing board respins ! It's interesting and you'll probably enjoy learning that stuff. > Now I think different, but am unsure... Go for it, the investment is small... > I've choosen xilinx's XC95-36-72-108 to work with. > > I've read some examples of VHDL and I think it suits me. Try Verilog and VHDL and choose according to your taste. > Non-SMD PLCC socket will make it easy to solder. > > Now, programming.. > > Is it true that all I need is a FREE Webpack software > and a simple JTAG cable??? Yes. The JTAG cable must be Xilinx-software-compatible though, don't use a JTAG cable for ARM or something. > Will the Webpack only produce the fusemap or does > it also contain the software to actually burn the chip? It contains all you need including the free simulator which will allow you to check your design before burning the chip. Before you build any hardware you should install the software, implement your design, and simulate it thoroughly. Always test your pin allocations BEFORE manufacturing the PCB ! The synthesis tool will tell you if you want to use an impossible pin mapping. > Current version of Webpack is huge for my modem (2.25Gb) Get it on DVD, or have a friend download it with DSL... > but maybe I'll get the version 7.1i - what do you guys > think of that version with XC95-36-72-108 in mind? Get the latest versions, less bugs, smoother user interface, etc. > The last question (for now, sure) is: > how are CPLDs programmed, with JTAG or something else? You are not going to want to take the chip out of the circuit to place it in a programmer every time you want to experiment so you are going to use in-circuit programming which means JTAG. > Everybody says that it uses JTAG, but I've found a PDF > that says different: google for > "XILINX PROGRAMMER QUALIFICATION SPECIFICATION" RTFM, lol, datasheet page 13 states : XC9500 devices are programmed in-system via a standard 4-pin JTAG protocol, as shown in Figure 13. In-system pro- gramming offers quick and efficient design iterations and eliminates package handling. The Xilinx development sys- tem provides the programming data sequence using a Xilinx download cable, a third-party JTAG development system, JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. All I/Os are 3-stated and pulled high by the IOB resistors during in-system programming. If a particular signal must remain Low during this time, then a pulldown resistor may be added to the pin. External Programming XC9500 devices can also be programmed by the Xilinx HW130 device programmer as well as third-party program- mers. This provides the added flexibility of using pre-pro- grammed devices during manufacturing, with an in-system programmable option for future enhancements. Use JTAG. But (as mentioned on this list a few days ago) be extremely cautious about the signal integrity of the TCK signal. Try to get an example reference design schematic and work from there.Article: 133016
aleksa wrote: > I'm currently using GALs (16V8-18V8-22V10), > but my current board requires 4 GALs and > I would like to replace them with one CPLD > which would also replace 4 other general ICs. > > I've never had the guts to try CPLD because I thought > they were complicated to learn, hard to solder and > most of all, impossible to programm without some $$$. What do you program the GALs with now ? - many pgmrs also pgm CPLDs (so you just need an adaptor) Or, you can use the JTAG ISP > Now I think different, but am unsure... > > I've choosen xilinx's XC95-36-72-108 to work with. There are also Atmel ATF150xASL series, in PLCC, but lower power than XC95xx. Note that PLCC is now somewhat trailing-edge, and newest families are TQFP only. > > I've read some examples of VHDL and I think it suits me. > Non-SMD PLCC socket will make it easy to solder. > > Now, programming.. > > Is it true that all I need is a FREE Webpack software > and a simple JTAG cable??? > > Will the Webpack only produce the fusemap or does > it also contain the software to actually burn the chip? > If the burn software is not contained in the Webpack- > where do I get it from? Or that is where the $$$ comes in? > > Current version of Webpack is huge for my modem (2.25Gb) > but maybe I'll get the version 7.1i - what do you guys > think of that version with XC95-36-72-108 in mind? This does show a problem with Tools. Those that bundle FPGA+CPLD, can get code bloat. Some vendors separate out the download, to allow CPLD users to avoid the pain of GB's. You could look at Atmel's WinCUPL - very fast compile of easy to use boolean equation entry - fine for spld merge tasks, and for most 32/64/128MC CPLDs. WinCUPL is a small 21MB (even smaller as command line model only), and you also need ATMELISP v6.4 @ 2MB to pgm the JED file (that model uses a parallel port SW JTAG ) http://www.atmel.com/dyn/products/tools.asp?family_id=653 WinCUPL also has a functional simulator, that can append JED test vectors, which allows Programmer verification of operation (in a ZIF style device programmer) Lattice and Xilinx also allow you to code in ABEL, which is easier to learn than VHDL. > > The last question (for now, sure) is: > how are CPLDs programmed, with JTAG or something else? > > Everybody says that it uses JTAG, Check the device pinouts - if they have TMS/TDI/TDO/TCK, then it is JTAG. -jgArticle: 133017
hi Alan, The machine has fedore core 2 on iot with a 2.6 kernel I am not using zonealarm or any firewall on my machine. I am still not able to fix it. -D Alan Nishioka wrote: > On Jun 12, 9:25 am, "Symon" <symon_bre...@hotmail.com> wrote: > > Alan Nishioka wrote: > > > On Jun 12, 8:14 am, ni <nbg2...@gmail.com> wrote: > > >> I get the following error with chipscope analyzer whenever I do the > > >> intialize chain. > > >> ERROR: Socket Open Failed. localhost/127.0.0.1:50001 > > >> localhost > > >> java.net.ConnectException: Connection refused > > >> ERROR: Failed to detect cable. > > >> Try to open a specific cable from the 'JTAG Chain' menu > > > > >> IMPACT is able to initialize the chain successfully. > > > > > It looks like a network connection is failing. Are you sure you are > > > not being blocked by your firewall? > > > > > Alan Nishioka > > > > Hi Alan, > > > > I don't think that's it.http://en.wikipedia.org/wiki/Localhost > > > > Did the OP try turning his computer off and on again? ;-) > > > > Cheers, Syms. > > Zone Alarm can block this sort of access and cause this sort of > problem. It causes similar problems with the Xilinx simulator. > > Alan NishiokaArticle: 133018
On Jun 13, 5:59 pm, ni <nbg2...@gmail.com> wrote: > I am running some xmp file provided by the manufacturer. The flow for > generating bit file was smooth using 7.1 and 8.1 versions of ISE/XPS. > I used to generate a netlist using xps. > then run export to project navigator . > run ngcbuild -i system.ngc system_all.ngc > run the chipscope inserter on ngc file and then open the exported ise > file which contained the ngc and the bmm files only. > > Now in 9.2 there is no way to export the file to projectnavigator. It > exports all the vhd files and then the system.ucf also generates error > indicating the hierarchy of the entities in ucf wile not present. > Is there a way to switch to the old style of flow using 9.2? > Some cores are not available in 8.1 and are only available in 9.2 and > hence I need to use 9.2. > > I would really appreciate any help on this. > > -D > so that Sorry guys its working now. I managed to figure out a way thanks, DArticle: 133019
Jim Granville <no.spam@designtools.maps.co.nz> wrote: > aleksa wrote: > > I'm currently using GALs (16V8-18V8-22V10), > > but my current board requires 4 GALs and > > I would like to replace them with one CPLD > > which would also replace 4 other general ICs. > > > > I've never had the guts to try CPLD because I thought > > they were complicated to learn, hard to solder and > > most of all, impossible to programm without some $$$. > What do you program the GALs with now ? - many pgmrs also > pgm CPLDs (so you just need an adaptor) > Or, you can use the JTAG ISP > > Now I think different, but am unsure... > > > > I've choosen xilinx's XC95-36-72-108 to work with. > There are also Atmel ATF150xASL series, in PLCC, but lower > power than XC95xx. > Note that PLCC is now somewhat trailing-edge, and newest > families are TQFP only. Note also that XC95xx has smaller logic operation capabilities against XC95xxXL or XC95xxXV and has higher prices. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 133020
Uwe Bonnes wrote: > Jim Granville <no.spam@designtools.maps.co.nz> wrote: > >>aleksa wrote: >>>I've choosen xilinx's XC95-36-72-108 to work with. > > >>There are also Atmel ATF150xASL series, in PLCC, but lower >>power than XC95xx. > > >>Note that PLCC is now somewhat trailing-edge, and newest >>families are TQFP only. > > > Note also that XC95xx has smaller logic operation capabilities against > XC95xxXL or XC95xxXV and has higher prices. The XC95xxXV (2.5V device) states this : Xilinx Data Sheet: [Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC9536XV devices with equivalent XC9536XL devices in all designs as soon as possible. Recommended replacements are pin compatible, however require a VCC change to 3.3V, and a recompile of the design file. In addition, there is no 1.8V I/O support.] - seems 2.5V never hit critcal mass, and thus is EOL.... As Uwe mentions, the XC95xxXL is MUCH cheaper than the XC95xx, BUT the XL is a 3.3V VccIO device. The ATF1502ASL is 5V Vcc capable - that may matter, when replacing SPLDs. Some of the new Lattice devices mention 5V tolerant IO (when VccIO=3.3V), but they are not in PLCC packages, and still need multiple Supplies. -jgArticle: 133021
faza wrote: > Can anyone explain how FIR filter implemented in real time I would vote for systolic array. > application....Wat is the role of software supporting the hardware??? Initialize the coefficients, and start everything going. -- glenArticle: 133022
Peter Alfke wrote: > On Jun 10, 7:25 pm, Alex Freed <al...@mirrow.com> wrote: (snip) >>If it takes 2 seconds to re-configure the FPGA and you do it 24 hours a >>day 365 days a year, in 100 years you will only reconfigure it >>1,576,800,000 times. Not "billions"! > Alex, Xilinx is a U.S. company, and your number is called 1.5 billion > over here. (Yes, I know Europeans call it a milliard.) > You also picked a very long config time. Typical FPGAs can be > configured much faster. Usually you want some of the time to actually use the device, not spend all the time as reconfiguration. I suppose I could imagine a system that rapidly switches between two or three configurations, though. Still, the time between reconfiguration should be longer than reconfiguration time. -- glenArticle: 133023
On Fri, 13 Jun 2008 18:31:51 +1200, Jim Granville <no.spam@designtools.maps.co.nz> wrote: >Philip Freidin wrote: >> On Mon, 19 May 2008 15:10:34 -0700 (PDT), Aiken <aikenpang@gmail.com> wrote: >>>Since the input freq is very near the System clock and Asynchronous >>>don't have a clock signal coming in. >>>is it possible that connecting the input signal directly to FF clock >>>then following with a negative clk edge FF then positive clk edge FF? >>>will it make any trouble and how to solve it? >> >> >> Your signal should go to the D of the first of 2 FFs described above. >> Clocking on alternate edges is not nearly as good as both FFs in the >> synchronizer clocked by the same edge. While it saves 1/2 a cycle of >> latency, it seems a silly optimization for a signal that is asynchronous. > >True, but dual edges might have other merit, if there is ever a chance >the OP needs to catch a pulse under 33ns, and under 25ns too. >Dual edges can resolve close to 12.5ns, and a Glitch catcher, could >allow you to catch pulses even shorter, >( but only time defined to the nearest 12.5ns time slot) > >-jg True, but your use of dual edge is not what the OP was suggesting. His proposed usage was as follows: a) Async signal into the CLK of a FF1, with let us assume D tied high b) Q of FF1 to D of FF2, with FF2 clocked by falling 40 MHz clock c) Q of FF2 to D of FF3, with FF3 clocked by rising 40 MHz clock d) Q of FF3 to the rest of his system. This will catch any pulse that meets min clock high of FF1 (assuming it is rising edge triggered). Not explained is the logic to clear FF1, and the dead time till that ripples through FF2 and FF3. The problem with the OPs circuit is that it contains the often proposed (and counter productive) arrangement of FF2 and FF3 on opposite clock edges. Since the signal is asynchronous, you must deal with the worst case latency through the synchronizer at the system level. At the component level you are trying to deal with moving an asynchronous domain signal to a synchronous domain. Assuming you are a competent and experienced designer, you have an understanding that this is important for system reliability, specifically to deal with metastability, but also to avoid race conditions, if the signal must be used in multiple destinations. With the current technology available in FPGAs, with min clock high times typically below 1 ns, his circuit could reliably catch pulses probably below 2 ns wide. This has nothing to do with the 40 MHz clock edges. Having caught and latched the rising async transition, the OP must now transfer it to the synchronous domain. Dual rising edge FFs is a recomended way to do it. A rising and a falling edge synchronizer is not recommended (or at least, not by me). What you describe is something quite different. Two separate synchronization paths, one clocked on the rising edge of the 40 MHz clock and one clocked by the falling edge. This gives two paths 12.5 ns out of phase, as you describe. But then you (typically) have to combine these signals into 1 signal, in (one would assume) the 40 MHz, at which point you are back to 25 ns resolution. To retain the 12.5 ns resolution (of questionable value given the asynchronous nature of the signal), you have to duplicate the down stream logic, or pass it around with a tag to indicate which synchronizer reported the signal first. Hardly something that is typically needed. Cheers, Philip Freidin. =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 133024
Modellpilot wrote: > The task of my student research project is to implement a digital VSB > modulator for analog TV in an FPGA. The design has three inputs: CVBS > (Color Video Baseband Signal) and audio1 (mono/left) as well as audio2 > (right) - digital sampled as YCbCr and I2S, respectively. The output > shall be "sampled" analog TV baseband (real-values) as input for > direct digital synthesis to TV RF. If the output is baseband, then you don't have any vestigial sideband. That doesn't happen until the RF modulator. http://en.wikipedia.org/wiki/Vestigial_sideband_modulation#Vestigial_sideband_.28VSB.29 -- glen
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