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Hai, I want to know which is the right way of implementing the hardware(industry standard)..I have referred various FIR implementations where they are mostly handling filter coefficients as integer(truncating from fixed or floating point using MATLAB) or binary.Is it difficult to handle and implement real(fraction) filter coefficients value directly in the hardware? for example: Filter coefficients: fixed point=3D0.081207275390625 or signed integer=3D 6945 or fixed point binary =3D0011011001000010 all the above are equivalent but belongs to different data type..Now i am confused which to select for implementation in my code.. Note: Fixed point representation is looking challenging for some synthesis tool as it not supported. Signed integer looks simple but less accurate Fixed point binary looks tedious.. Pls suggest.. regards, faza On Jun 17, 12:18=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > faza wrote: > > I am facing problem while synthesis of Fixed point data type.I cannot > > change the synthesis tool.Is there any method which can convert fixed > > point to integer =A0before hand and perform computation and convert back= > > to fixed point without affecting the precision.? > > I presume you mean fixed point with the binary point not > immediately to the right of the least significant bit, > sometimes called scaled fixed point. > > Adding such numbers with the same scale factor is the same > as adding integers. =A0Multiplying follows the rules you learned > in 3rd grade, the digits (bits) after the binary point of > the product is the sum of the bits after the binary points > of the to operands. =A0Multiply should give you a double length > product, select the appropriate bits. > > (snip) > > -- glenArticle: 133076
http://biz.yahoo.com/ap/080617/cadence_design_mentor_graphics.htmlArticle: 133077
Hi, Check out this thread, I think it contains some information that might be useful to you (not specific to the Cypress chip, but some good stuff on accessing USB sticks in general): http://groups.google.com/group/comp.arch.embedded/browse_thread/thread/42517517c02b9374 Regards, -- Hauke DArticle: 133078
Hi,
Unless you're using EDK for your design, iMPACT is the way to go. Here
is a tutorial that describes the steps you would use on a Spartan-3
demo board. I'm not familiar with the board you're using but, but the
same general steps usually apply. Start at the bottom of page 8
("Select the Configure Device (iMPACT) under the Generate Programming
File...").
http://ece.wpi.edu/~rjduck/Spartan%203%20decoder%20tutorial.pdf
Regards,
-- Hauke D
Article: 133079Hi, Whoops, apologies, I misread your original post, I guess you are using EDK :) It's been a while since I worked with EDK, but as long as you're generating .bit files you can use iMPACT to configure your FPGA with the same procedure. I forget if and how EDK provides functionality to configure the FPGA directly... Regards, -- Hauke DArticle: 133080
On Jun 15, 2:33 pm, "arko" <a...@winnet.com> wrote: > I've seen messages from regular posters saying that they > run Modelsim/XE Starter Edition in Linux. This evidently > works for the node-locked 'disk-id' based licenses. > > But if you have a full license, on a USB-dongle or other > physical key, will Modelsim/XE still work under WINE? Why bother? The native Linux version works so much better.Article: 133081
"ghelbig" <ghelbig@lycos.com> wrote in message news:8e662edc-f529-4fd2-930d-e4cfec5f1db6@l28g2000prd.googlegroups.com... > On Jun 15, 2:33 pm, "arko" <a...@winnet.com> wrote: >> I've seen messages from regular posters saying that they >> run Modelsim/XE Starter Edition in Linux. This evidently >> works for the node-locked 'disk-id' based licenses. >> >> But if you have a full license, on a USB-dongle or other >> physical key, will Modelsim/XE still work under WINE? > > Why bother? The native Linux version works so much better. > Hum.... Modelsim XE for Linux, keep on dreaming :-) I assume you mean Modelsim SE/LE/Questa which is N times more expensive! Hans www.ht-lab.comArticle: 133082
On Jun 17, 9:50 am, "HT-Lab" <han...@ht-lab.com> wrote: > "ghelbig" <ghel...@lycos.com> wrote in message > > news:8e662edc-f529-4fd2-930d-e4cfec5f1db6@l28g2000prd.googlegroups.com... > > > On Jun 15, 2:33 pm, "arko" <a...@winnet.com> wrote: > >> I've seen messages from regular posters saying that they > >> run Modelsim/XE Starter Edition in Linux. This evidently > >> works for the node-locked 'disk-id' based licenses. > > >> But if you have a full license, on a USB-dongle or other > >> physical key, will Modelsim/XE still work under WINE? > > > Why bother? The native Linux version works so much better. > > Hum.... Modelsim XE for Linux, keep on dreaming :-) > > I assume you mean Modelsim SE/LE/Questa which is N times more expensive! > > Hanswww.ht-lab.com Oops. I missed the "XE" part. More coffee, please.Article: 133083
"ghelbig" <ghelbig@lycos.com> wrote in message news:dbd758d9-3dfd-4879-bcbc-b9fbe39e7a2e@f24g2000prh.googlegroups.com... > On Jun 17, 9:50 am, "HT-Lab" <han...@ht-lab.com> wrote: >> "ghelbig" <ghel...@lycos.com> wrote in message >> >> news:8e662edc-f529-4fd2-930d-e4cfec5f1db6@l28g2000prd.googlegroups.com... >> >> > On Jun 15, 2:33 pm, "arko" <a...@winnet.com> wrote: >> >> I've seen messages from regular posters saying that they >> >> run Modelsim/XE Starter Edition in Linux. This evidently >> >> works for the node-locked 'disk-id' based licenses. >> >> >> But if you have a full license, on a USB-dongle or other >> >> physical key, will Modelsim/XE still work under WINE? >> >> > Why bother? The native Linux version works so much better. >> >> Hum.... Modelsim XE for Linux, keep on dreaming :-) >> >> I assume you mean Modelsim SE/LE/Questa which is N times more expensive! >> >> Hanswww.ht-lab.com > > Oops. I missed the "XE" part. More coffee, please. Milk no sugar for me please :-) Hans www.ht-lab.comArticle: 133084
"Dave" <dhschetz@gmail.com> wrote in message news:33883490-2aa7-440e-94ae-9316659ad854@t54g2000hsg.googlegroups.com... > http://biz.yahoo.com/ap/080617/cadence_design_mentor_graphics.html Worrying.....:-( Hans www.ht-lab.comArticle: 133085
I have 240 extra pieces of the Altera EP2C20F484C6N and we will not be able to use. Parts are new in original factory sealed packaging. Please let me know if you can use. I should be able to supply below factory direct pricing. Please let me know if you are interested in any quantity at all. Regards, Jon E. Hansen (949)864-7745Article: 133086
"Hauke D" <haukex@zero-g.net> wrote in message news:9da201d7-42a6-4739-8695-a7b14677b4f8@8g2000hse.googlegroups.com... > Hi, > > Whoops, apologies, I misread your original post, I guess you are using > EDK :) It's been a while since I worked with EDK, but as long as > you're generating .bit files you can use iMPACT to configure your FPGA > with the same procedure. I forget if and how EDK provides > functionality to configure the FPGA directly... EDK just front-ends the ISE tools with support for embedded development. It uses iMPACT to configure the target device, just as it continues to use XST and DataMem for their related functions.Article: 133087
In article <33883490-2aa7-440e-94ae-9316659ad854@t54g2000hsg.googlegroups.com>,
Dave <dhschetz@gmail.com> wrote:
>http://biz.yahoo.com/ap/080617/cadence_design_mentor_graphics.html
EDA monopoly! But in the long run I think the real competition is going to
be freeware.
--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 133088Consider using rateless codes, reed-solomon and ldpc based codes do provide erasure correction capabilities, however rateless codes such those based on LT class of codes (tornado etc) ,or more generally digital fountain codes, will have better performance due to their near linear decoding complexity as opposed to say reed-solomon erasure only decoding complexity which is around O(n^2) for naive implementations. Arash Partow __________________________________________________ Be one who knows what they don't know, Instead of being one who knows not what they don't know, Thinking they know everything about all things. http://www.partow.net On Jun 11, 11:50 pm, Charles Xavier <skelo...@gmail.com> wrote: > As you all know, downloading files from usenet leaves you with two > sets of files.. The rar files from what you're downloading and the > par2 files for incomplete file repair. > > If anyone has attempted to download anything in the 8GB range, you'll > find that well.. if you're missing enough parts of the file, the par2 > recovery can be a painful, painful process taking up to three hours in > some cases. > > I'm sick of it. > > So, here's the idea. Use a FPGA to do thereed-solomondecoding to > accelerate the PAR2 repair/recovery process. The system should utilize > a USB connection to pipe data directly from the disk to the FPGA that > will do the offboard processing of the data. The data transfer should > be controlled by an application on the computer. > > Second Problem.. > > The XBOX 360 doesn't play x.264 and all the good movies are in x.264. > Converting from x.264 to h.264 could be done offboard on an FPGA > because it takes for-ever to complete on my system (8 hours). This > should have the same premise as the previous issue, minus using a x. > 264 decoding core and possibly directly converting it to h.264 or > doing a decompression-recompression.. > > SPECS: The development system i'm using is the XILINX ML-505 board > with the Virtex 5 chip. This is a open-source project being done for > fun and learning btw. > > Suggestions / Comments / Complaints?Article: 133089
Thanks.... MikeWhy wrote: > "Hauke D" <haukex@zero-g.net> wrote in message > news:9da201d7-42a6-4739-8695-a7b14677b4f8@8g2000hse.googlegroups.com... > > Hi, > > > > Whoops, apologies, I misread your original post, I guess you are using > > EDK :) It's been a while since I worked with EDK, but as long as > > you're generating .bit files you can use iMPACT to configure your FPGA > > with the same procedure. I forget if and how EDK provides > > functionality to configure the FPGA directly... > > EDK just front-ends the ISE tools with support for embedded development. It > uses iMPACT to configure the target device, just as it continues to use XST > and DataMem for their related functions.Article: 133090
This is a multi-part message in MIME format. ------=_NextPart_000_0010_01C8D134.08D23E80 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi all=20 What are the limitations of the free Xilinx Webpack ?=20 Does any one know ?=20 Thanks=20 EC ------=_NextPart_000_0010_01C8D134.08D23E80 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text/html; = charset=3Diso-8859-1"> <META content=3D"MSHTML 6.00.2900.2180" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY> <DIV><FONT size=3D2>Hi all </FONT></DIV> <DIV><FONT size=3D2></FONT> </DIV> <DIV><FONT size=3D2>What are the limitations of the <STRONG><FONT = size=3D3>free=20 Xilinx Webpack</FONT></STRONG> </FONT><FONT size=3D3><STRONG>?=20 </STRONG></FONT></DIV> <DIV><STRONG></STRONG> </DIV> <DIV>Does any one know ? </DIV> <DIV> </DIV> <DIV><FONT size=3D2>Thanks </FONT></DIV> <DIV><FONT size=3D2>EC</FONT></DIV> <DIV><STRONG></STRONG> </DIV></BODY></HTML> ------=_NextPart_000_0010_01C8D134.08D23E80--Article: 133091
RealInfo <therightinfo@yahoo.com> wrote: > Hi all > What are the limitations of the free Xilinx Webpack ? > Does any one know ? > Thanks > EC Did you search for that on teh Xilinx website? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 133092
Sometimes it can be a bit tricky to stop 'X's and 'U's creeping into the logic, especially at startup initialisation. If any logic tries to use these values then Modelsim cheerfully spawns lots of warnings. I've written a function called clean() which goes through a vector and replaces any 'X' or 'U' values with '0'. This sorts out alot of Modelsim problems but I'm slightly worried about any unintended effects on synthesis. It does seem to synthesise without any problems, but can I rely on this for all synth tools or even future XST releases? Is a better solution to meticulously make sure all registers are initialised when they are declared? or is it perfectly safe not necessarily poor coding practise? Cheers RobArticle: 133093
You simulation model should match the behaviour of your hardware, otherwise it is useless. Modern FPGAs initialize all registers upon poweron. You models should reflect that. Just initialize the signales at declaration and you are done. In many ASIC libraries and some older FPGAs the initial values of registers are random. 'X' is the perfect representation for that. You definitely want the 'X's in your simulation in that case because it is the only way to make sure that your circuit works correctly even with random start values. Your circuitry must be design so that all flip-flop eventually obtain defined states. Kolja Sulimma On 18 Jun., 13:25, Rob <BertyBoos...@googlemail.com> wrote: > Sometimes it can be a bit tricky to stop 'X's and 'U's creeping into > the logic, especially at startup initialisation. If any logic tries to > use these values then Modelsim cheerfully spawns lots of warnings. > I've written a function called clean() which goes through a vector and > replaces any 'X' or 'U' values with '0'. This sorts out alot of > Modelsim problems but I'm slightly worried about any unintended > effects on synthesis. It does seem to synthesise without any problems, > but can I rely on this for all synth tools or even future XST > releases? > > Is a better solution to meticulously make sure all registers are > initialised when they are declared? or is it perfectly safe not > necessarily poor coding practise? > > Cheers > RobArticle: 133094
Hai, I want to know which is the right way of implementing and usage of fixed point number data types in hardware(industry standard)..I have referred various FIR implementations where they are mostly handling filter coefficients as integer(truncating from fixed or floating point using MATLAB) or binary.Is it difficult to handle and implement real(fraction) numbers i.e.,filter coefficients values directly in the hardware? for example: sample Filter coefficients generated by FDA tool: fixed point=0.211944580078125 or 16-bit signed integer= 13890 or fixed point binary =0011011001000010 all the above are equivalent but belongs to different data type..Now i am confused which to select for implementation in my code.. Note: Fixed point representation is looking challenging for some synthesis tool as it not supported. Signed integer looks simple but less accurate Fixed point binary looks tedious.. Pls suggest if anyone knew how to convert fixed point to integer or binary ?using which tool?I suspect MATLAB fixed point tool will be useful but i dont know the procedure.. regards, fazaArticle: 133095
> -- Hauke D Thank you for you help, I am going to read it carefully About the vinculum, thank you for the tip but I have to use the FPGA board I have with the Cypress controller. If anyone else has advices, don't hesitate :) XArticle: 133096
On Jun 18, 8:09=A0am, faza <fazulu.v...@gmail.com> wrote: > Hai, > > I want to know which is the right way of implementing and usage of > fixed point number data types in hardware(industry standard)..I have > referred various FIR > implementations where they are mostly handling filter coefficients as > integer(truncating from fixed or floating point using MATLAB) or > binary.Is it difficult to handle and implement real(fraction) numbers > i.e.,filter > coefficients values directly in the hardware? > Google for fixed point VHDL to_ufixed and you'll get the code for the standard (or soon to be a standard) VHDL fixed point package. http://www.google.com/search?source=3Dig&hl=3Den&rlz=3D1G1GGLQ_ENUS278&q=3D= fixed+point+VHDL+to_ufixed Kevin JenningsArticle: 133097
On Jun 18, 7:57 am, Kolja Sulimma <ksuli...@googlemail.com> wrote: > You simulation model should match the behaviour of your hardware, > otherwise it is useless. > Modern FPGAs initialize all registers upon poweron. You models should > reflect that. > Just initialize the signales at declaration and you are done. > > In many ASIC libraries and some older FPGAs the initial values of > registers are random. 'X' is the > perfect representation for that. You definitely want the 'X's in your > simulation in that case because > it is the only way to make sure that your circuit works correctly even > with random start values. > Your circuitry must be design so that all flip-flop eventually obtain > defined states. > > Kolja Sulimma You have just argued against yourself. You have told him to initialize registers in the declaration, then you say you want Xs to represent arbitrary initialization. This arbitrary initialization is what the X is intended to represent, an unknown state. If you really want to model the hardware, you need to *never* initialize registers in the declaration, but rather initialize them in an async reset portion of the process. Then any that you miss show up as Xs and any that you properly initialize should be synthesized that way. RickArticle: 133098
On Jun 18, 1:38 pm, rickman <gnu...@gmail.com> wrote: > On Jun 18, 7:57 am, Kolja Sulimma <ksuli...@googlemail.com> wrote: > > > > > You simulation model should match the behaviour of your hardware, > > otherwise it is useless. > > Modern FPGAs initialize all registers upon poweron. You models should > > reflect that. > > Just initialize the signales at declaration and you are done. > > > In many ASIC libraries and some older FPGAs the initial values of > > registers are random. 'X' is the > > perfect representation for that. You definitely want the 'X's in your > > simulation in that case because > > it is the only way to make sure that your circuit works correctly even > > with random start values. > > Your circuitry must be design so that all flip-flop eventually obtain > > defined states. > > > Kolja Sulimma > > You have just argued against yourself. You have told him to > initialize registers in the declaration, then you say you want Xs to > represent arbitrary initialization. This arbitrary initialization is > what the X is intended to represent, an unknown state. If you really > want to model the hardware, you need to *never* initialize registers > in the declaration, but rather initialize them in an async reset > portion of the process. Then any that you miss show up as Xs and any > that you properly initialize should be synthesized that way. > > Rick This is exactly the problem, i'd rather not give certain registers init values, especially in the data path, as firstly it is unnecessary for the actual hardware implementation and secondly because in simulation seeing a vector of 'X's indicates that this bus hasn't yet been assigned a proper value. The problem comes when that data bus is driving a process that says something like "if data_bus = 0 then...". I can usually avoid this with clock enables, but sometimes it isn't convenient to have a clock enable signal with the data.Article: 133099
>http://biz.yahoo.com/ap/080617/cadence_design_mentor_graphics.html > John Cooley has posted a copy of Fister's letter to Rhines: http://www.deepchip.com/wiretap/080617.html I wonder whether this will wake Synopsys up?
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z