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Hello, Im new to Xilinx core generator tool and have a very fundamental question. I want to generate a single port RAM with an enable signal for the READ operation and the WRITE operation. The write operation works fine. For the read operation, I want to see the output only when a read_enable signal is asserted. I used the "ENA pin" but when asserted I dont see the required output. When I choose the option "Always enabled", it works fine and I see the previous output always. But I want the output only when the read_enable signal is asserted. Can this be done? Thanks for your help. --VandanaArticle: 133776
On Jul 14, 10:26 am, Vandana <nair...@gmail.com> wrote: > Hello, > > Im new to Xilinx core generator tool and have a very fundamental > question. I want to generate a single port RAM with an enable signal > for the READ operation and the WRITE operation. > > The write operation works fine. For the read operation, I want to see > the output only when a read_enable signal is asserted. I used the "ENA > pin" but when asserted I dont see the required output. When I choose > the option "Always enabled", it works fine and I see the previous > output always. But I want the output only when the read_enable signal > is asserted. > > Can this be done? Thanks for your help. > > --Vandana If your memory is generated with block RAM, the ENA pin is actually common to read and write for the single port RAM. So writing will update the data outputs unless you have specified a RAM with output registers and a separate register enable. Also, the output from the block ram will always update on the cycle after the ENA pin is asserted. If you want asynchronous readout, you need to use distributed memory instead. Regards, GaborArticle: 133777
On Jul 14, 11:08 am, Gabor <ga...@alacron.com> wrote: > On Jul 14, 10:26 am, Vandana <nair...@gmail.com> wrote: > > > > > Hello, > > > Im new to Xilinx core generator tool and have a very fundamental > > question. I want to generate a single port RAM with an enable signal > > for the READ operation and the WRITE operation. > > > The write operation works fine. For the read operation, I want to see > > the output only when a read_enable signal is asserted. I used the "ENA > > pin" but when asserted I dont see the required output. When I choose > > the option "Always enabled", it works fine and I see the previous > > output always. But I want the output only when the read_enable signal > > is asserted. > > > Can this be done? Thanks for your help. > > > --Vandana > > If your memory is generated with block RAM, the ENA pin is actually > common > to read and write for the single port RAM. So writing will update the > data outputs unless you have specified a RAM with output registers and > a separate register enable. Also, the output from the block ram will > always update on the cycle after the ENA pin is asserted. If you want > asynchronous readout, you need to use distributed memory instead. > > Regards, > Gabor Thanks, I realised the ENA pin is common to Read/Write and Reset.Article: 133778
Hi All, I'm doing an internal project for my tiny company and have chosen to use a Xilinx XC9572 and an Atmel ATMEGA324P along with 6 74LS245 transceivers for this portion. This project is a board to interface to an ancient (but initially very expensive) machine, replacing the original interface with a modern one. The original is all 5V and I don't care about speed, density, power consumption or cost too much. I'm mostly interested in ease of implementation and reliability. Anyway, I bought a Xilinx USB II cable the other day and was looking for any pointers or tips you may have. I have both Windows XP SP3 and Ubuntu 8.04 available for development. I'd prefer to do most or all work under Ubuntu. Is that practical using the Xilinx toolset? I am currently working on the schematic/board for the above and plan on clocking both the CPLD and uP at 20MHz. Any thoughts on the necessity of using a four-layer board (inner layers power/ground)? The basic function of the CPLD will be to accept byte-wide writes to one of 16 possible registers from the "ancient machine" (Intel 8085 @3.0 MHz.) and to store this in the CPLD as a 12 bit value, possibly double-buffered, then to interrupt the uP. The uP will read and decode the 12 bit value from the CPLD and store the 8 bit part in RAM. Going in the other direction the uP will write to a single 8 bit wide register, possibly double-buffered, in the CPLD which will cause the CPLD to issue an interrupt to the "ancient machine". Sometime later the "ancient machine" will read the register in the CPLD and the CPLD will clear the interrupt line. Back in '86-'88 I got fairly proficient with 22V10s and ABEL. I haven't done any programmable logic since then. Later in this project I'll be using a mid-sized FPGA (probably Spartan 3) to implement some faster and more complex logic (specialized 20 Mbps data stream organized in scan lines) Thanks.Article: 133779
gregben <gregbdelete@laserlabdelete.com> writes: > I'm doing an internal project for my tiny company and have chosen to > use a Xilinx XC9572 and an Atmel ATMEGA324P along with 6 74LS245 > transceivers for this portion. > > I have both Windows XP SP3 and Ubuntu 8.04 available for > development. I'd prefer to do most or all work under Ubuntu. Is that > practical using the Xilinx toolset? I can do XC9572XL development 100% on Linux (Fedora 6) so you shouldn't have a problem with that. I don't use the USB cable, though, I made my own programmer from a spare MCU and the XAPP058 sample program. I can program an XC9572XL in about 12 seconds with it.Article: 133780
Il 13/07/2008 16.50, timinganalyzer ha scritto: > On Jul 13, 2:58 am, Antonio Pasini > <removethis_antonio.pas...@alice.it> wrote: >> Il 07/07/2008 17.26, timinganalyzer ha scritto: >> >>> Hi All, >>> I am pleased to announce this new version of the TimingAnalyzer. The [snip] >> Please add a choice for Windows users to behave as is common accepted >> practice today on Windows. >> >> In any case, looks promising, and I wish you a good success. >> >> Choice is always good. > > Hello Antonio, > > I am in the process of changing the user interface to be more Windows > like. I realize this is a problem and will be making changes in each > beta so it works similar to other windows programs like Visio. > > In the next version, 0.87, you select objects by clicking in them, > Once selected, you click > in them again to deselect them. I'm glad you took my rant with a positive mood :-) Wasn't meant to be offensive at all. Under Windows, it's also common practice to use CTRL to add or remove objects from a selection; when clicking on one without CTRL, all the above selected will be deselected, except the last one. Clicking on a void area should deselect all. > I thought about putting a "Add Edge" mode in so you only add edges > when this mode is selected. Could be useful. It happened to me to adding unwanted edges.. > Thanks for the constructive criticism, even though it was all mostly > all negative, I do feel they are good points. I do agree that the To be more on constructive side, I'm reporting you that I found some glitches in saving images; they were saved in paths different from what I choose. There they were, but not were I saved them; usually in .JAR home dir or original source dir. Also, PNG format didn't work. Another interesting option to add later in the future could be importing VCD waveforms from simulators. The format is relatively easy to parse; could be useful to document particularly critical timings when one has an already working simulation. Thanks Dan for the opportunity to try this.Article: 133781
On Jul 14, 12:45 pm, gregben <gregbdel...@laserlabdelete.com> wrote: > Hi All, > > I'm doing an internal project for my tiny company and have chosen to use > a Xilinx XC9572 and an Atmel ATMEGA324P along with 6 74LS245 > transceivers for this portion. > > This project is a board to interface to an ancient (but initially very > expensive) machine, replacing the original interface with a modern one. > The original is all 5V and I don't care about speed, density, power > consumption or cost too much. I'm mostly interested in ease of > implementation and reliability. > > Anyway, I bought a Xilinx USB II cable the other day and was looking for > any pointers or tips you may have. > > I have both Windows XP SP3 and Ubuntu 8.04 available for development. > I'd prefer to do most or all work under Ubuntu. Is that practical using > the Xilinx toolset? > > I am currently working on the schematic/board for the above and plan on > clocking both the CPLD and uP at 20MHz. Any thoughts on the necessity of > using a four-layer board (inner layers power/ground)? > You didn't mention the package you're using for the XC9572, but in any case 4 layers is probably worth the peace of mind. 2-layer boards need very careful attention to ground and power routing, and remember that even such a venerable part as the XC9572 (not -XL?) still has fairly fast edge rates and flip-flops fast enough to clock on reflections. > The basic function of the CPLD will be to accept byte-wide writes to one > of 16 possible registers from the "ancient machine" (Intel 8085 @3.0 > MHz.) and to store this in the CPLD as a 12 bit value, possibly > double-buffered, then to interrupt the uP. The uP will read and decode > the 12 bit value from the CPLD and store the 8 bit part in RAM. Going in > the other direction the uP will write to a single 8 bit wide register, > possibly double-buffered, in the CPLD which will cause the CPLD to issue > an interrupt to the "ancient machine". Sometime later the "ancient > machine" will read the register in the CPLD and the CPLD will clear the > interrupt line. > > Back in '86-'88 I got fairly proficient with 22V10s and ABEL. I haven't > done any programmable logic since then. > If I'm not mistaken, you can still program the XC9572 in ABEL with the Xilinx webpack tools, but don't quote me on it. However if you plan to move to a small FPGA for the next version I would recommend learning either Verilog or VHDL. The schematic entry tools from Xilinx are not ready for prime time IMHO. > Later in this project I'll be using a mid-sized FPGA (probably Spartan > 3) to implement some faster and more complex logic (specialized 20 Mbps > data stream organized in scan lines) > > Thanks. At 20 MHz, I would suggest looking at Spartan 2 or Spartan 2e to save possible headaches with power supplies. The last time I checked the Spartan 2e was still the cheapest device per user I/O (but not per fabric LUT or flip-flop). What you lose in the Spartan 2 series is the DDR I/O flip-flops and DCM (Digital Clock Manager) but they still have DLL's (delay-locked loops) if you need something simple like a clock doubler. Another cheap source for small to medium FPGA's is the Lattice ECP2 series. These are more along the lines of Spartan 3 feature-wise. With a somewhat larger than minimum-size FPGA in the newer series you should be able to embed a small processor and get rid of your "ancient" CPU as well. Regards, GaborArticle: 133782
I have an AMIRIX board ap1070 . There is a pci bridge (POWERSPAN II ) from TUNDRA on the board which provides the interface communication between the fpga and the pci card. The AMIRIX has given me the source code of the drivers in linux but on windows they have just givenme a exe file which opens a gui application to read and write into the fpga. I have made some changes to the design to provide the ability to write bulk data into the fpga bram. The design works fine with windows but then I donw havee source code and hence cannot do any modifications on the host side. Where as in Linux whenever I run the driver program the system hangs. I dont know why such a thing happens. Is there any good reference material or standard for initializing the pci bridges? Right now I am going through the application note of powerspan II since I suspect that in windowsthe pci bridge registers get programmed properly in windows and in linux they dont. Thanks, D In windows howeverArticle: 133783
On Jul 14, 2:10 pm, Antonio Pasini <removethis_antonio.pas...@alice.it> wrote: > Il 13/07/2008 16.50, timinganalyzer ha scritto: > > > On Jul 13, 2:58 am, Antonio Pasini > > <removethis_antonio.pas...@alice.it> wrote: > >> Il 07/07/2008 17.26, timinganalyzer ha scritto: > > >>> Hi All, > >>> I am pleased to announce this new version of the TimingAnalyzer. The > > [snip] > > > > >> Please add a choice for Windows users to behave as is common accepted > >> practice today on Windows. > > >> In any case, looks promising, and I wish you a good success. > > >> Choice is always good. > > > Hello Antonio, > > > I am in the process of changing the user interface to be more Windows > > like. I realize this is a problem and will be making changes in each > > beta so it works similar to other windows programs like Visio. > > > In the next version, 0.87, you select objects by clicking in them, > > Once selected, you click > > in them again to deselect them. > > I'm glad you took my rant with a positive mood :-) Wasn't meant to be > offensive at all. > > Under Windows, it's also common practice to use CTRL to add or remove > objects from a selection; when clicking on one without CTRL, all the > above selected will be deselected, except the last one. > > Clicking on a void area should deselect all. > > > I thought about putting a "Add Edge" mode in so you only add edges > > when this mode is selected. > > Could be useful. It happened to me to adding unwanted edges.. > > > Thanks for the constructive criticism, even though it was all mostly > > all negative, I do feel they are good points. I do agree that the > > To be more on constructive side, I'm reporting you that I found some > glitches in saving images; they were saved in paths different from what > I choose. There they were, but not were I saved them; usually in .JAR > home dir or original source dir. Also, PNG format didn't work. > > Another interesting option to add later in the future could be importing > VCD waveforms from simulators. > > The format is relatively easy to parse; could be useful to document > particularly critical timings when one has an already working simulation. > > Thanks Dan for the opportunity to try this. Hi Antonio, I see what you mean about the ctrl key. This will be fixed in the next version. I do know about the image directory issue, and that will be fixed in the next version as well. It can read VCD files but I have that disabled for now until I get a chance to test it thoroughly. Now its limited to smaller sized VCD files but I'm looking at ways to speed up the file I/O, or allow the user to select a region in time which would load and display quickly. Thanks for your input. DanArticle: 133784
On Jul 13, 8:21 pm, Andrew FPGA <andrew.newsgr...@gmail.com> wrote: > Hi, > I have designed a VHDL entity that is a subset of the complete design. > I have verified its functionality with a simulation in modelsim and > now I want to run it through the xilinx synthesis(XST) and place and > route tools to verify it meets timing. This entity is a subset of the > complete design, and one of its output ports contains a large number > of signals(several thousand). This fails to map since our target FPGA > does not have several thousand IO pads. How can I run this sub module > through the PAR tools to verify I meet timing? > > Here is what I have tried so far: > 1) IOB over mapping problem solved by unchecking the XST "add I/O > buffers" option. However, the mapper rightfully strips the whole > design since there are now no inputs or outputs. I have unsuccessfully > tried to use the mapper constraint "SAVE NET FLAG". Despite applying > this flag to the inputs and outputs of my submodule, everything still > gets stripped. > > e.g. > attribute s: string; > attribute s of inputs: signal is "yes"; > > The map report says: > The signal "inputs<1><6>" is sourceless and has been removed. > > I can't understand why the the SAVE NET FLAG constraint is not > preserving this signal. Inputs is an array of arrays - perhaps this > attribute can't be applied to such a signal ? > > Has anyone successfully used SAVE NET FLAG on array of arrays before? > What other approaches do folk use to verify timing of a submodule > without letting the IOB's affect the result? > > (I could create some dummy mux logic to mux the outputs down to a > fewer number, so that an achieable number of IOBS are created - But > this will distort the timing and logic usage. > > Cheers > Andrew Check the "-u" option with map. Cheers, Jim (jimwu88 NOOOSPAM at yahoo NOOOSPAM dot com) http://home.comcast.net/%7Ejimwu88/tools/Article: 133785
On 7$B7n(B14$BF|(B, $B2<8a(B9$B;~(B38$BJ,(B, Heiner Litz <heinerl...@googlemail.com> wrote: > Hi, > > since I updated to ISE 10.2 and regenerated my GTPs with coregen I > have simulation problems. All output values from the GTP models are X > although ALL input values driven by the toplevel module are defined (0 > or 1). > > Actually some input values are X but these are derived from a DCM > which is again driven by the PLL lock detect (from the GTPs) so the > main problem is that the PLL does not lock I guess. (however its X and > not zero) The CLKIN and all resets are definitely fine. > > Any ideas? I don't think it necessary to regenerate the IP core if you already have the previous version of the IP core. Maybe you just keep the *.ngc file maybe the GTP block has not compiled or recongonized by modelsim. will cause the error.Article: 133786
vlsi_learner wrote: > I have some IP output data written in an Altera FPGA memory inside the > FPGA. > > I have two questions here > > 1) How can I read the FPGA memory data.Can I use USB blaster cable for > this? Yes, you can examine FPGA memory with the Quartus tools if you compile that option into the design. CHeck the doco... I can't remember what they call it... > 2) Can I somehow dump the memory data into a file for comparison with > a golden result generated? Can't recall if Quartus will allow that, but I'd imagine it would!?! Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 133787
If you use the block RAMs as read-before-write, you will not see the update until read-with-enable (or multiple, sequential write enables.) For this, you do not need to use CoreGen; you can just instantiate the library directly, and apply the appropriate attributes. See the appropriate Xilinx library document. JTW "Vandana" <nairvan@gmail.com> wrote in message news:9200d206-2e95-4c4a-ba05-034d46dba03c@l64g2000hse.googlegroups.com... > On Jul 14, 11:08 am, Gabor <ga...@alacron.com> wrote: >> On Jul 14, 10:26 am, Vandana <nair...@gmail.com> wrote: >> >> >> >> > Hello, >> >> > Im new to Xilinx core generator tool and have a very fundamental >> > question. I want to generate a single port RAM with an enable signal >> > for the READ operation and the WRITE operation. >> >> > The write operation works fine. For the read operation, I want to see >> > the output only when a read_enable signal is asserted. I used the "ENA >> > pin" but when asserted I dont see the required output. When I choose >> > the option "Always enabled", it works fine and I see the previous >> > output always. But I want the output only when the read_enable signal >> > is asserted. >> >> > Can this be done? Thanks for your help. >> >> > --Vandana >> >> If your memory is generated with block RAM, the ENA pin is actually >> common >> to read and write for the single port RAM. So writing will update the >> data outputs unless you have specified a RAM with output registers and >> a separate register enable. Also, the output from the block ram will >> always update on the cycle after the ENA pin is asserted. If you want >> asynchronous readout, you need to use distributed memory instead. >> >> Regards, >> Gabor > > Thanks, I realised the ENA pin is common to Read/Write and Reset.Article: 133788
"Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:ukgm749980f7j127kv2smh4hok8e24jifj@4ax.com... > On Sun, 13 Jul 2008 17:21:23 -0700 (PDT), Andrew FPGA > <andrew.newsgroup@gmail.com> wrote: > >>Hi, >>I have designed a VHDL entity that is a subset of the complete design. >>I have verified its functionality with a simulation in modelsim and >>now I want to run it through the xilinx synthesis(XST) and place and >>route tools to verify it meets timing. This entity is a subset of the >>complete design, and one of its output ports contains a large number >>of signals(several thousand). This fails to map since our target FPGA >>does not have several thousand IO pads. How can I run this sub module >>through the PAR tools to verify I meet timing? > > You can get it through synthesis, and use the synthesis timing estimate > as an indicator whether you are on track for timing or not. The synthesis tool provides a statistical estimate of the delays. Using the mapper option to not strip out unused ports permits accurate measurement of achievable timing, which can be very useful for early identification of problem areas. JTW > IMO there is no point taking it further; the synthesis timing estimates > are slightly conservative in my experience (though they may be accurate > for a 95% full FPGA) so you stand a good chance of exceeding them in > PAR. > > On the other hand, PAR results for a block will probably NOT be repeated > when the same block is incorporated into the whole design. As you fill > up the rest of the FPGA with other stuff, the PAR tools are much more > restricted in their ability to find good fast placement and routes. So > you may believe your timings are achievable based on PAR in an almost > empty FPGA, while in reality they are not, for the entire design. > >> >>Here is what I have tried so far: >>1) IOB over mapping problem solved by unchecking the XST "add I/O >>buffers" option. > > This is the one. It gets you through synthesis, and that gives you > estimated timings above. > >>However, the mapper rightfully strips the whole >>design since there are now no inputs or outputs. > > You *could* create a wrapper with registers on your unit's ports, and > some simple means of combining a thousand pins into a few (e.g. n-way > multiplexer, controlled by a few further external pins). You NEED the > registers; either 2 levels of registers, or ensure registers are NOT > moved into the IOBs, and CHECK the map.mrp report file to make sure that > they aren't. Routes from IOBs into the FPGA fabric can be unbelievably > slow, so you need registers in the fabric... > > Then you have a viable synthesisable unit which can be run through > mapping and PAR. > > But, as above, beware of trusting the timing results if the final design > will be significantly larger. If the synthesis estimates aren't good > enough, these probably aren't either. > > - BrianArticle: 133789
Mark McDougall wrote: OK, I had a quick peek... "In System Memory Content Editor" Yes, you can import/export memory data to/from a file. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266 From poliquin@softcomp.remove-this.com Mon Jul 14 21:27:08 2008 Path: unlimited.newshosting.com!dartmaster!63.218.45.62.MISMATCH!s02-b06.iad01!nx01.iad01.newshosting.com!newshosting.com!novia!border2.nntp.dca.giganews.com!nntp.giganews.com!out03b.usenetserver.com!news.usenetserver.com!in01.usenetserver.com!news.usenetserver.com!in03.usenetserver.com!news.usenetserver.com!pc02.usenetserver.com!fe64.usenetserver.com.POSTED!ae564236!not-for-mail From: Tom P <poliquin@softcomp.remove-this.com> Subject: Re: Xilinx tools in Windows or Linux - Suggestions User-Agent: Pan/0.14.2.91 (As She Crawled Across the Table) Message-Id: <pan.2008.07.15.04.27.07.512650@softcomp.remove-this.com> Newsgroups: comp.arch.fpga References: <3ca02bda-17be-409d-b120-81a14072521d@z24g2000prf.googlegroups.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 28 X-Complaints-To: abuse@usenetserver.com X-Abuse-Info: Please be sure to forward a copy of ALL headers X-Abuse-Info: Otherwise we will be unable to process your complaint properly. NNTP-Posting-Date: Tue, 15 Jul 2008 00:33:13 EDT Date: Mon, 14 Jul 2008 21:27:08 -0700 Xref: unlimited.newshosting.com comp.arch.fpga:109335 On Wed, 25 Jun 2008 11:06:28 -0700, Alex.Louie wrote: > On Jun 25, 7:04 am, muthu...@gmail.com wrote: >> Friends, >> >> I have been using the Xilinx tools ISE, EDK in Windows environment. >> But now planning to use Linux PC for running ISE and EDK. I am >> curious, which platform (Windows or Linux) is good for Xilinx tools? >> I am planning to use the ISE and EDK in GUI mode, not command line >> mode. >> I am using ISE 10.1 on Linux Fedora 5 (old), kernel 2.6.20-1.2316.fc5 and it works great! The USB cable programmer also works well. Xilinx finally did it right and used libusb (standard), so no complicated drive install. Newer versions of Fedora should work fine. Thanks Xilinx! TomArticle: 133790
Hi, I need a GTP design which I can modify and regenerate. I am using cadence ncsim. regs, Heiner On Jul 15, 3:13 am, "dadabu...@gmail.com" <dadabu...@gmail.com> wrote: > On 7$B7n(B14$BF|(B, $B2<8a(B9$B;~(B38$BJ,(B, Heiner Litz <heinerl...@googlemail.com> wrote: > > > Hi, > > > since I updated to ISE 10.2 and regenerated my GTPs with coregen I > > have simulation problems. All output values from the GTP models are X > > although ALL input values driven by the toplevel module are defined (0 > > or 1). > > > Actually some input values are X but these are derived from a DCM > > which is again driven by the PLL lock detect (from the GTPs) so the > > main problem is that the PLL does not lock I guess. (however its X and > > not zero) The CLKIN and all resets are definitely fine. > > > Any ideas? > > I don't think it necessary to regenerate the IP core if you already > have the previous version of the IP core. > Maybe you just keep the *.ngc file > maybe the GTP block has not compiled or recongonized by modelsim. will > cause the error.Article: 133791
On Jul 15, 9:27 am, Tom P <poliq...@softcomp.remove-this.com> wrote: > On Wed, 25 Jun 2008 11:06:28 -0700, Alex.Louie wrote: > > On Jun 25, 7:04 am, muthu...@gmail.com wrote: > >> Friends, > > >> I have been using the Xilinx tools ISE, EDK in Windows environment. > >> But now planning to use Linux PC for running ISE and EDK. I am > >> curious, which platform (Windows or Linux) is good for Xilinx tools? > >> I am planning to use the ISE and EDK in GUI mode, not command line > >> mode. > > I am using ISE 10.1 on Linux Fedora 5 (old), kernel 2.6.20-1.2316.fc5 > and it works great! The USB cable programmer also works well. Xilinx > finally did it right and used libusb (standard), so no complicated > drive install. Newer versions of Fedora should work fine. > > Thanks Xilinx! > > Tom I have been using Xilinx ISE softwares on Ubuntu, and it works perfectly fine. I like to use it with Linux as I can create the make environment and run the softwares which makes them very convenient. -- GoliArticle: 133792
Hi, I have used the core generator for a DDR2 controller and I'm trying to implement my own user application. In my current simulation the controller comes out of calibration but when I try to write to memory the debug output tells me that the data are all X but the user interface waveforms look reasonable. I'm sure I'll find what the problem is in due time but I'm wondering if anyone who walked through this path has any suggestions. Also this is with the Xilinx memory model. I tried a Micron specific memory model I downloaded separately (http://www.freemodelfoundry.com/fmf_vlog_models/ram/mt47h64m16.v) but this one seems to be extremely sensitive to clock frequency and keeps complaining about input clock frequency not being stable even though the changes are only a couple pico seconds every clock. Anyone has experience with this model? Thanks.Article: 133793
> Check the "-u" option with map. Thanks, I had come across that option but felt it was a bit of a "sledgehammer". Its possible some parts of the design should be stripped - and so if I use that option those parts won't get stripped. The SAVE NET FLAG really should be doing the job, but for some reason it isn't working for me. It seems to work fine when I apply SAVE NET FLAG to a scalar or 1d array. But when I apply it to a signal that is an array of arrays, it only seems to effect the first array element. I assume its valid VHDL syntax to apply an attribute to an array of arrays? If yes, then its looking like XST doesn't support this properly - at the very least it would be nice if XST warned it couldn't apply the attribute...Article: 133794
Tom P <poliquin@softcomp.remove-this.com> wrote: > On Wed, 25 Jun 2008 11:06:28 -0700, Alex.Louie wrote: > > On Jun 25, 7:04 am, muthu...@gmail.com wrote: > >> Friends, > >> > >> I have been using the Xilinx tools ISE, EDK in Windows environment. > >> But now planning to use Linux PC for running ISE and EDK. I am > >> curious, which platform (Windows or Linux) is good for Xilinx tools? > >> I am planning to use the ISE and EDK in GUI mode, not command line > >> mode. > >> > I am using ISE 10.1 on Linux Fedora 5 (old), kernel 2.6.20-1.2316.fc5 > and it works great! The USB cable programmer also works well. Xilinx > finally did it right and used libusb (standard), so no complicated > drive install. Newer versions of Fedora should work fine. Xilinx only did it half way right. For the parallel port cables they still use WinDriver instead of /dev/ppdev access. And there is no JTAG API to make custom adapters known to Impact. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 133795
Tom P <poliquin@softcomp.remove-this.com> wrote: > On Wed, 25 Jun 2008 11:06:28 -0700, Alex.Louie wrote: > > On Jun 25, 7:04 am, muthu...@gmail.com wrote: > >> Friends, > >> > >> I have been using the Xilinx tools ISE, EDK in Windows environment. > >> But now planning to use Linux PC for running ISE and EDK. I am > >> curious, which platform (Windows or Linux) is good for Xilinx tools? > >> I am planning to use the ISE and EDK in GUI mode, not command line > >> mode. > >> > I am using ISE 10.1 on Linux Fedora 5 (old), kernel 2.6.20-1.2316.fc5 > and it works great! The USB cable programmer also works well. Xilinx > finally did it right and used libusb (standard), so no complicated > drive install. Newer versions of Fedora should work fine. Xilinx only did it half way right. For the parallel port cables they still use WinDriver instead of /dev/ppdev access. And there is no JTAG API to make custom adapters known to Impact. For the parallel port, libusb-driver http://rmdir.de/~michael/xilinx/ still comes handy -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 133796
Hi FPGA Folk, Is there any xilinx or other documentation that describes what these symbols mean? E.g. Tcko, Tbxcy, Tcinck? The FPGA datasheets define a small subset of all the possible parameters defined in the speedfiles (accessible with speedprint). E.g. Tcko is the flop clock to out. Great. But what about Tbxcy and Tcinck? I can sortof guess what they might be, but surely these are defined somewhere? (I'm using ISE 9.1 sp3 - clicking on the blue underlined hyperlinks in the timing report is only randomly successful. When the work they link to an html view of the logic cell, and highlight the primative that the symbol relates to.) CheersArticle: 133797
On Jul 15, 4:23 am, Muzaffer Kal <k...@dspia.com> wrote: > Hi, > I have used the core generator for a DDR2 controller and I'm trying to > implement my own user application. In my current simulation the > controller comes out of calibration but when I try to write to memory > the debug output tells me that the data are all X but the user > interface waveforms look reasonable. I'm sure I'll find what the > problem is in due time but I'm wondering if anyone who walked through > this path has any suggestions. > Also this is with the Xilinx memory model. I tried a Micron specific > memory model I downloaded separately > (http://www.freemodelfoundry.com/fmf_vlog_models/ram/mt47h64m16.v) but > this one seems to be extremely sensitive to clock frequency and keeps > complaining about input clock frequency not being stable even though > the changes are only a couple pico seconds every clock. Anyone has > experience with this model? > > Thanks. I'm not sure what you mean by core generator DDR2 controller, but if you're talking about MIG, then I have successfully used this with the Micron memory models available on the micron website.Article: 133798
"Andrew FPGA" <andrew.newsgroup@gmail.com> wrote in message news:b8b06151-90c0-4115-a643-35a539d57e49@c58g2000hsc.googlegroups.com... > Hi FPGA Folk, > Is there any xilinx or other documentation that describes what these > symbols mean? E.g. Tcko, Tbxcy, Tcinck? > Andrew, file:///C:/Xilinx/doc/usenglish/help/delay_types/html/web_ds_v4/ta_tbxcy.htm for my installation of ISE8.2. Your location may vary. HTH., Syms.Article: 133799
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