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Philip Herzog ha escrito: > I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where > the FPGA couldn't be routed anymore since it was too full. Now I have to > optimize or reduce some modules to win some area, but I can only guess > which ones use a lot of area so optimizing them would win me significant space. > > Is there a tool (or am I overlooking something in ISE) which tells me which > part of the design uses how much space? I'm aware that optimizing across > hierarchy may make this information inaccurate, but still I guess it would > show me the right way... This is a good free 3rd party tool for this purpose: http://www.conekt.net/fpgaoptim.html Regards, MarcArticle: 133376
Rob schrieb: > Hi, > > I have a problem with getting the correct startup values for an array > of bytes on a Xilinx V5 > When the array is declared it is initialised using a function (which > of course has only constant inputs). In simulation the array appears > to be correctly initialised, but when the bitfile is downloaded it > looks as though all the registers are initialised to zero. > > Is it me or XST!? > > Rob Hi Rob, aren't there any hints (warnings or infos) in your synthesis report. It should be noted somewhere if a piece of code is ignored by the synthesis tool. How is your array synthesized? As a bunch of FFs or as RAM? There are different coding rules for initialisation. But what should be working for both is using some attribute (see the ISE Templates) Using a function for array/RAM/ROM initialisation is similar to using a file. Since this is not covered by the synthesis standard for VHDL 87 or 93 there's no general guideline of how to do it. But some tools are able to do this anyway, so you have to read the tool specific instructions very carefully. (or search this newsgroup, it's a common topic) Have a nice synthesis EilertArticle: 133377
Thanks for your answer > Or do you intend to have two signals on each fpga like this: > > fpga1 fpga2 > -------- ------------ > | | > a_out|----------------->| a_in > | | > b_in |<-----------------| b_out > | | > -------- ------------ Yes that is exactly what I am trying to do, the control FPGA is connected to a seriell Port and I wanna forward the rx and tx signals between the FPGAs so that I can also make use them on the target FPGA. > > In this case you need two UCF files. One for each FPGA. > And there's no special code needed to access the ports. Yes, I also have and UCF File for the Target FPGA where I map the forwarded signals from the control FPGA. So hopefully its fine what I have implemented :) Cheers,Article: 133378
> How about timing / synchronization of the data? > > Is a clock being forwarded from one FPGA to the other, to which the > data is sychronized? > If not, how do you expect the receiving FPGA to know when each data > bit is valid? > > If you want to treat the interface as asynchronous, you need an > additional strobe from the tx which changes when a bit is valid, and > some logic at the receiver side to sync to the receiver's internal > clock to mitigate metastability issues. The logic to handle the tx and rx bits is implemented on the target FPGA. So the only thing I have to do is just forward the rx bits on the Control FPGA to the target FPGA in "real-time" and all the other stuff is then done by a module on the target FPGA...Article: 133379
You can also try ADEPT, which also extracts hierarchical logical utilization and lots more... ADEPT: http://home.comcast.net/%7Ejimwu88/tools/adept/ Screenshot: http://home.comcast.net/%7Ejimwu88/tools/adept/logic_util.jpg It also exports the view to Excel spreadsheet: e.g http://home.comcast.net/%7Ejimwu88/tools/adept/logic_util.xls Cheers, JimArticle: 133380
HI Eilert, The array is being implemented as registers. I've had a look through the syth report and there are two warnings related to the init function and they are produced because a 5 bit vector is being assigned to an 8 bit vector (i'm not sure why simulation didn't warn about this). Maybe this one bad line is causing the init function to fail? I'll reimplement and see what I get. Rob On Jun 26, 9:08 am, backhus <n...@nirgends.xyz> wrote: > Rob schrieb:> Hi, > > > I have a problem with getting the correct startup values for an array > > of bytes on a Xilinx V5 > > When the array is declared it is initialised using a function (which > > of course has only constant inputs). In simulation the array appears > > to be correctly initialised, but when the bitfile is downloaded it > > looks as though all the registers are initialised to zero. > > > Is it me or XST!? > > > Rob > > Hi Rob, > aren't there any hints (warnings or infos) in your synthesis report. > It should be noted somewhere if a piece of code is ignored by the > synthesis tool. > > How is your array synthesized? As a bunch of FFs or as RAM? There are > different coding rules for initialisation. But what should be working > for both is using some attribute (see the ISE Templates) > > Using a function for array/RAM/ROM initialisation is similar to using a > file. Since this is not covered by the synthesis standard for VHDL 87 or > 93 there's no general guideline of how to do it. But some tools are able > to do this anyway, so you have to read the tool specific instructions > very carefully. (or search this newsgroup, it's a common topic) > > Have a nice synthesis > EilertArticle: 133381
jetmarc@hotmail.com writes: > This is a good free 3rd party tool for this purpose: > http://www.conekt.net/fpgaoptim.html You beat me to it :) Thanks for the kind words BTW! While I'm here, I've been hacking on this tool lately to get things like arrays of LUTs with similar names merged into a single entry so that the details of what's being used up within your lowest level blocks is visible. Watch this space... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 133382
Hi all, I'm working on a self reconfigurating system on ml402 (a virtex 4 sx35 device). I tested all bitstreams, full and partial, and they work fine. The problems come when I try to make a self reconfiguration loading bitstreams stored in CF. I successfully generated the system.ace file and I put it on the CF with a partial bitstream. I set the M2:M0 pin to 111 and the selector to SYSACE (also the persist bit option is set correctly). When I turn on the board it loads the system.ace file and configure the system that works fine. The done led is turned on, but also the error led is turned on and the system can't open the partial bitstream from CF. I tried to put some other types of files on CF and make a C code to open and read them, but the result is the same: done led turned on (system configured), and error led turned on. Through serial the program says me that it can't open files because it can't find them. Has anyone any suggestion? Has anyone successfully reconfigured a virtex device through hwicap and CF? I'd really appreciate your help. Thanks. Regards, Paolo FuriaArticle: 133383
Hi all; i am trying to use lock_pins to lock theinstantiated LUTs pins , iam using ISE 9.1 and my family is virtex 2 pro, first i tried to do this using ucf file and it works, but i want to do this by adding this attribute in the vhdl file , i got an error during the mapping phase , i don't know what is it what i wrote in the vhdl attribute INIT : string; attribute INIT of LUT1_o0_s: label is "2"; attribute lock_pins: string; attribute lock_pins of LUT1_o0_s: label is "true"; begin LUT1_o0_s : LUT1 generic map ( INIT =>"01") port map (O => o0_s, I0 => aleft0right); and the error Using target part "2vp30ff896-7". Mapping design into LUTs... ERROR:MapLib:688 - Pin true in LOCK_PINS constraint does not exist. Error found in mapping process, exiting... Errors found during the mapping phase. Please see map report file for more details. Output files will not be written. thanks fatmaArticle: 133384
Hi, is it possible to configure and start the Xilinx IPIF dma s/g transfer via the userlogic. how can i write into the dma registers from vhdl? thnx sebastianArticle: 133385
Hi Rob,
Besides the bus widths issue, here's what you can do for initialisation
without need for a function.
e.g. (kept simple with 8 bit only)
constant init_vector : std_logic_vector(7 downto 0) := "10011001";
reg1:process(Reset,clock)
begin
if Reset='1' then
four bit register <= init_vector(7 downto 3);
elsif rising_edge(clock) then
...
end
reg2:process(Reset,clock)
begin
if Reset='1' then
one_bit_register <= init_vector(0);
elsif rising_edge(clock) then
...
end
optional:
Reset <='0';
_____________________
Thus the registers become initialized to the constant value on Reset.
And if Reset is tied to a constant inactive value, the initialisation
values should still be used by XST as power-on init values (not 100%
sure) , while the reset network is ripped away.
Thus you have a central point where you can change your init values and
may even use hex values if you like (e.g: X"99" for the example above)
Have a nice synthesis
Eilert
Rob schrieb:
> HI Eilert,
>
> The array is being implemented as registers. I've had a look through
> the syth report and there are two warnings related to the init
> function and they are produced because a 5 bit vector is being
> assigned to an 8 bit vector (i'm not sure why simulation didn't warn
> about this).
> Maybe this one bad line is causing the init function to fail? I'll
> reimplement and see what I get.
>
> Rob
>
> On Jun 26, 9:08 am, backhus <n...@nirgends.xyz> wrote:
>> Rob schrieb:> Hi,
>>
>>> I have a problem with getting the correct startup values for an array
>>> of bytes on a Xilinx V5
>>> When the array is declared it is initialised using a function (which
>>> of course has only constant inputs). In simulation the array appears
>>> to be correctly initialised, but when the bitfile is downloaded it
>>> looks as though all the registers are initialised to zero.
>>> Is it me or XST!?
>>> Rob
>> Hi Rob,
>> aren't there any hints (warnings or infos) in your synthesis report.
>> It should be noted somewhere if a piece of code is ignored by the
>> synthesis tool.
>>
>> How is your array synthesized? As a bunch of FFs or as RAM? There are
>> different coding rules for initialisation. But what should be working
>> for both is using some attribute (see the ISE Templates)
>>
>> Using a function for array/RAM/ROM initialisation is similar to using a
>> file. Since this is not covered by the synthesis standard for VHDL 87 or
>> 93 there's no general guideline of how to do it. But some tools are able
>> to do this anyway, so you have to read the tool specific instructions
>> very carefully. (or search this newsgroup, it's a common topic)
>>
>> Have a nice synthesis
>> Eilert
>
Article: 133386On Jun 25, 3:01 pm, Philip Herzog <p...@arcor.de> wrote: > Hi! > > I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where > the FPGA couldn't be routed anymore since it was too full. Now I have to > optimize or reduce some modules to win some area, but I can only guess > which ones use a lot of area so optimizing them would win me significant = space. > > Is there a tool (or am I overlooking something in ISE) which tells me whi= ch > part of the design uses how much space? I'm aware that optimizing across > hierarchy may make this information inaccurate, but still I guess it woul= d > show me the right way... > > - Philip > -- > Frauenparkpl=E4tze sind eine gute Sache - fr=FCher ist > man als Triebt=E4ter stundenlang ziellos durch's > Parkhaus geirrt. (Andreas Leidig) Any module that has been put in an area group will have its own resource utilization reported in the area groups section of the map report. For all of the cores that we have designed for our EDK package, we create core level UCF files and put the core in an area group. Some times we put constraints on the area group, and some times it is just there to get more detailed reporting. Refer to the Xilinx constraint guide for more information on area group constraints. Regards, John McCaskill www.FasterTechnology.com/cores.htmlArticle: 133387
Is it possible to use the System Generator for DSP with the ML403 with
GigabitEthernet or USB? They only support ML402 directly, why?
Has anybody a BSB and sources how to manage it to use ML403 for DSP
with Matlab programs?
Thx
Eric
From webmaster@nillakaes.de Thu Jun 26 09:24:38 2008
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From: Thorsten Kiefer <webmaster@nillakaes.de>
Subject: synthesis error
Newsgroups: comp.arch.fpga
Date: Thu, 26 Jun 2008 18:24:38 +0200
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Hi,
synthesizing the following code yields an error.
CODE :
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:22:54 06/23/2008
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity main is
port(
clk,reset : in std_logic;
btn: std_logic_vector(2 downto 0);
rx : in std_logic;
tx : out std_logic;
led: out std_logic_vector(7 downto 0);
sseg : out std_logic_vector(7 downto 0);
an : out std_logic_vector(3 downto 0);
-- to/from chip
ad : out std_logic_vector(17 downto 0);
we_n, oe_n : out std_logic;
-- SRAM chip a
dio_a : inout std_logic_vector(15 downto 0);
ce_a_n,ub_a_n,lb_a_n : out std_logic;
-- SRAM chip b
dio_b : inout std_logic_vector(15 downto 0);
ce_b_n,ub_b_n,lb_b_n : out std_logic
);
end main;
architecture Behavioral of main is
signal tx_full, rx_empty: std_logic;
signal rx_data,tx_data : std_logic_vector(7 downto 0);
signal btn_tick: std_logic;
signal mem : std_logic;
signal mem_rw : std_logic;
signal mem_addr : std_logic_vector(17 downto 0);
signal mem_data_f2s : std_logic_vector(31 downto 0);
signal mem_data_s2f : std_logic_vector(31 downto 0);
signal mem_ready : std_logic;
signal h2a_hex : std_logic_vector(3 downto 0);
signal h2a_ascii : std_logic_vector(7 downto 0);
signal wr_uart,rd_uart : std_logic;
type state_t is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10);
type regs_t is record
state : state_t;
led : std_logic_vector(7 downto 0);
hex : unsigned(3 downto 0);
end record;
signal r_reg,r_next : regs_t;
begin
uart_unit : entity uart
port map(clk=>clk,reset=>reset,rd_uart=>rd_uart,wr_uart=>wr_uart,
rx=>rx,w_data=>tx_data,tx_full=>tx_full,rx_empty=>rx_empty,
r_data=>rx_data,tx=>tx);
btn_db_unit : entity debounce
port
map(clk=>clk,reset=>reset,button=>btn(0),db_level=>open,db_tick=>btn_tick);
sram_unit : entity sram_ctrl
port
map(clk=>clk,reset=>reset,ad=>ad,we_n=>we_n,oe_n=>oe_n,dio_a=>dio_a,ce_a_n=>ce_a_n,
ub_a_n=>ub_a_n,lb_a_n=>lb_a_n,dio_b=>dio_b,ce_b_n=>ce_b_n,ub_b_n=>ub_b_n,lb_b_n=>lb_b_n,
mem=>mem,rw=>mem_rw,addr=>mem_addr,data_f2s=>mem_data_f2s,data_s2f=>mem_data_s2f,ready=>mem_ready);
hex2a : entity hex2ascii port map(hex=>h2a_hex,ascii=>h2a_ascii);
an <= "1110";
sseg <= '1' & (not tx_full) & "11" & (not rx_empty) & "111";
process(clk,reset)
begin
if reset = '1' then
r_reg.state <= s0;
r_reg.led <= "11111111";
r_reg.hex <= (others=>'0');
elsif rising_edge(clk) then
r_reg <= r_next;
end if;
end process;
process(r_reg)
begin
r_next <= r_reg;
mem_addr <= "000000000000000000";
mem_rw <= '0';
mem_data_f2s <= "00000000000000000000000000000000";
wr_uart <= '0';
tx_data <= "00000000";
case r_reg.state is
when s0 =>
if btn_tick='1' then
r_next.state <= s1;
mem_addr <= "111111111111111111";
mem_rw <= '0';
mem_data_f2s <= "01010101010101010101010101010101";
end if;
when s1 =>
if mem_ready='1' then
r_next.state <= s2;
end if;
when s2 =>
r_next.state <= s3;
mem_addr <= "111111111111111111";
mem_rw <= '1';
when s3 =>
if mem_ready='1' then
r_next.state <= s4;
end if;
when s4 =>
r_next.led <= mem_data_f2s(7 downto 0);
r_next.state <= s5;
when s5 =>
wr_uart <= '1';
r_next.hex <= r_reg.hex + 1;
r_next.state <= s6;
when others =>
r_next.state <= s0;
end case;
end process;
tx_data <= h2a_ascii;
h2a_hex <= std_logic_vector(r_reg.hex);
led <= r_reg.led;
end Behavioral;
ERROR:
=========================================================================
* Low Level Synthesis *
=========================================================================
ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<7>>; this
signal is connected to multiple drivers.
Drivers are:
Output port doA<7> of instance <hex2a/Mrom_ascii> of inferred macro ROM
Signal <h2a_ascii<7>> in Unit <main> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<6>>; this
signal is connected to multiple drivers.
Drivers are:
Output port doA<6> of instance <hex2a/Mrom_ascii> of inferred macro ROM
Signal <h2a_ascii<6>> in Unit <main> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<5>>; this
signal is connected to multiple drivers.
Drivers are:
Output port doA<5> of instance <hex2a/Mrom_ascii> of inferred macro ROM
Signal <h2a_ascii<5>> in Unit <main> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<4>>; this
signal is connected to multiple drivers.
Drivers are:
Output port doA<4> of instance <hex2a/Mrom_ascii> of inferred macro ROM
Signal <h2a_ascii<4>> in Unit <main> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<3>>; this
signal is connected to multiple drivers.
Drivers are:
Output port doA<3> of instance <hex2a/Mrom_ascii> of inferred macro ROM
Signal <h2a_ascii<3>> in Unit <main> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<2>>; this
signal is connected to multiple drivers.
Drivers are:
Output port doA<2> of instance <hex2a/Mrom_ascii> of inferred macro ROM
Signal <h2a_ascii<2>> in Unit <main> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<1>>; this
signal is connected to multiple drivers.
Drivers are:
Output port doA<1> of instance <hex2a/Mrom_ascii> of inferred macro ROM
Signal <h2a_ascii<1>> in Unit <main> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<0>>; this
signal is connected to multiple drivers.
Drivers are:
Output port doA<0> of instance <hex2a/Mrom_ascii> of inferred macro ROM
Signal <h2a_ascii<0>> in Unit <main> is assigned to GND
Where do is assign h2s_ascii to ground ?
Best regards
Thorsten
Article: 133388"Thorsten Kiefer" <webmaster@nillakaes.de> wrote in message news:4863c2c9$0$25950$6e1ede2f@read.cnntp.org... > Hi, > synthesizing the following code yields an error. > > CODE : > > ---------------------------------------------------------------------------------- > -- Company: > -- Engineer: > -- > -- Create Date: 16:22:54 06/23/2008 > -- Design Name: > -- Module Name: main - Behavioral > -- Project Name: > -- Target Devices: > -- Tool versions: > -- Description: > -- > -- Dependencies: > -- > -- Revision: > -- Revision 0.01 - File Created > -- Additional Comments: > -- > ---------------------------------------------------------------------------------- > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.numeric_std.ALL; > > ---- Uncomment the following library declaration if instantiating > ---- any Xilinx primitives in this code. > --library UNISIM; > --use UNISIM.VComponents.all; > > entity main is > port( > clk,reset : in std_logic; > btn: std_logic_vector(2 downto 0); > rx : in std_logic; > tx : out std_logic; > led: out std_logic_vector(7 downto 0); > sseg : out std_logic_vector(7 downto 0); > an : out std_logic_vector(3 downto 0); > > -- to/from chip > ad : out std_logic_vector(17 downto 0); > we_n, oe_n : out std_logic; > -- SRAM chip a > dio_a : inout std_logic_vector(15 downto 0); > ce_a_n,ub_a_n,lb_a_n : out std_logic; > -- SRAM chip b > dio_b : inout std_logic_vector(15 downto 0); > ce_b_n,ub_b_n,lb_b_n : out std_logic > ); > end main; > > architecture Behavioral of main is > signal tx_full, rx_empty: std_logic; > signal rx_data,tx_data : std_logic_vector(7 downto 0); > signal btn_tick: std_logic; > signal mem : std_logic; > signal mem_rw : std_logic; > signal mem_addr : std_logic_vector(17 downto 0); > signal mem_data_f2s : std_logic_vector(31 downto 0); > signal mem_data_s2f : std_logic_vector(31 downto 0); > signal mem_ready : std_logic; > signal h2a_hex : std_logic_vector(3 downto 0); > signal h2a_ascii : std_logic_vector(7 downto 0); > signal wr_uart,rd_uart : std_logic; > > type state_t is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10); > type regs_t is record > state : state_t; > led : std_logic_vector(7 downto 0); > hex : unsigned(3 downto 0); > end record; > signal r_reg,r_next : regs_t; > > begin > uart_unit : entity uart > port > map(clk=>clk,reset=>reset,rd_uart=>rd_uart,wr_uart=>wr_uart, > > rx=>rx,w_data=>tx_data,tx_full=>tx_full,rx_empty=>rx_empty, > r_data=>rx_data,tx=>tx); > btn_db_unit : entity debounce > port > map(clk=>clk,reset=>reset,button=>btn(0),db_level=>open,db_tick=>btn_tick); > sram_unit : entity sram_ctrl > port > map(clk=>clk,reset=>reset,ad=>ad,we_n=>we_n,oe_n=>oe_n,dio_a=>dio_a,ce_a_n=>ce_a_n, > > ub_a_n=>ub_a_n,lb_a_n=>lb_a_n,dio_b=>dio_b,ce_b_n=>ce_b_n,ub_b_n=>ub_b_n,lb_b_n=>lb_b_n, > > mem=>mem,rw=>mem_rw,addr=>mem_addr,data_f2s=>mem_data_f2s,data_s2f=>mem_data_s2f,ready=>mem_ready); > hex2a : entity hex2ascii port map(hex=>h2a_hex,ascii=>h2a_ascii); > > an <= "1110"; > sseg <= '1' & (not tx_full) & "11" & (not rx_empty) & "111"; > > process(clk,reset) > begin > if reset = '1' then > r_reg.state <= s0; > r_reg.led <= "11111111"; > r_reg.hex <= (others=>'0'); > elsif rising_edge(clk) then > r_reg <= r_next; > end if; > end process; > > process(r_reg) > begin > r_next <= r_reg; > mem_addr <= "000000000000000000"; > mem_rw <= '0'; > mem_data_f2s <= "00000000000000000000000000000000"; > wr_uart <= '0'; > tx_data <= "00000000"; > > case r_reg.state is > when s0 => > if btn_tick='1' then > r_next.state <= s1; > mem_addr <= "111111111111111111"; > mem_rw <= '0'; > mem_data_f2s <= > "01010101010101010101010101010101"; > end if; > when s1 => > if mem_ready='1' then > r_next.state <= s2; > end if; > when s2 => > r_next.state <= s3; > mem_addr <= "111111111111111111"; > mem_rw <= '1'; > when s3 => > if mem_ready='1' then > r_next.state <= s4; > end if; > when s4 => > r_next.led <= mem_data_f2s(7 downto 0); > r_next.state <= s5; > when s5 => > wr_uart <= '1'; > r_next.hex <= r_reg.hex + 1; > r_next.state <= s6; > when others => > r_next.state <= s0; > end case; > end process; > > tx_data <= h2a_ascii; > h2a_hex <= std_logic_vector(r_reg.hex); > led <= r_reg.led; > end Behavioral; > > > ERROR: > ========================================================================= > * Low Level Synthesis * > ========================================================================= > > ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<7>>; this > signal is connected to multiple drivers. > Drivers are: > Output port doA<7> of instance <hex2a/Mrom_ascii> of inferred macro ROM > Signal <h2a_ascii<7>> in Unit <main> is assigned to GND > > ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<6>>; this > signal is connected to multiple drivers. > Drivers are: > Output port doA<6> of instance <hex2a/Mrom_ascii> of inferred macro ROM > Signal <h2a_ascii<6>> in Unit <main> is assigned to GND > > ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<5>>; this > signal is connected to multiple drivers. > Drivers are: > Output port doA<5> of instance <hex2a/Mrom_ascii> of inferred macro ROM > Signal <h2a_ascii<5>> in Unit <main> is assigned to GND > > ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<4>>; this > signal is connected to multiple drivers. > Drivers are: > Output port doA<4> of instance <hex2a/Mrom_ascii> of inferred macro ROM > Signal <h2a_ascii<4>> in Unit <main> is assigned to GND > > ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<3>>; this > signal is connected to multiple drivers. > Drivers are: > Output port doA<3> of instance <hex2a/Mrom_ascii> of inferred macro ROM > Signal <h2a_ascii<3>> in Unit <main> is assigned to GND > > ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<2>>; this > signal is connected to multiple drivers. > Drivers are: > Output port doA<2> of instance <hex2a/Mrom_ascii> of inferred macro ROM > Signal <h2a_ascii<2>> in Unit <main> is assigned to GND > > ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<1>>; this > signal is connected to multiple drivers. > Drivers are: > Output port doA<1> of instance <hex2a/Mrom_ascii> of inferred macro ROM > Signal <h2a_ascii<1>> in Unit <main> is assigned to GND > > ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<0>>; this > signal is connected to multiple drivers. > Drivers are: > Output port doA<0> of instance <hex2a/Mrom_ascii> of inferred macro ROM > Signal <h2a_ascii<0>> in Unit <main> is assigned to GND > > > > Where do is assign h2s_ascii to ground ? > > Best regards > Thorsten h2s_ascii is neither an input nor is it assigned anything .. it is a floating undefined net .. that is your problem. MikeArticle: 133389
On Jun 25, 2:49 pm, Duth <premd...@gmail.com> wrote: > 11.1 is planned to be released a year after 10.1. That means plan for > March 2009. Xilinx is considering working with some customers on a > beta program to get feedback for the NCSim and Synopsys support. If > interested in this, please contact your Xilinx FAE. > > Aldec simulators are not supported by Xilinx and that is why you will > probably need to talk to Aldec to get their roadmaps. Thank you for an straightforward response. When I contacted Aldec about Verilog-2005 SecureIP support, they hinted that the vendor (Xilinx) must provide an encrypted model for the Aldec-simulator, i.e., the IP-publisher is responsible for re-generating the IP-model on each supported platform (simulator.) Here's Aldec's apnote on EDK 10.1: http://support.aldec.com/KnowledgeBase/Article.aspx?aid=000737 "Import and Simulation Behavioral model including SecureIP encryption. Currently, the MicroBlaze behavioral model is not provided for Aldec Active-HDL7.3sp1 simulator. If you are interested in it please ask Xilinx support to encrypt them as SecureIP for us." I don't know whether that's really the case... I assume the *real* issue is more complicated than just this, otherwise EDK 10.1 would have shipped with out-of-the-box Synopsys/VCS and Cadence/NCsim support?Article: 133390
On Jun 26, 8:15 am, fmostafa <fatma.abouele...@ugent.be> wrote: > Hi all; > > i am trying to use lock_pins to lock theinstantiated LUTs pins , > iam using ISE 9.1 and my family is virtex 2 pro, first i tried to do > this using ucf file and it works, but i want to do this by adding this > attribute in the vhdl file , i got an error during the mapping phase , > i don't know what is it > > what i wrote in the vhdl > > attribute INIT : string; > attribute INIT of LUT1_o0_s: label is "2"; > attribute lock_pins: string; > attribute lock_pins of LUT1_o0_s: label is "true"; > begin > > LUT1_o0_s : LUT1 > generic map ( > INIT =>"01") > port map (O => o0_s, > I0 => aleft0right); > > and the error > > Using target part "2vp30ff896-7". > Mapping design into LUTs... > ERROR:MapLib:688 - Pin true in LOCK_PINS constraint does not exist. > > Error found in mapping process, exiting... > Errors found during the mapping phase. Please see map report file for > more > details. Output files will not be written. > > thanks > fatma Try changing "true" to "ALL". Cheers, HTH, Jim (jimwu88 NOOOSPAM at yahoo NOOOSPAM dot com) http://home.comcast.net/%7Ejimwu88/tools/Article: 133391
Forgot to mention that the "Constraints Guide" PDF in %XILINX%\doc \usenglish\books\docs\cgd is a good reference for constraint related issue. Cheers, Jim (jimwu88 NOOOSPAM at yahoo NOOOSPAM dot com) http://home.comcast.net/%7Ejimwu88/tools/Article: 133392
Mike Lewis wrote: > "Thorsten Kiefer" <webmaster@nillakaes.de> wrote in message > news:4863c2c9$0$25950$6e1ede2f@read.cnntp.org... >> Hi, >> synthesizing the following code yields an error. >> >> CODE : >> .. snip.. >> signal h2a_hex : std_logic_vector(3 downto 0); >> signal h2a_ascii : std_logic_vector(7 downto 0); .. snip.. >> hex2a : entity hex2ascii port map(hex=>h2a_hex,ascii=>h2a_ascii); >> .. snip .. >> >> tx_data <= h2a_ascii; >> .. snip .. >> ERROR:Xst:528 - Multi-source in Unit <main> on signal <h2a_ascii<7>>; this >> signal is connected to multiple drivers. >> Drivers are: >> Output port doA<7> of instance <hex2a/Mrom_ascii> of inferred macro ROM >> Signal <h2a_ascii<7>> in Unit <main> is assigned to GND >> .. snip .. >> >> >> Where do is assign h2s_ascii to ground ? >> >> Best regards >> Thorsten > > h2s_ascii is neither an input nor is it assigned anything .. it is a > floating undefined net .. that is your problem. > It assigned to something, but we and the synthesizer don't know what it is as the hex2ascii component wasn't defined. There was probably another synthesis warning on the "hex2a : entity hex2ascii" line. Ed McGettigan -- Xilinx Inc.Article: 133393
"backhus" <nix@nirgends.xyz> wrote in message news:g403su$soj$1@news.hs-bremen.de... > > Hi Rob, > Besides the bus widths issue, here's what you can do for initialisation > without need for a function. > <snip> > > _____________________ > > Thus the registers become initialized to the constant value on Reset. > And if Reset is tied to a constant inactive value, the initialisation > values should still be used by XST as power-on init values (not 100% sure) > , while the reset network is ripped away. This is in no way equivalent to assigning an initial value. While it is generally better from a design perspective to reset things with a reset signal rather than counting on intial value assignments, what you've described with tying reset to a 'constant value' will end up either not initializing anything on reset since the code inside the "if Reset = '1' then" will never be executed (assuming Reset is tied to a constant '0') or the code inside the "elsif rising_edge(clock) then" will never be executed (assuming that Reset is tied to a constant '1'). In either case, you won't get what you want. Kevin JenningsArticle: 133394
"KJ" <kkjennings@sbcglobal.net> wrote in message news:tZS8k.1343$np7.1219@flpi149.ffdc.sbc.com... > Slight correction to previous, I missed the word 'inactive' in your sentence "And if Reset is tied to a constant inactive value..". This means then the latter part of my post was not correct, but the first part still is. In any case, the code inside the "if Reset = '1' then" portion will be synthesized away, and no assignments having to do with 'init_vector' will occur, ever...not a very good replacement for an initial value assignment. Kevin JenningsArticle: 133395
On Jun 26, 12:28 am, meralonu...@gmail.com wrote: > Spartan 3E starter kit: > I tried (like all beginners) to read rotary switch (knob) using FSM > with 8 states, 4 for CW and 4 for CCW movements. I did not debounce > phased switch inputs. It works fine. But I remember seeing much debate > on this issue and claims of success with 4 FF's (plus debouncers). My > design created 3 FFs and works fine without debouncers. What have I > done wrong? Do "Spartan 3E starter kits" already have debouncers? > Another question: When I include something like a<=a+1; and a<=a-1; it > puts adders and stuff. Is it possible to force the use of async. up- > down counters? > Thanks The smallest possible Quad design uses 2 FFs, so you have done nothing wrong. The earlier discussion here included an optional 'anti-flicker' state engine of 2 more FF's that could have some merit for user interfaces (but added backlash, so less ideal for machine control) The Two FF design, effectively overlays the state follower, with the two LSB bits in the counter. It is also a design decision, on what you do with the illegal states. Check your report file. If you avoided syncronisers, and have more than one state bit dependent on an async pin, then you _could_ have aperture errors - in a hand control, it will be hard to even spot this, but in a machine control, it could cause serious control problems. -jgArticle: 133396
On Jun 26, 6:36=A0pm, Heinrich <Heinr...@myweb.com> wrote: > The logic to handle the tx and rx bits is implemented on the target > FPGA. So the only thing I have to do is just forward the rx bits on the > Control FPGA to the target FPGA in "real-time" and all the other stuff > is then done by a module on the target FPGA... Well ok, but if you don't tell us what you've done, we can't tell you if you've done it correctly or not! If you've got data lines only (no clock or async handshaking), you need clock transferred by some other method - either explicitly or in a way that the clock can be extracted/implied from the data stream. -TArticle: 133397
Starting on April 20 this year there was a 3-week long thread about quadrature decoding. 85 postings!!! Let me summarize for a beginner: You should assume that the quadrature input is asynchronous, can have totally undefined duty cycle (down to pulses below 1 ns) and will have undefined bounce whenever it makes or breaks contact. You can however assume that, when one contact changes, the other one will be stable. Then you have to decide how many counts you want to decode: One count per any change, or one count per full cycle. Then you must decide whether a one-quadrature or 2-quadrature ambiguity is acceptable. You can also call that backlash. Manually operated switches are very forgiving, robotics shaft encoders can be far more demanding. I put two designs into the Xilinx forums or blogs, but various people had widely varying opinions. I think this here is a fair synopsis. Peter Alfke, Xilinx Applications.Article: 133398
Hi all, For the ram implied in a CPLD design, will the data written in it remain after power off? I have a small rom in my curent CPLD design, occasionally I need change the content inside, instead of reprogramming it, I want something like a nvram that I can update through the uP dynamicallly. Thanks, JayArticle: 133399
On 26 Jun., 18:24, Thorsten Kiefer <webmas...@nillakaes.de> wrote: > Hi, > synthesizing the following code yields an error. [..] > Where do is assign h2s_ascii to ground ? You connect h2a_ascii with tx_data. I guess tx_data is the real problem, as it is connected to gnd in process and h2a_ascii in concurrent statement. Without the component declarations I can only guess, that the entity inside drives h2a and sources tx_data. It would be a good idea to include the component declarations. I know why I use std_ulogic instead of std_logic :). bye Thomas
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