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On 19 Jun., 11:48, Saransh <mehrotrasara...@gmail.com> wrote: > Hi all, > > When I do Generate Netlist in Xilinx 9.2i, I get the following error > - > > ------------------------- > ./synthesis.sh: line 2: $'\r': command not found > ./synthesis.sh: line 4: $'\r': command not found > ./synthesis.sh: line 6: $'\r': command not found > ./synthesis.sh: line 8: $'\r': command not found > > ERROR:Xst:1688 - Unknown option for -intstyle switch. > ./synthesis.sh: line 17: syntax error: unexpected end of file > make: *** [implementation/system.ngc] Error 2 > Done! > > --------------------------- > > Could anyone please help me out in this matter. Hi, I had the same problem. Have a look at http://www.xilinx.com/support/answers/24134.htm In short: You need to create an Env Variable SHELLOPTS and set it to 'igncr' This should help...Article: 133426
On Jun 28, 6:07 am, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Evan Lavelle wrote: > > On Sat, 28 Jun 2008 09:00:03 +1200, Jim Granville > > <no.s...@designtools.maps.co.nz> wrote: > > >>Is this homework ? > > > I did my last "homework", as you put it, 28 years ago, in Quantum > > Mechanics. > > >>The design is not usually going to stay on paper, it has to > >>end up in silicon. That makes most of this irrelevent. > > > There's a common misconception that K-maps are/were only used for > > minimisation, so they're now irrelevant. Actually, K-maps are probably > > the most fundamental tool for the design, specification, and analysis > > of combinatorial logic. They're also independent of the > > implementation, which makes them ideally suited for verification of > > the same circuits. They're about 'what', not 'how'. An HDL > > description, on the other hand, is exactly the opposite - 'how', not > > 'what'. As I said originally, this is about verification. The fact > > that the K-map may or may not end up in silicon is "irrelevant". > > I'm still trying to get a handle on the 'why' ? > > > Leon asked whether anyone still used K-maps for programmable logic; a > > good question, without being condescending. I don't imagine many > > people use them to fill up FPGAs. On the other hand, I'm sure there > > are still people in this NG who do digital logic design, and some of > > them may occasionally even do non-trivial combinatorial logic. > > Do you mean actual FET level logic ? > Even at the lowest combinatorial logic, I still look at the tools > output, and often they do eqn invert, or do D/T/XOR synthesis swapping > in order to pack things more efficently. > > -jg The last time I did Karnaugh maps was in an attempt to get 8b10b encoding into a CPLD. In this case I also had more than 4 inputs and I have to say that human interaction with such maps is not easy no matter how you slice it. This is like trying to envisage objects with more than 3 dimensions. However to answer the original question, the fact that 'B' lines up left in one map and right in the other is useful if you view them side-by-side as in your post, rather than stacked up as in a 3D viewer. Still an explanation of the end use of this would be interesting... Regards, GaborArticle: 133427
Xilinx ISE 9.2 and ISE 10.1
I wanted to design a simple correlator which correlates a 15 bit
sequence with another sequence of 15 bytes (8 bit signed values =
Sample below). I needed to zero the summation result after 15 samples,
so I did. But compiler didn't. There is no warning but even the
simulator does not seem to notice ACC <= x"000000"; line. I do not see
a reset input for the inferred updown accumulator in the RTL schematic
either. But I see an unconnected D(L:R) input on accumulator.
I see that, from the simulator outputs, Corr<=ACC; line is synthesized
and working ok, though.
What am I missing. Thanks for help to the beginner.
Additional question (bonus? :-( ) : Waveform editor does not accept
-100 for a 8-bit signed decimal signal but displays -28 instead. When
I enter binary 10011100 which corresponds to -100 and display the
values in decimal it interestingly displays -100. Does it mean -28
equals to -100 somehow?
architecture Rec of Rec is
constant PN : BIT_VECTOR (14 downto 0) := "000100110101111";
signal ACC : SIGNED (23 downto 0) := x"000000";
signal cntr : integer range 0 to 14 := 0;
begin
process(clk) begin
if(clk'event and clk='1') then
if(cntr=0) then
Corr <= ACC;
ACC <= x"000000"; -- Problematic line is this one
end if;
if(PN(cntr)='1') then
ACC <= ACC + Sample;
else
ACC <= ACC - Sample;
end if;
if(cntr=14) then
cntr <= 0;
else
cntr <= cntr +1;
end if;
end if;
end process;
end Rec;
Article: 133428On Sat, 28 Jun 2008 09:00:28 +0100, Evan Lavelle wrote: > On Sat, 28 Jun 2008 09:00:03 +1200, Jim Granville > <no.spam@designtools.maps.co.nz> wrote: > >>Is this homework ? > > I did my last "homework", as you put it, 28 years ago, in Quantum > Mechanics. > >>The design is not usually going to stay on paper, it has to end up in >>silicon. That makes most of this irrelevent. > > There's a common misconception that K-maps are/were only used for > minimisation, so they're now irrelevant. Actually, K-maps are probably > the most fundamental tool for the design, specification, and analysis of > combinatorial logic. They're also independent of the implementation, > which makes them ideally suited for verification of the same circuits. > They're about 'what', not 'how'. An HDL description, on the other hand, > is exactly the opposite - 'how', not 'what'. As I said originally, this > is about verification. The fact that the K-map may or may not end up in > silicon is "irrelevant". > > Leon asked whether anyone still used K-maps for programmable logic; a > good question, without being condescending. I don't imagine many people > use them to fill up FPGAs. On the other hand, I'm sure there are still > people in this NG who do digital logic design, and some of them may > occasionally even do non-trivial combinatorial logic. It's been 30 years since I've used Karnaugh maps, they were useful when the 7400 was state of the art and every gate counted. In that era logic was necessarily simple so a tool that could minimize a four input equation was helpful. However as you must have figured out by now, Karnaugh maps don't scale well. When the first widely used programmable logic was introduced, PALs, the Karnaugh maps largely disappeared. PALs had to many terms, 20, for a Karnaugh map to be usable. When FPGAs were introduced they were based on 4 input LUTs. The LUT is universal logic so there is no point in doing any minimization on the scale that Karnaugh maps are useful. What's more modern synthesis tools handle logic minimization on a scale that is simply not possible by a human being. The kinds of optimizations that are still done by hand are also in a class that is outside of the domain of Karnaugh maps, to be specific the kind of things that are done by hand are deciding what terms can be moved to a synchronous set or reset instead of the main equation, or figuring out what portion of an equation can be calculated in an earlier pipeline stage. Those are time optimizations not logic optimizations, i.e. they require knowledge of what's known when and what's nearby and what's far away.Article: 133429
"General Schvantzkopf" <schvantzkopf@yahoo.com> wrote in message
news:y-2dnZJNvsTS8vvVnZ2dnUVZ_sjinZ2d@comcast.com...
> On Sat, 28 Jun 2008 09:00:28 +0100, Evan Lavelle wrote:
>
>> On Sat, 28 Jun 2008 09:00:03 +1200, Jim Granville
>> <no.spam@designtools.maps.co.nz> wrote:
>>
<snip>
> It's been 30 years since I've used Karnaugh maps, they were useful when
> the 7400 was state of the art and every gate counted. In that era logic
> was necessarily simple so a tool that could minimize a four input equation
> was helpful.
All very true, but Evan's question was explicitly targetted toward people
who USE K-maps ("If you use K-maps, which version do you prefer..." from the
original post) and his reasons had to do with verification not design (later
post).
I don't think he was looking for responses from people who don't use K-maps
while they are not doing verification.
KJ
Article: 133430Guys.. I am *brand new* to Aldec Active HDL. What few cpld/pals that I have done have been with CUPL. I've started using ActiveHDL(Student Ver), writing some easy VHDL just to get acquainted with both VHDL and the Aldec tool. What I don't understand is the integrated implementation portion. If I were to want to do a Altera design, for example, do I need to have the Altera toolset installed in order to build the jedec file or does the Aldec tool do that also? I guess I am at a loss at the point between designing/simulating the project and implementation with ActiveHDL. Help me see the light. Thanks, JimArticle: 133431
Hi, In the if-else immediately following your reset of ACC, you assign to ACC again, overriding any previous assignment. Depending on the intended behavior of your circuit you could switch to using variables or reorganize your if's in a way that ACC is assigned only once. Regards, -- Hauke D On Jun 28, 6:57=A0pm, meralonu...@gmail.com wrote: > Xilinx ISE 9.2 and ISE 10.1 > I wanted to design a simple correlator which correlates a 15 bit > sequence with another sequence of 15 bytes (8 bit signed values =3D > Sample below). I needed to zero the summation result after 15 samples, > so I did. But compiler didn't. There is no warning but even the > simulator does not seem to notice ACC <=3D x"000000"; line. I do not see > a reset input for the inferred updown accumulator in the RTL schematic > either. But I see an unconnected D(L:R) input on accumulator. > I see that, from the simulator outputs, Corr<=3DACC; line is synthesized > and working ok, though. > What am I missing. Thanks for help to the beginner. > Additional question (bonus? :-( ) : Waveform editor does not accept > -100 for a 8-bit signed decimal signal but displays -28 instead. When > I enter binary 10011100 which corresponds to -100 and display the > values in decimal it interestingly displays -100. Does it mean -28 > equals to -100 somehow? > > architecture Rec of Rec is > =A0 constant PN : BIT_VECTOR (14 downto 0) :=3D "000100110101111"; > =A0 signal ACC =A0: SIGNED (23 downto 0) :=3D x"000000"; > =A0 signal cntr : integer range 0 to 14 :=3D 0; > begin > =A0 process(clk) begin > =A0 =A0 if(clk'event and clk=3D'1') then > =A0 =A0 =A0 if(cntr=3D0) then > =A0 =A0 =A0 =A0 Corr <=3D ACC; > =A0 =A0 =A0 =A0 ACC <=3D x"000000"; =A0-- Problematic line is this one > =A0 =A0 =A0 end if; > =A0 =A0 =A0 if(PN(cntr)=3D'1') then > =A0 =A0 =A0 =A0 ACC <=3D ACC + Sample; > =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 ACC <=3D ACC - Sample; > =A0 =A0 =A0 end if; > =A0 =A0 =A0 if(cntr=3D14) then > =A0 =A0 =A0 =A0 cntr <=3D 0; > =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 cntr <=3D cntr +1; > =A0 =A0 =A0 end if; > =A0 =A0 end if; > =A0 end process; > end Rec;Article: 133432
<meralonurlu@gmail.com> wrote in message
news:74798b96-6f57-4afd-8b29-2374fd04eb6c@t54g2000hsg.googlegroups.com...
> Xilinx ISE 9.2 and ISE 10.1
> I wanted to design a simple correlator which correlates a 15 bit
> sequence with another sequence of 15 bytes (8 bit signed values =
> Sample below). I needed to zero the summation result after 15 samples,
> so I did. But compiler didn't. There is no warning but even the
> simulator does not seem to notice ACC <= x"000000"; line. I do not see
> a reset input for the inferred updown accumulator in the RTL schematic
> either. But I see an unconnected D(L:R) input on accumulator.
> I see that, from the simulator outputs, Corr<=ACC; line is synthesized
> and working ok, though.
> What am I missing. Thanks for help to the beginner.
> Additional question (bonus? :-( ) : Waveform editor does not accept
> -100 for a 8-bit signed decimal signal but displays -28 instead. When
> I enter binary 10011100 which corresponds to -100 and display the
> values in decimal it interestingly displays -100. Does it mean -28
> equals to -100 somehow?
>
> architecture Rec of Rec is
> constant PN : BIT_VECTOR (14 downto 0) := "000100110101111";
> signal ACC : SIGNED (23 downto 0) := x"000000";
> signal cntr : integer range 0 to 14 := 0;
> begin
> process(clk) begin
> if(clk'event and clk='1') then
> if(cntr=0) then
> Corr <= ACC;
> ACC <= x"000000"; -- Problematic line is this one
> end if;
> if(PN(cntr)='1') then
> ACC <= ACC + Sample;
> else
> ACC <= ACC - Sample;
> end if;
> if(cntr=14) then
> cntr <= 0;
> else
> cntr <= cntr +1;
> end if;
> end if;
> end process;
> end Rec;
The clearing of the ACC will most likely be cancelled by the RN(cntr) = '1'
IF-block. This block should have been made dependend on the first condition:
if(cntr=0) then
Corr <= ACC;
ACC <= x"000000";
elsif(PN(cntr)='1') then
ACC <= ACC + Sample;
else
ACC <= ACC - Sample;
end if;
Regards,
Alvin.
Article: 133433
KJ wrote:
> "General Schvantzkopf" <schvantzkopf@yahoo.com> wrote in message
> news:y-2dnZJNvsTS8vvVnZ2dnUVZ_sjinZ2d@comcast.com...
>
>>On Sat, 28 Jun 2008 09:00:28 +0100, Evan Lavelle wrote:
>>
>>
>>>On Sat, 28 Jun 2008 09:00:03 +1200, Jim Granville
>>><no.spam@designtools.maps.co.nz> wrote:
>>>
>
> <snip>
>
>>It's been 30 years since I've used Karnaugh maps, they were useful when
>>the 7400 was state of the art and every gate counted. In that era logic
>>was necessarily simple so a tool that could minimize a four input equation
>>was helpful.
>
>
> All very true, but Evan's question was explicitly targetted toward people
> who USE K-maps ("If you use K-maps, which version do you prefer..." from the
> original post) and his reasons had to do with verification not design (later
> post).
To answer that question, the Logic minimisation I use, is that built
into the tools, which will include the tools version of K-Maps, and
others as well. ie the REPORT files are closely scrutinised.
It is common to look at the tool output, and recode the source, and
sometimes we have taken one tools output, and pasted into another
as source code.
Sometimes, the choices made within the tools surprises, and sometimes it
disappoints....
Where the tools have a blind spot is in 'node creation' to reduce
total mapped logic (at the expense of some speed). Understandable,
as that is a LOT more variables in the air.
Sometimes the designer has to help there.
It's a matter of matching the degrees of freedom, to the tools IQ.
In Xilinx flows, fastest and smallest switches sometimes seem to work
backwards :)
-jg
Article: 133434Thanks to Alvin A. and Hauke D. I used a variable and it worked. I will surely remember that it is not a C/pascal program but a circuit description.Article: 133435
On Jun 27, 10:09 am, Evan Lavelle <nos...@here.com> wrote: > Is there a 'normal' way to write down K-maps with more than 4 inputs? > > I've just written some code to verify logic which implements n-input > K-maps. The user has to initialise a square or rectangular array with > the function output data, so I did a quick Google search to find out > how people wrote their grids. On the net, at least, it looks like the > reflected binary Gray version is the normal way to do it. It's not > what I was used to, but I assumed that most people would use it. > > Now that I've done it, though, I'm not so sure. For a 5-input > function, for example, a reflected binary Gray map looks like this: > > // /----- A -----\ > // /- B -\ /- B -\ > // --------------- --------------- > // | x | x | x | x | | x | x | x | x | > // |---------------| |---------------| > // | x | x | x | x |\ | x | x | x | x |\ > // --------------- E --------------- E > // / | x | x | x | x |/ / | x | x | x | x |/ > // D |---------------| D |---------------| > // \ | x | x | x | x | \ | x | x | x | x | > // --------------- --------------- > // \- C -/ \- C -/ > > A is the MS input, and E is the LS input. The 8 columns have > left-to-right ABC codings of 000, 001, 0011, and so on. The 4 rows are > coded 00, 01, 11, 10 from top-to-bottom. > > The coding I've used historically is different. It's still Gray-coded, > of course, but it looks like this (actually, I assign A, B, C, D, E > arbitrarily, but I've adjusted it to be mostly consistent with the > reflected version): > > // /----- A -----\ > // /- B -\ /- B -\ > // --------------- --------------- > // | x | x | x | x | | x | x | x | x | > // |---------------| |---------------| > // | x | x | x | x |\ | x | x | x | x |\ > // --------------- E --------------- E > // / | x | x | x | x |/ / | x | x | x | x |/ > // D |---------------| D |---------------| > // \ | x | x | x | x | \ | x | x | x | x | > // --------------- --------------- > // \- C -/ \- C -/ > > The problem with the reflected version is that it's not easy to > (manually) minimise over the 2 grids, because B has moved. In the > second version, you can place the two grids over each other to get > your minterms. The difference is more significant for 6 variables - > it's not obvious how to minimise the first version, but the second > version easily turns into a 3D toroid and you can actually visualise > the groups. Note that I'm not talking about machine minimisation - > this is just how a human would write and visualise a 5- or 6-input > map, and how they'd want to write down the function output data. > > If you use K-maps, which version do you prefer for 5- and 6-input > functions? I clearly have to use the reflected version for more than 6 > inputs; it's only 5 and 6 which are problems. > > Thanks - > > Evan Evan, In John F. Wakerly's "Digital Design, Principles and Practices", 4th Edition, pgs 235-236,564 (there is also a 5th edition) uses your second version (the historical one) of 5/6-variable map for logic minimization exercises and FSM synthesis. Of course, mathematically, either one works. alanArticle: 133436
On Jun 27, 2:19 am, jay <heavenf...@gmail.com> wrote: > On 6=D4=C227=C8=D5, =CF=C2=CE=E71=CA=B152=B7=D6, Jim Granville <no.s...@d= esigntools.maps.co.nz> > wrote: > > > > > jay wrote: > > > Hi all, > > > > For the ram implied in a CPLD design, will the data written in it > > > remain after power off? > > > > I have a small rom in my curent CPLD design, occasionally I need > > > change the content inside, instead of reprogramming it, I want > > > something like a nvram that I can update through the uP dynamicallly. > > > That depends on the CPLD. > > Some do have a mode, where you can load the CPLD config > > latches and not the NV_Fuse_memory. > > (I think Atmel ATF15xxBE series have the twin modes) > > > not sure of the details, ie when the change-over occurs > > and what the pins do during re-load > > > -jg > > Thanks, but I'm only using a general CPLD from A. > > Jay If you can't switch the CPLD for another PLD, I'm afraid you'll have to reprogram the device as a whole to do this. If you are open to change though, in Lattice XP2 FPGA (which are flash based -so system- wise they're very close to big CPLDs) there is a relatively small flash memory (TAG memory) with an external (and internal) SPI interface. The TAG memory can be reprogrammed while these device are operating. AlexArticle: 133437
Hi, I am using an EDK-generated PPC subsystem on a ML403. I wonder if it would be complicated to create a peripheral that has high speed master access to the SDRAM. I would like to build a shared memory frame buffer. Or are there any other good ways to achieve my goal? I don't want to use the onboard SRAM. And block ram is too rare and not enough.. Regards, Philipp :-)Article: 133438
"Tom" <tom.derham@gmail.com> wrote in message news:f656be07-d2be-4844-9c96-3feec6b44be6@y22g2000prd.googlegroups.com... On Jun 28, 2:08 am, Heinrich <Heinr...@myweb.com> wrote: > they have both the same clock Frequency but the phase doesnt > matter as it is just some serial databits that need to be forwarded > between them. So if the relative phase isn't known, how does the receiving FPGA know #when# to read each data bit from the transmitting FPGA? More specifically, what happens if the receiving FPGA decides to read the value at its input pin just at the very same moment that it is being changed by the transmitting FPGA? (note: this is not good). ======= Single ended serial clock and data lines fit the description and would have little difficulty. Also, RS232 serial works reasonably well without an explicit clock. The trick there is the serial clock is at least 16x slower than the device clock. You do your own timing, in other words, or bring it with you.Article: 133439
On Jun 29, 12:56=A0pm, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > Single ended serial clock and data lines fit the description and would ha= ve > little difficulty. Also, RS232 serial works reasonably well without an > explicit clock. The trick there is the serial clock is at least 16x slowe= r > than the device clock. You do your own timing, in other words, or bring i= t > with you. Sure, as I mentioned before, if the clock can be extracted or implied from the data stream then no problem. In the case of RS232, as you say, it resynchronizes to the start bit for every byte and uses the 16x faster clock to estimate the best sample point for each bit. Since the OP didn't mention the nature of the data connection, I wanted to confirm that he was properly aware of the issues. -T From webmaster@nillakaes.de Sun Jun 29 11:30:30 2008 Path: flpi142.ffdc.sbc.com!flpi088.ffdc.sbc.com!prodigy.com!flpi089.ffdc.sbc.com!prodigy.net!newsfeed2.telusplanet.net!newsfeed.telus.net!feeder.erje.net!newsfeeder.dynfx.net!weretis.net!feed.cnntp.org!news.cnntp.org!not-for-mail Message-Id: <4867d4d0$0$25951$6e1ede2f@read.cnntp.org> From: Thorsten Kiefer <webmaster@nillakaes.de> Subject: arithmetic problem Newsgroups: comp.arch.fpga Date: Sun, 29 Jun 2008 20:30:30 +0200 User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 19 Organization: CNNTP NNTP-Posting-Host: 7dcef54f.read.cnntp.org X-Trace: DXC=JMb11?oJ5YDIJdhVWPK]ABWoT\PAgXa?A3QObBb3c?JMCWCf629N19DhldKiGb`JFM8mohc21mJIIEZe[JF^52kG X-Complaints-To: abuse@cnntp.org Xref: prodigy.net comp.arch.fpga:146029 X-Received-Date: Sun, 29 Jun 2008 14:30:43 EDT (flpi142.ffdc.sbc.com) Hi, the following code : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; ... rnext.addr <= std_logic_vector(unsigned(rreg.addr) + 1); ... yields the following error : Line 140. Expression in type conversion to std_logic_vector has 3 possible definitions in this scope, for example, UNSIGNED and UNSIGNED. What can I do ? Regards ThorstenArticle: 133440
On Jun 28, 10:03=A0pm, Tom <tom.der...@gmail.com> wrote: > On Jun 29, 12:56=A0pm, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > > > Single ended serial clock and data lines fit the description and would h= ave > > little difficulty. Also, RS232 serial works reasonably well without an > > explicit clock. The trick there is the serial clock is at least 16x slow= er > > than the device clock. You do your own timing, in other words, or bring = it > > with you. > > Sure, as I mentioned before, if the clock can be extracted or implied > from the data stream then no problem. In the case of RS232, as you > say, it resynchronizes to the start bit for every byte and uses the > 16x faster clock to estimate the best sample point for each bit. > > Since the OP didn't mention the nature of the data connection, I > wanted to confirm that he was properly aware of the issues. > > -T Was this the dumbest thread ever? Maybe we should just stop answering when the OP refuses to give a coherent answer. Peter AlfkeArticle: 133441
> I am using an EDK-generated PPC subsystem on a ML403. > I wonder if it would be complicated to create a peripheral that has high > speed master access to the SDRAM. I would like to build a shared > memory frame buffer. Or are there any other good ways to achieve my > goal? I don't want to use the onboard SRAM. And block ram is too rare > and not enough.. If you are using a mch sdram controller you can make your peripheral into a MCH initiator, connect it to the memory controller, and use this simple protocol for your DMA. It is simpler and more efficient than OPB DMA.Article: 133442
Hello All, A new version beta 0.85 is now available. The following changes and additions have occurred. 1 Quickly add previously used Delays and Constraints from pop-up menu 2 The current state is inverted automatically when adding new pulse if the newstate in the toolbar is the same as the current state in the signal. 3 Keystroke shortcuts for all the signal state buttons in toolbar. Hover over button to see keystrokes. 4 Signals can now use text values for next state. This is useful when labels are needed in digital signals. 5 Moving text and edges by mouse drags now use undo and redo 6 Should work with JRE1.5 or newer You can download the Free Edition now and read all about the TimingAnalyzer at: www.timing-diagrams.comArticle: 133443
I created a simple Verilog-2001 test-module: `default_nettype none module top #( parameter integer D_W = 16 ) ( input wire sel, input wire signed [D_W-1:0] ina, inb, output wire signed [D_W:0] out ); assign out = sel ? (ina - inb ) : (ina + inb); endmodule // : top `default_nettype wire ------------------------------------------------ When I ran this module through Xilinx Webpack 10.1, it synthesized as a "addsub" macro. I.e., I tested another module which performs addition-only, and both modules occupied the same amount of LUT. Furthermore, the Xilinx synthesis report even tells me : | "Synthesizing Unit <top>. | Related source file is "top.v". | Found 17-bit addsub for signal <out>. | Summary: | inferred 1 Adder/Subtractor(s). | Unit <top> synthesized. | | INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing." ------------------------------------------------ But I tried the same top.v module in Altera Quartus-II. I manually turned ON 'auto resource sharing' inside the Project Analsyis settings. When I synthesize to (Cyclone-II 2C20), Quartus-II creates an adder unit, plus a bunch of separate muxes in front of port 'inb.' I've found that the LUT consumption is TWICE the amount (34 vs 17) as a straight adder-only. | Resource Usage (my "addsub") | Estimated Total logic elements 34 | | Total combinational functions 34 | Logic element usage by number of LUT inputs | -- 4 input functions 0 | -- 3 input functions 16 | -- <=2 input functions 18 // <== for the MUX2! | | Logic elements by mode | -- normal mode 17 | -- arithmetic mode 17 | | Total registers 0 | -- Dedicated logic registers 0 | -- I/O registers 0 | | I/O pins 50 | Maximum fan-out node sel | Maximum fan-out 17 | Total fan-out 101 | Average fan-out 1.20 Am I doing something wrong? I expected the Altera-FPGAs to support addsub-selection at the hardware-level. Instead, it looks like it's wasting a bunch of LUTs to implement a non-fused MUX21 in front of every inb[] bit. Is this a device-limitation, or is the synthesis-tool issue? (Time to revert to AHDL, heh?)Article: 133444
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On Jun 29, 5:54 pm, timinganalyzer <timinganaly...@gmail.com> wrote:
> Hello All,
>
> A new version beta 0.85 is now available. The following changes and
> additions have occurred.
>
> 1 Quickly add previously used Delays and Constraints from pop-up menu
> 2 The current state is inverted automatically when adding new pulse if
> the newstate in the
> toolbar is the same as the current state in the signal.
> 3 Keystroke shortcuts for all the signal state buttons in toolbar.
> Hover over button to see keystrokes.
> 4 Signals can now use text values for next state. This is useful when
> labels are needed in digital signals.
> 5 Moving text and edges by mouse drags now use undo and redo
> 6 Should work with JRE1.5 or newer
>
> You can download the Free Edition now and read all about the
> TimingAnalyzer at:
>
> www.timing-diagrams.com
Hi,
I tried to install it on Vista Basic.But facing difficulty in
installing.I did install the JRE.when I run the timinganalyzer.jar exe
file It pops me a message saying main class not found exiting !!
Could u pls help me in fixing the problem ...ur help will be
appreciated
Thanks in advance,
hesh
Article: 133447Hai, Can i implement FIR filter in FPGA using fixed point number.. I referred various FIR filter implementation in FPGA all have used integer coefficients for their implementation and i am interested to know the difficulties of using fixed point numbers.I knew fixed point numbers utilize more hardware. I understand fixed point number is scaled and rounded to get integer values from various tools(FDAtool) hence some information will lost..Ultimately this will alter the filter response(cutoff,passband,stopband) am i correct? if it is possible to implement in fixed point can anyone compare the accuracy of integer FIR implementation and fixed point implementation? pls clarify .. regards, rajArticle: 133448
On Sun, 29 Jun 2008 20:30:30 +0200, Thorsten Kiefer wrote:
>library IEEE;
>use IEEE.STD_LOGIC_1164.ALL;
>use IEEE.numeric_std.ALL;
>...
>rnext.addr <= std_logic_vector(unsigned(rreg.addr) + 1);
>...
>
>yields the following error :
>Line 140. Expression in type conversion to std_logic_vector has 3 possible
>definitions in this scope, for example, UNSIGNED and UNSIGNED.
>
>What can I do ?
1) Make absolutely sure that you don't have
use ieee.std_logic_arith
or
use ieee.std_logic_[un]signed
in the context clauses.
2) Just as an experiment (I'm not recommending this for real code)
try
rnext.addr <= std_logic_vector(
unsigned'(unsigned(rreg.addr) + 1)
);
3) Try a different compiler to see if you get a more informative
diagnostic.
In isolation, your original code is OK (assuming the
record fields rreg.addr and rnext.addr are both
std_logic_vectors of the same width).
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 133449> Hi, > I tried to install it on Vista Basic.But facing difficulty in > installing.I did install the JRE.when I run the timinganalyzer.jar exe > file It pops me a message saying main class not found exiting !! > Could u pls help me in fixing the problem ...ur help will be > appreciated > Thanks in advance, > hesh I had this when trying a previous release with a version of the JRE that was to old. Dan say's he's changed things so it should work with JRE1.5 or later, it might be worth trying with JRE1.6? Dan? Nial
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