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On Wed, 23 Jul 2008, Robert F. Jarnot wrote: |-------------------------------------------------------------------------------| |"[..] | | | |[..] The | |transputer linker had the same issues you allude with yours -- the linker would| |sometimes have to make many 10's, or even a few hundred passes (for a large | |program) to make all of the variable length prefix instructions as short as | |possible." | |-------------------------------------------------------------------------------| Yikes. |-------------------------------------------------------------------------------| |" That is probably one of the reasons that the successor to the | |transputer from www.xmos.com looks much more like a modern register-based | |architecture with a lot of other clever transputer features retained or | |extended. [..]" | |-------------------------------------------------------------------------------| So do the linkers for XMOS devices use only a few passes? Are radhard versions of XMOS devices available? With best regards from Portugal, Paul ColinArticle: 134076
On 23 Jul, 13:46, Vagant <vladimir.v.koroste...@rambler.ru> wrote: > Hi All > > I know that there are good google groups devoted to fpga and vhdl > design but struggle to find anything about digital systems design. I > actually look for a forum or a discussion group where people of > different levels (professionals and beginners as well) help to learn > how to design digital systems and would be grateful for advice. Thank > you. :) edaboard.com?Article: 134077
> >** Is there any way i can rise the spi clock while >keeping the sd connector "off board"? ** > Try terminating the signals appropriately. For instance, series terminations on the CS, SCK and MOSI lines at the master. And before you ask, the value depends on the characteristic impedance of the cable...Article: 134078
On Jul 23, 11:44 am, Mike Treseler <mtrese...@gmail.com> wrote: > ghelbig wrote: > > I haven't entered pin numbers manually in years. Too easy to make > > mistakes, especially with pin counts in the K range. > > I have one PERL script that parses a wirelist into a spreadsheet, and > > another that turns the spreadsheet into a constraint file. > > And Quartus supports Tcl scripts for pin number entry, that method > > works "just fine" too. > > That makes good sense for pin numbers. > But direction should be inferred from the code, > and IO type and timing is a separate problem. > > -- Mike Treseler That's why I run it through the spread sheet; I set the I/O type there. Getting direction from the top level would be a good addition. Timing is always a problem... :) G.Article: 134079
I have successfully compiled a design in Quartus 2 . Now I use the EDA netlistwriter to generate an FPGA Xchange File. and i get the following errors Error: EDA Netlist Writer failed to generate FPGA Xchange file Error: Error(s) found while running EDA Netlist Writer But there are no messages to tell why these errors occured? Has anyone faced this issue before? Am i overlooking something trivial? By the way i could generate a .fx file for another design. But it does not seem to work for the current design. ThanksArticle: 134080
On Jul 24, 10:54=A0am, ghelbig <ghel...@lycos.com> wrote: > On Jul 23, 11:44 am, Mike Treseler <mtrese...@gmail.com> wrote: > > > ghelbig wrote: > > > I haven't entered pin numbers manually in years. =A0Too easy to make > > > mistakes, especially with pin counts in the K range. > > > I have one PERL script that parses a wirelist into a spreadsheet, and > > > another that turns the spreadsheet into a constraint file. > > > And Quartus supports Tcl scripts for pin number entry, that method > > > works "just fine" too. > > > That makes good sense for pin numbers. > > But direction should be inferred from the code, > > and IO type and timing is a separate problem. > > > =A0 =A0 =A0 =A0-- Mike Treseler > > That's why I run it through the spread sheet; I set the I/O type > there. =A0Getting direction from the top level would be a good addition. > > Timing is always a problem... :) > I use the spreadsheet as basically the 'master' data set and put all I/ O information there. I have columns in there for... 1. The basics: signal name, direction, pin number, setup, hold, clock- to-output, propogation delay requirements. 2. Device specific options: I/O drive strength, slew rate, termination, I/O voltage standard, fast input/output registers (and any other properties that belong with a signal I/O). Each of the things in #1 and #2 get a column in the spreadsheet. Each signal gets a row. Various pages in that spreadsheet workbook produce the following design artifacts that are then simply copy/pasted into the appropriate tool. The formulas on those pages produce text in the format required by the tool (i.e. valid VHDL or TCL). - Design top level port map (can be pasted into the VHDL file). - Port map with the connections to the testbench instantiation of the design. - TCL script to load into the synthesis tool to set all of the properties. Since it's in a spreadsheet I can use formulas so that changes in one area get reflected in all of the appropriate places. Particularly when it comes to calculating timing requirements this is useful because you can have a completely different workbook page that defines the clocks involved, DLL/PLL clock multiplier/divider values, setup/ hold requirements of the devices that the design will be talking to. Deriving the timing requirements for the new design in this manner, makes it a lot clearer to follow (and find calculation errors) than if the calculations are done 'somewhere else' and only the end result value is pasted into the tool. In effect the spreadsheet is the master source of the information and also directly produces design artifacts that are then copied into other tools...and I suppose if there is a way to output the values in the pages of a spreadsheet into separate files then the manual copy/ paste operation could be eliminated. KJArticle: 134081
On Jul 24, 8:22=A0am, KJ <kkjenni...@sbcglobal.net> wrote: <snip> > In effect the spreadsheet is the master source of the information and > also directly produces design artifacts that are then copied into > other tools...and I suppose if there is a way to output the values in > the pages of a spreadsheet into separate files then the manual copy/ > paste operation could be eliminated. > > KJ OpenOffice has a scripting language that you could use to produce the files from your spreadsheet. I have used it so that I could have my Make files call OpenOffice and have it create pdfs of our documentation and put them where they belong when we make our EDK distribution. There is an active forum for OpenOffice at http://www.oooforum.org/ I received lots of help there when I was trying to get my project working. Regards, John McCaskill www.FasterTechnology.comArticle: 134082
On Jul 24, 11:55=A0am, John McCaskill <jhmccask...@gmail.com> wrote: > On Jul 24, 8:22=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > > <snip> > > > In effect the spreadsheet is the master source of the information and > > also directly produces design artifacts that are then copied into > > other tools...and I suppose if there is a way to output the values in > > the pages of a spreadsheet into separate files then the manual copy/ > > paste operation could be eliminated. > > > KJ > > OpenOffice has a scripting language that you could use to produce the > files from your spreadsheet. =A0I have used it so that I could have my > Make files call OpenOffice and have it create pdfs of our > documentation and put them where they belong when we make our EDK > distribution. > > There is an active forum for OpenOffice athttp://www.oooforum.org/ > I received lots of help there when I was trying to get my project > working. > > Regards, > > John McCaskillwww.FasterTechnology.com Thanks for the tip KJArticle: 134083
On 23 Jul., 07:54, wojtek <wojtekpowiertow...@gmail.com> wrote: > I'am always open for new ideas how to code certain things, but for now > I will probably stick with my code (since I've written small software > to automatically generate VHDL for certain input/output frequencies), > in future I will probably switch to Verilog and update files on my > page with Verilog files instead of VHDL. But such suggestions are > always helpful and welcome :) > > Regards > snip hi, The point wasn't that you should change to verilog or make a lot of changes, just that the minor change of making the phase accumulator produce a clock enable and running everything on the same clock would make it a lot easier to integrate in a design, because it would avoid an extra clock domain and all the potential problems with that. -LasseArticle: 134084
Hi, I am unable to generate multiple clocks using the PLL along with the signal tap analyzer in simulink when I am targetting a particular board. It throws an error saying that "Multiple clock domains cannot be supported when you target a particular board". I am unable to understand how do I debug my design if I cannot use signal tap knowing the fact that I would surely need to use multiple clocks in my design.Article: 134085
KJ wrote:
> In effect the spreadsheet is the master source of the information and
> also directly produces design artifacts that are then copied into
> other tools
Sounds good.
You and G. have convinced me to try this next time.
...and I suppose if there is a way to output the values in
> the pages of a spreadsheet into separate files then the manual copy/
> paste operation could be eliminated.
copy/paste is fine with me.
I don't do this often enough
to justify debugging a full automation.
Consider publishing an example .xls with just a few rows.
-- Mike Treseler
Article: 134086On Jul 24, 2:44 am, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote: > Hi, > > You don't need the FSL_bus. > You can directly take the MicroBlaze signals FSL0_M_Data, FSL0_M_Full, > FSL0_M_Write and connect them to your module. > If you want to do this in EDK, you will need to create a pcore for your > module and manually connect these signal in XPS. > You can also make these signal external to the EDK project and connect th= em > in Project Navigator. > It's depend on how your design look now. > > G=F6ran > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > news:0b840fac-04c0-41a6-8ca1-99593fe48018@l64g2000hse.googlegroups.com... > On Jul 23, 3:26 pm, "Ray D." <ray.delvecc...@gmail.com> wrote: > > > > > On Jul 22, 2:34 am, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote: > > > > Hi, > > > > Then it should be a direct match for the FSL interface. > > > If MicroBlaze executes a 'put' instruction , it will not write until = the > > > FSL_M_Full flag is '0' and when it write it will set the FSL_M Write > > > high > > > for one clock cycle. > > > MicroBlaze have plenty of options for the FSL instructions, you can g= et > > > all > > > about them in the reference manual. > > > > G=F6ran > > > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > > >news:693f947e-929e-49f6-939d-d834e0048121@27g2000hsf.googlegroups.com.= .. > > > On Jul 21, 2:36 am, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote: > > > > > Hi, > > > > > Depending a little on how your busy signals work, you might just ho= ok > > > > up > > > > your module to the FSL interface on MicroBlaze. > > > > Your busy signal needs be high when it can't accept a new word even > > > > when > > > > there is no attempt to write to the module. > > > > MicroBlaze will also just do one cycle write so your module needs t= o > > > > accept > > > > a new word in one clock cycle when busy is low. > > > > > Connect: > > > > din(7 downto 0) -> FSL0_M_Data(24 to 31) > > > > din_ready -> FSL0_M_Write > > > > busy -> FSL0_M_Full > > > > > You need to enable FSL Interfaces to MicroBlaze with the parameter > > > > C_FSL_LINKS (set it to 1) > > > > You can write to the fsl interface with the function putfslx, you c= an > > > > read > > > > more about this function in the document "OS and Libraries Document > > > > Collection". > > > > > G=F6ran > > > > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > > > >news:276dce6d-c9ed-4937-95ea-e3c86ff3656a@d45g2000hsc.googlegroups.c= om... > > > > > > Hey all, > > > > > > I have a Xilinx Spartan-3E starter board, and I'm implementing a > > > > > MicroBlaze processor on the FPGA. I would also like to use the L= CD > > > > > which is on board, and I have already developed a hardware module > > > > > that > > > > > takes care of initialization and printing to the LCD. The interf= ace > > > > > is shown below: > > > > > > entity LCD_top is > > > > > Port ( > > > > > clk : in STD_LOGIC; > > > > > reset : in STD_LOGIC; > > > > > > din : in STD_LOGIC_VECTOR (7 downto 0); > > > > > din_ready : in STD_LOGIC; > > > > > busy : out STD_LOGIC; > > > > > > LCD_D : out STD_LOGIC_VECTOR (11 downto 8); > > > > > LCD_E : out STD_LOGIC; > > > > > LCD_RS : out STD_LOGIC; > > > > > LCD_RW : out STD_LOGIC > > > > > > ); > > > > > end LCD_top; > > > > > > I really would like to instantiate this module along with the > > > > > processor core. My question is this - how would I go about > > > > > interfacing this with the MicroBlaze processor internal to the FP= GA? > > > > > What I would like to do is define a GPIO port on the processor to > > > > > connect to the din, din_ready and busy lines of the LCD module, b= ut > > > > > I > > > > > keep getting the following error: > > > > > > ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO > > > > > CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD > > > > > \system.mhs line 150 > > > > > - connection is not connected to an external port! > > > > > MPD subproperties IOB_STATE=3DBUF|REG or THREE_STATE=3DTRUE req= uire > > > > > that the port > > > > > be connected directly to an external port. > > > > > > Is there any way to work around this? I realize I could just > > > > > connect > > > > > the LCD to the GPIO directly and write software drivers, but I'm > > > > > trying to avoid that because I already have the hardware module i= n > > > > > place and working smoothly. It will also be nice to have this > > > > > separate module so that it does the work of printing to the LCD, = and > > > > > the processor itself can stay busy with other more important jobs= . > > > > > > Also, is there an easier way to add another hardware module witho= ut > > > > > manually editing the generated VHDL files for the core? I'm not > > > > > sure > > > > > if you can do that within Platform Studio. > > > > > > Any advice would be much appreciated, thanks! > > > > > > Ray > > > > That is how the module works so I'll have to try some of these > > > options! The busy signal is set high the entire time data is being > > > written to the LCD. Originally I had a module "program.vhd" that > > > controlled the LCD module along with a keyboard module that we we had > > > in place for user input. Within program.vhd, I implement a state > > > machine and check if the busy signal is high before writing to the > > > LCD. If busy =3D 0, then I set din_ready high and set the 8-bits of > > > data. This is buffered within the LCD module and you only need to > > > hold din_ready for a single cycle to write to the LCD. The LCD is > > > connected over a 4-bit interface to the FPGA and this is taken care o= f > > > within the LCD module. When the writing operation begins busy is set > > > to '1' until complete. > > > > Ray > > > OK - I'm new to using the EDK and am having trouble implementing this > > with the FSL bus. I have a few questions: > > > 1) When I create a custom peripheral, it generates an HDL wrapper - Do > > I simply edit this wrapper by instantiating my LCD_top module as a > > component within the top level design? > > > 2) Should I check the box "Generate template driver files to help you > > implement software interface", or will the provided functions to read > > and write to the FSL bus suffice? > > > 3) Do you know of any good tutorials on how to implement a custom > > peripheral on the FSL bus? I've come across a few for adding > > peripherals to the other buses, but most that I have found do not > > follow through with how to edit the VHDL files and correctly add the > > peripheral to the system in Platform Studio (they simply tell you go > > to 'Create/Import Custom Peripheral'). > > > Any help/input is appreciated, thanks! > > > Ray > > Two more things - > > 1) the four output ports of the LCD module must be connected to the > external FPGA pins in order to drive the LCD. What is the best way to > go about doing this? Is this something that can be edited within > Platform Studio or do I need to manually edit VHDL/UCF files? I'm > assuming I will have to add the outputs to the interface shown below. > > 2) When I choose the master interface for the FSL bus, the ports are > defined as follows: > > -- DO NOT EDIT BELOW THIS LINE --------------------- > -- Bus protocol ports, do not add or delete. > FSL_Clk : in std_logic; > FSL_Rst : in std_logic; > FSL_S_Clk : out std_logic; > FSL_S_Read : out std_logic; > FSL_S_Data : in std_logic_vector(0 to 31); > FSL_S_Control : in std_logic; > FSL_S_Exists : in std_logic; > FSL_M_Clk : out std_logic; > FSL_M_Write : out std_logic; > FSL_M_Data : out std_logic_vector(0 to 31); > FSL_M_Control : out std_logic; > FSL_M_Full : in std_logic > -- DO NOT EDIT ABOVE THIS LINE --------------------- > > You mention that my din(7 downto 0) port should be connected to the > FSL_M_Data port, but the former is an input while the latter is an > output. Am I missing something? I tried to define this as a slave > interface, but that also yields an error when I try to generate the > bitstream. > > Thanks. I think I understand what you are saying, but I'm still unsure of how to implement it. I went through the 'Create and Import Peripheral' wizard to create the pcore and HDL wrapper file, but when you go through this it asks which bus you wish to attach the peripheral to - this generated HDL file is an interface file for the FSL bus, correct? I assumed I needed to edit this file and place my LCD module within this interface file (with the interface shown in my previous message). Do I need to go through this wizard to directly connect to the FSL interface or is this the incorrect method? When you say directly take the MicroBlaze signal and connect them to my module, do you mean edit the aforementioned wrapper file for the pcore, or is there an alternative way? Is there a top level VHD file that I need to edit in order to port the LCD module output to the external FPGA pins? I realize these probably are simple questions but since I've never been through this process within the EDK (and can't find any good tutorials - most deal with adding peripheral to OPB or PLB bus), I'm having a hard time figuring out which steps I need to take in order to accomplish what you have suggested. Anyway, I really do appreciate all your help so far. Thank you! RayArticle: 134087
On Jul 24, 4:45 am, woj...@gmail.com wrote: > I have j-link jtag from iar system, its supplied by 5VDC from USB. Im > wondernig if it would be possible to use it (with some modification) > to program xinlix devices ? Probably with enough mucking around with the voltage levels, learning to talk to it's usb interface, and patching that into an open source programming tool like xc3sprog, but is it worth the effort other than as a learning project? You can buy a jtag cable for $12 (parallel port) or $37 (usb) from www.digilentinc.com that comes with software for programming common xilinx devices.Article: 134088
"RCIngham" <robert.ingham@gmail.com> ha scritto nel messaggio news:GemdnXcN7tHaHxXVRVn_vwA@giganews.com... > > >>** Is there any way i can rise the spi clock while >>keeping the sd connector "off board"? ** >> > > Try terminating the signals appropriately. For instance, series > terminations on the CS, SCK and MOSI lines at the master. > > And before you ask, the value depends on the characteristic impedance of > the cable... > Before deciding to go on with a lower clock, i tried a parallel termination. I tried a single resistor close to the receiver's SCK line. It didn't help. Now reading again something about Digital Signal Integrity i noticed that if the parallel resistor is not really close to the receiver it cannot work because there ia a part of impedance left unmatched. Series termination should not pose this issue, so i hope they would do. Anyway i remember i read somewhere that the highest termination value is about 330 ohm, as a rule of thumb... perhaps. I think it's not possible though, to calculate the real impedance, since the signal path is broken into: fpga board, cable, breadboard, the small sd card board.Article: 134089
rickman wrote: > That is over three times the size of my CPU I wrote: > Which one is your CPU? Is it open source? rickman wrote: > Mine was done some 6 or 7 years ago for a simple application and I > never released it. I have called it "Bonus" for no special reason. > If I decide to open source it I will try to come up with a better > name. I was just inquiring because it sounded like your design might be particularly space-efficient. > We seem to have quantity, but quality only in a few. True.Article: 134090
Hi, has anybody used the FFT v4.1 core from Xilinx Core generator before to do IFFT? This is the scenario: - I am using this config of the FFT core with the selected configurations -pipelined, streaming -unscaled. input wave is 24 bits. output is 34 bits. coefficients also 24 bits input 1) I use matlab to generate 24 bit complex waveform and save it into text file 2) I run my testbench in modelsim (simulation). the testbench reads in the text file of complex waveforms generated in (1). It is then fed through the xilinx core generated FFT. This generates an FFT result. (I have verified this output in matlab. It seems to be working fine.) 3) the FFT result is fed into another instantation of the same core. this time, the core is configured to do IFFT by clearing the fwd_inv signal (. Also, because the FFT core accepts a maximum input bus width of 24 bits, I truncate the output from previous FFT from 34 bits to 24 bits before feeding into the IFFT core. 4) in theory, the normalised input and output waveform results should be the same. I see some alarming results. a) the output of the IFFT shows the first 7 samples of constant value. This will result in some kind of phase shift. The output of the simulation is piped into a text file. I read it into matlab and do my analysis. In addition, viewing of the complex output waveform in modelsim waveform viewer in analog step also confirms this. :( Huh? Is that normal? Have i missed out something here? If not, isnt it appalling? dun xilinx test their IP cores before releasing them? Ridiculous right? ChrisArticle: 134091
On Jul 25, 9:49=A0am, chrisde...@gmail.com wrote: > 2) I run my testbench in modelsim (simulation). the testbench reads in > the text file of complex waveforms generated in (1). It is then fed > through the xilinx core generated FFT. This generates an FFT result. > (I have verified this output in matlab. It seems to be working fine.) Are you sure that you have got the correct timing between the first input data word and the other FFT core control inputs? For example, you have to assert the Start input a few cycles before you put the first data word on the input data bus of the core. Have a careful look at the timing diagram for pipelined streaming mode in the Xilinx FFT data sheet to make sure you have the timing correct in your simulation. I have used this core in almost the same configuration you describe with no problems. -TArticle: 134092
Hi, A pcore in EDK contains the HDL files and a set of data files. All files are in ASCII format. The hdl files is in pcores/<your module>_vX_XX_a/hdl/vhdl The data files is in pcores/<your module>_vX_XX_a/data There are two data files that you need. First the .pao file which contains a the list of HDL files that your module need. It can contain reference to other pcores libraries if needed The second is the .mpd files which contains all information XPS needs. It contains: type of core, what bus interfaces exists, which parameters/generics, signals,.. There is a document in the installation describing these files, the data files is called PSF files. When you use "Create and Import Peripheral" it creates the data files for you. You can also look in existing pcores to see what they contains. The fit_timer in EDK is very simple and should give you a hint how to create a pcore for your LCD module. You don't need any bus interfaces, just pure signals. Göran "Ray D." <ray.delvecchio@gmail.com> wrote in message news:61bf0515-e8b9-44fb-9e8f-268ca7ed6bca@i24g2000prf.googlegroups.com... On Jul 24, 2:44 am, "Göran Bilski" <goran.bil...@xilinx.com> wrote: > Hi, > > You don't need the FSL_bus. > You can directly take the MicroBlaze signals FSL0_M_Data, FSL0_M_Full, > FSL0_M_Write and connect them to your module. > If you want to do this in EDK, you will need to create a pcore for your > module and manually connect these signal in XPS. > You can also make these signal external to the EDK project and connect > them > in Project Navigator. > It's depend on how your design look now. > > Göran > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > news:0b840fac-04c0-41a6-8ca1-99593fe48018@l64g2000hse.googlegroups.com... > On Jul 23, 3:26 pm, "Ray D." <ray.delvecc...@gmail.com> wrote: > > > > > On Jul 22, 2:34 am, "Göran Bilski" <goran.bil...@xilinx.com> wrote: > > > > Hi, > > > > Then it should be a direct match for the FSL interface. > > > If MicroBlaze executes a 'put' instruction , it will not write until > > > the > > > FSL_M_Full flag is '0' and when it write it will set the FSL_M Write > > > high > > > for one clock cycle. > > > MicroBlaze have plenty of options for the FSL instructions, you can > > > get > > > all > > > about them in the reference manual. > > > > Göran > > > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > > >news:693f947e-929e-49f6-939d-d834e0048121@27g2000hsf.googlegroups.com... > > > On Jul 21, 2:36 am, "Göran Bilski" <goran.bil...@xilinx.com> wrote: > > > > > Hi, > > > > > Depending a little on how your busy signals work, you might just > > > > hook > > > > up > > > > your module to the FSL interface on MicroBlaze. > > > > Your busy signal needs be high when it can't accept a new word even > > > > when > > > > there is no attempt to write to the module. > > > > MicroBlaze will also just do one cycle write so your module needs to > > > > accept > > > > a new word in one clock cycle when busy is low. > > > > > Connect: > > > > din(7 downto 0) -> FSL0_M_Data(24 to 31) > > > > din_ready -> FSL0_M_Write > > > > busy -> FSL0_M_Full > > > > > You need to enable FSL Interfaces to MicroBlaze with the parameter > > > > C_FSL_LINKS (set it to 1) > > > > You can write to the fsl interface with the function putfslx, you > > > > can > > > > read > > > > more about this function in the document "OS and Libraries Document > > > > Collection". > > > > > Göran > > > > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > > > >news:276dce6d-c9ed-4937-95ea-e3c86ff3656a@d45g2000hsc.googlegroups.com... > > > > > > Hey all, > > > > > > I have a Xilinx Spartan-3E starter board, and I'm implementing a > > > > > MicroBlaze processor on the FPGA. I would also like to use the > > > > > LCD > > > > > which is on board, and I have already developed a hardware module > > > > > that > > > > > takes care of initialization and printing to the LCD. The > > > > > interface > > > > > is shown below: > > > > > > entity LCD_top is > > > > > Port ( > > > > > clk : in STD_LOGIC; > > > > > reset : in STD_LOGIC; > > > > > > din : in STD_LOGIC_VECTOR (7 downto 0); > > > > > din_ready : in STD_LOGIC; > > > > > busy : out STD_LOGIC; > > > > > > LCD_D : out STD_LOGIC_VECTOR (11 downto 8); > > > > > LCD_E : out STD_LOGIC; > > > > > LCD_RS : out STD_LOGIC; > > > > > LCD_RW : out STD_LOGIC > > > > > > ); > > > > > end LCD_top; > > > > > > I really would like to instantiate this module along with the > > > > > processor core. My question is this - how would I go about > > > > > interfacing this with the MicroBlaze processor internal to the > > > > > FPGA? > > > > > What I would like to do is define a GPIO port on the processor to > > > > > connect to the din, din_ready and busy lines of the LCD module, > > > > > but > > > > > I > > > > > keep getting the following error: > > > > > > ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO > > > > > CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD > > > > > \system.mhs line 150 > > > > > - connection is not connected to an external port! > > > > > MPD subproperties IOB_STATE=BUF|REG or THREE_STATE=TRUE require > > > > > that the port > > > > > be connected directly to an external port. > > > > > > Is there any way to work around this? I realize I could just > > > > > connect > > > > > the LCD to the GPIO directly and write software drivers, but I'm > > > > > trying to avoid that because I already have the hardware module in > > > > > place and working smoothly. It will also be nice to have this > > > > > separate module so that it does the work of printing to the LCD, > > > > > and > > > > > the processor itself can stay busy with other more important jobs. > > > > > > Also, is there an easier way to add another hardware module > > > > > without > > > > > manually editing the generated VHDL files for the core? I'm not > > > > > sure > > > > > if you can do that within Platform Studio. > > > > > > Any advice would be much appreciated, thanks! > > > > > > Ray > > > > That is how the module works so I'll have to try some of these > > > options! The busy signal is set high the entire time data is being > > > written to the LCD. Originally I had a module "program.vhd" that > > > controlled the LCD module along with a keyboard module that we we had > > > in place for user input. Within program.vhd, I implement a state > > > machine and check if the busy signal is high before writing to the > > > LCD. If busy = 0, then I set din_ready high and set the 8-bits of > > > data. This is buffered within the LCD module and you only need to > > > hold din_ready for a single cycle to write to the LCD. The LCD is > > > connected over a 4-bit interface to the FPGA and this is taken care of > > > within the LCD module. When the writing operation begins busy is set > > > to '1' until complete. > > > > Ray > > > OK - I'm new to using the EDK and am having trouble implementing this > > with the FSL bus. I have a few questions: > > > 1) When I create a custom peripheral, it generates an HDL wrapper - Do > > I simply edit this wrapper by instantiating my LCD_top module as a > > component within the top level design? > > > 2) Should I check the box "Generate template driver files to help you > > implement software interface", or will the provided functions to read > > and write to the FSL bus suffice? > > > 3) Do you know of any good tutorials on how to implement a custom > > peripheral on the FSL bus? I've come across a few for adding > > peripherals to the other buses, but most that I have found do not > > follow through with how to edit the VHDL files and correctly add the > > peripheral to the system in Platform Studio (they simply tell you go > > to 'Create/Import Custom Peripheral'). > > > Any help/input is appreciated, thanks! > > > Ray > > Two more things - > > 1) the four output ports of the LCD module must be connected to the > external FPGA pins in order to drive the LCD. What is the best way to > go about doing this? Is this something that can be edited within > Platform Studio or do I need to manually edit VHDL/UCF files? I'm > assuming I will have to add the outputs to the interface shown below. > > 2) When I choose the master interface for the FSL bus, the ports are > defined as follows: > > -- DO NOT EDIT BELOW THIS LINE --------------------- > -- Bus protocol ports, do not add or delete. > FSL_Clk : in std_logic; > FSL_Rst : in std_logic; > FSL_S_Clk : out std_logic; > FSL_S_Read : out std_logic; > FSL_S_Data : in std_logic_vector(0 to 31); > FSL_S_Control : in std_logic; > FSL_S_Exists : in std_logic; > FSL_M_Clk : out std_logic; > FSL_M_Write : out std_logic; > FSL_M_Data : out std_logic_vector(0 to 31); > FSL_M_Control : out std_logic; > FSL_M_Full : in std_logic > -- DO NOT EDIT ABOVE THIS LINE --------------------- > > You mention that my din(7 downto 0) port should be connected to the > FSL_M_Data port, but the former is an input while the latter is an > output. Am I missing something? I tried to define this as a slave > interface, but that also yields an error when I try to generate the > bitstream. > > Thanks. I think I understand what you are saying, but I'm still unsure of how to implement it. I went through the 'Create and Import Peripheral' wizard to create the pcore and HDL wrapper file, but when you go through this it asks which bus you wish to attach the peripheral to - this generated HDL file is an interface file for the FSL bus, correct? I assumed I needed to edit this file and place my LCD module within this interface file (with the interface shown in my previous message). Do I need to go through this wizard to directly connect to the FSL interface or is this the incorrect method? When you say directly take the MicroBlaze signal and connect them to my module, do you mean edit the aforementioned wrapper file for the pcore, or is there an alternative way? Is there a top level VHD file that I need to edit in order to port the LCD module output to the external FPGA pins? I realize these probably are simple questions but since I've never been through this process within the EDK (and can't find any good tutorials - most deal with adding peripheral to OPB or PLB bus), I'm having a hard time figuring out which steps I need to take in order to accomplish what you have suggested. Anyway, I really do appreciate all your help so far. Thank you! RayArticle: 134093
> >"RCIngham" <robert.ingham@gmail.com> ha scritto nel messaggio >news:GemdnXcN7tHaHxXVRVn_vwA@giganews.com... >> > >>>** Is there any way i can rise the spi clock while >>>keeping the sd connector "off board"? ** >>> >> >> Try terminating the signals appropriately. For instance, series >> terminations on the CS, SCK and MOSI lines at the master. >> >> And before you ask, the value depends on the characteristic impedance of >> the cable... >> > >Before deciding to go on with a lower clock, i tried a parallel >termination. I tried a single resistor close to the receiver's SCK >line. It didn't help. Now reading again something about Digital >Signal Integrity i noticed that if the parallel resistor is not really >close to the receiver it cannot work because there ia a part of >impedance left unmatched. Series termination should not pose >this issue, so i hope they would do. Anyway i remember i read >somewhere that the highest termination value is about 330 ohm, >as a rule of thumb... perhaps. I think it's not possible though, to >calculate the real impedance, since the signal path is broken into: >fpga board, cable, breadboard, the small sd card board. > Have you measured the signals with an oscilloscope? What are the the rise and fall times, especially of SCK? Perhaps the drive capability of the outputs of the FPGA is insufficient relative to the high capacitance of the load? More drive AND series termination?Article: 134094
"RCIngham" <robert.ingham@gmail.com> ha scritto nel messaggio
news:x_2dnY2PK44pHhTVRVn_vwA@giganews.com...
> >
>>"RCIngham" <robert.ingham@gmail.com> ha scritto nel messaggio
>>news:GemdnXcN7tHaHxXVRVn_vwA@giganews.com...
>>> >
>>>>** Is there any way i can rise the spi clock while
>>>>keeping the sd connector "off board"? **
>>>>
>>>
>>> Try terminating the signals appropriately. For instance, series
>>> terminations on the CS, SCK and MOSI lines at the master.
>>>
>>> And before you ask, the value depends on the characteristic impedance
> of
>>> the cable...
>>>
>>
>>Before deciding to go on with a lower clock, i tried a parallel
>>termination. I tried a single resistor close to the receiver's SCK
>>line. It didn't help. Now reading again something about Digital
>>Signal Integrity i noticed that if the parallel resistor is not really
>>close to the receiver it cannot work because there ia a part of
>>impedance left unmatched. Series termination should not pose
>>this issue, so i hope they would do. Anyway i remember i read
>>somewhere that the highest termination value is about 330 ohm,
>>as a rule of thumb... perhaps. I think it's not possible though, to
>>calculate the real impedance, since the signal path is broken into:
>>fpga board, cable, breadboard, the small sd card board.
>>
>
> Have you measured the signals with an oscilloscope? What are the the rise
> and fall times, especially of SCK? Perhaps the drive capability of the
> outputs of the FPGA is insufficient relative to the high capacitance of
> the
> load? More drive AND series termination?
>
>
I don't have an oscilloscope available because i'm not into that
every day, but if i am not able to make it work with series
terminations i think i'll get one. In any case i'm a bit concerned
about using an oscilloscope... if fast signal transitions occurs, as
this article explains:
http://www.interfacebus.com/Design_Termination.html
the frequencies involved are "far" above the nominal one.
Here's the formula they show:
Signal Freq [GHz]=[0.35]/[Signal Transition Time{nSec)].
and perhaps a basic oscilloscope won't see that. This also
seems to be confirmed in this recent post:
"Micro-SD card initialisation-problem"
at comp.arch.embedded.
I guess something wrong with the clock was going on because
when the reading of the CSD/CID registers failed it was because
i got 0xFC as the "start" token while expecting 0xFE.
(0xFC == 0xFE << 1 ??). Reading the 16 data bytes anyway,
i got corrupted data.
I'll blindly try a set of series termination first. Starting from 10
ohm up to 120/220 ohm. I don't have them with me now...
i was unprepared for this sort of issue.
BTW... SD cards have an Erase command. In every implementation
i saw (mostly microcontroller based) it is never used. I can write
to the same sector again and again correctly. So when is Erase
used on SD Cards?
--
Article: 134095Hello, I want to implement a VHDL design in a Spartan3 device. Some components of the design use cascaded inverters to produce one-shots (short pulses). Upon synthesis, Xilinx-ISE simplifies the cascaded inverters (e.g. if 6 inverters are cascaded it simply removes them all). This alters the functionality of the design. How can I configure ISE so that it does not perform such simplifications (preferably per block, but if this is not possible for the whole design)? Thank you in advance guys! Regards, GeorgeArticle: 134096
Hi! I'm encountering a nasty bug when using the xilkernel with floating point. I have an application that uses the FPU (connected via APU) to the PPC440 (EDK 10.1 SP2). When I run the application standalone everything works fine. However, when I use xilkernel and use my application as starting thread execution stops after some time. I debugged this behaviour and can see, that the CPU issues an alignment exception all the time (remaining at the same instruction). The problem occurs in different regions of the program, depending on the code structure or whatever. For instance in _vprintf_r there is an instruction(stfd = store floating point double): stfd f30, 1760(r1) with r1 = 0x0111ed1a The resulting address is not aligned to an 8-byte boundary which causes the exception. It seems that the stack for the thread is not aligned to an 8-byte boundary. Looks like a xilkernel bug. Has anyone ever seen the same behaviour? How can I solve this problem? Thanks! Matthias AllesArticle: 134097
On Jul 25, 6:12 am, giorgos.puik...@gmail.com wrote: > Hello, > > I want to implement a VHDL design in a Spartan3 device. Some > components of the design use cascaded inverters to produce one-shots > (short pulses). Upon synthesis, Xilinx-ISE simplifies the cascaded > inverters (e.g. if 6 inverters are cascaded it simply removes them > all). This alters the functionality of the design. > > How can I configure ISE so that it does not perform such > simplifications (preferably per block, but if this is not possible for > the whole design)? > > Thank you in advance guys! > > Regards, > George Unfortunately simple logic elements like inverters and gates will always be mapped into LUT's regardless of any KEEP attributes on the intermediate nets. You can however create such delay elements by instantiating primitives like LUT's with the appropriate INIT attributes to generate the functions you want. Look at the Libraries guide to see your options for LUT instantiation. I should add that this sort of design practice is generally frowned upon in FPGA's, especially since there is a very wide variance in delay due to process and temperature, and a possibly even wider variance from build to build due to routing if you don't hand place your delay elements. Usually you can use synchronous techniques to create pulses and with a sufficiently fast clock rate you can often ignore the discrete timing effects of the synchronous pulse generator. Regards, GaborArticle: 134098
Hi again! > stfd f30, 1760(r1) with r1 = 0x0111ed1a > > The resulting address is not aligned to an 8-byte boundary which causes > the exception. It seems that the stack for the thread is not aligned to > an 8-byte boundary. Looks like a xilkernel bug. OK, I was able to fix this issue by myself in the xilkernel. My guess was right. The stack for all threads is created in mem.c line 63 like this: char thread_stack_mem[PTHREAD_STACK_MSIZE]; By replacing the line with char thread_stack_mem[PTHREAD_STACK_MSIZE] __attribute__ ((aligned (8))); the problems are gone. So the programmers of the xilkernel just never thought of 64bit types that some applications might use. MatthiasArticle: 134099
Board: spartan 3E Starter Kit, USB cable.
Project: Microblaze core, some perepherial and simple software
project.
XMDstub marked to initialize BRAMs.
Problem: In XMD after connection via USB I have a massege that there
is no signal Dbg_Rst...
Help...
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