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Hi > =A0 =A0I have checked. the first input sample is fed in when index for xn > is 3. No it isn't... the first input sample should be time aligned to when xn_index is 0. This occurs a few cycles (3 or so? i forget) after you assert Start high. > Did you do this the last time? No I haven't done what you said because I implemented in actual hardware, with real ADC (although double-checked against a digitially synthesized waveform), real data buffers on input and output, feeding output of the FFT out of the FPGA into a PC where it was post- processed in Matlab. I found no such problems that you report. I used the streaming core with various values of N (points), 24-bit for input, output and twiddles. I think the problems you seem to have found are unlikely to be related to quantization error... more likely a timing/simulation problem. It is extremely unlikely this bug exists in the hardware core itself, since it is used very widely in many applications. It is just about possible that it is a bug existing in the simulation files used by Modelsim. However, to be honest, it is much more likely it is due to something in your own implementation of the simulation testbench, or misunderstanding of the timing requirements for the core. Not sure I can assist you much more, if you are really stuck then open a Webcase with Xilinx and send them the simulation files you are using. One other thing - do check whether your scaling schedule is appropriate, and also whether you are expecting output in natural or bit/byte reversed order. Finally check you have not accidently enabled "cyclic prefix" (intended for use with OFDM transmitters), if you are using v5 of the core. -TArticle: 134251
"kami" <kamran.wadood@yahoo.co.uk> wrote in message news:wJOdnV4QFvPZ7w_V4p2dnAA@giganews.com... > >"kami" <kamran.wadood@yahoo.co.uk> wrote in message >>news:JJudnS58eI-AdwzV4p2dnAA@giganews.com... >>> Now, I was wondering what will be the best option if I wanted to >>> demonstrate the filter operation more clearly. I mean these are just >>> numbers that I am showing on the 7-seg display. But if I want to give > a >>> sinusoidal input and get a filtered waveform at the output. >> >>It wouldn't take much to drive a VGA display. >> > Do you mean using a logic analyzer? But my friend is struggling to develop > a logic analyzer in FPGA. So, how do you so it won't take much for VGA > display? > or do you mean using a cable (i've heard of a cable that can be connected > to FPGA and then the other end to the PC) is that what you meant? A VGA display needs only a few signal lines to drive it, fairly easy for the FPGA. I was maybe wrong to suggest it. Setting up a memory controller for the frame buffer and writing the line draw routines is too much of a project and distraction early on. Forget I mentioned it. Directly displaying the filtered waveform won't show the filtering as well a spectrogram. Your ears are also pretty sensitive to spectral changes. Audio will be the simplest demonstration. A DAC can drive earphones directly.Article: 134252
fmostafa wrote: > hi all; > > I am using Edk to create IP peripheral which contains RD and WR > Fifos. My question is, if the required data to be written to the read > fifo is undefined it will not be stored in the fifo or what. > > fatma Please define undefined data, electrically.Article: 134253
On 31 Jul., 15:26, nei...@pipstechnology.co.uk wrote: > On 31 Jul, 11:13, Brian Drummond <brian_drumm...@btconnect.com> wrote: > > > On Wed, 30 Jul 2008 06:41:15 -0700 (PDT), Dave <dhsch...@gmail.com> > > wrote: > > > >Does anyone know of a way to modify which VHDL libraries ISE > > >automatically uses in VHDL files created by the new file wizard? It > > >seems to always use std_logic_arith and std_logic_unsigned, and I > > >can't find a setting anywhere to modify this. I remember from my days > > >of using Quartus that there was a text are in the settings menus where > > >this could be changed. There's got to be something similar in ISE, > > >right? > > > If enouch people raise WebCases on this, Xilinx might eventually do > > something about it. > > > - Brian > > I raised a webcase on this back in 2006, and was told a change request > (CR # 425340) has already been filed and is scheduled to be fixed in a > later software release. I was running 8.2 at the time, so we've > already gone through a couple of software releases and still no fix. > > Maybe one of the Xilinx people here could chase up the CR and give us > an idea of when it will be fixed. > > Neill. oddly enough if you poke around in the xilinx directory you will find templates for some things, see for example \xilinx\data\testfix.tft -LasseArticle: 134254
langwadt@fonz.dk wrote: > On 31 Jul., 15:26, nei...@pipstechnology.co.uk wrote: >> On 31 Jul, 11:13, Brian Drummond <brian_drumm...@btconnect.com> wrote: >> >>> On Wed, 30 Jul 2008 06:41:15 -0700 (PDT), Dave <dhsch...@gmail.com> >>> wrote: >>>> Does anyone know of a way to modify which VHDL libraries ISE >>>> automatically uses in VHDL files created by the new file wizard? It >>>> seems to always use std_logic_arith and std_logic_unsigned, and I >>>> can't find a setting anywhere to modify this. I remember from my days >>>> of using Quartus that there was a text are in the settings menus where >>>> this could be changed. There's got to be something similar in ISE, >>>> right? >>> If enouch people raise WebCases on this, Xilinx might eventually do >>> something about it. >>> - Brian >> I raised a webcase on this back in 2006, and was told a change request >> (CR # 425340) has already been filed and is scheduled to be fixed in a >> later software release. I was running 8.2 at the time, so we've >> already gone through a couple of software releases and still no fix. >> >> Maybe one of the Xilinx people here could chase up the CR and give us >> an idea of when it will be fixed. >> >> Neill. > > oddly enough if you poke around in the xilinx directory you will find > templates for some things, see for example \xilinx\data\testfix.tft > > > -Lasse The CR is still open. I'm not sure how this feature is any better than creating your own source file and adding it to the project. -KevinArticle: 134255
On Aug 1, 2:42 pm, Kevin Neilson <kevin_neil...@removethiscomcast.net> wrote: > langw...@fonz.dk wrote: > > On 31 Jul., 15:26, nei...@pipstechnology.co.uk wrote: > >> On 31 Jul, 11:13, Brian Drummond <brian_drumm...@btconnect.com> wrote: > > >>> On Wed, 30 Jul 2008 06:41:15 -0700 (PDT), Dave <dhsch...@gmail.com> > >>> wrote: > >>>> Does anyone know of a way to modify which VHDL libraries ISE > >>>> automatically uses in VHDL files created by the new file wizard? It > >>>> seems to always use std_logic_arith and std_logic_unsigned, and I > >>>> can't find a setting anywhere to modify this. I remember from my days > >>>> of using Quartus that there was a text are in the settings menus where > >>>> this could be changed. There's got to be something similar in ISE, > >>>> right? > >>> If enouch people raise WebCases on this, Xilinx might eventually do > >>> something about it. > >>> - Brian > >> I raised a webcase on this back in 2006, and was told a change request > >> (CR # 425340) has already been filed and is scheduled to be fixed in a > >> later software release. I was running 8.2 at the time, so we've > >> already gone through a couple of software releases and still no fix. > > >> Maybe one of the Xilinx people here could chase up the CR and give us > >> an idea of when it will be fixed. > > >> Neill. > > > oddly enough if you poke around in the xilinx directory you will find > > templates for some things, see for example \xilinx\data\testfix.tft > > > -Lasse > > The CR is still open. I'm not sure how this feature is any better than > creating your own source file and adding it to the project. > -Kevin It seems like there's a few fairly simple changes like this that Xilinx has been "meaning to do" for quite a while, but never implementing. With FPGAs growing insanely large and complex, I wonder if silicon features will be less of a determining factor for market share than tool quality. I'm not at all sure X is beating A in that category...Article: 134256
Hi, just wondering about these...what are they, what hardware is involved, what are the advantages etc... thanksArticle: 134257
On Jul 31, 6:26=A0am, nei...@pipstechnology.co.uk wrote: > On 31 Jul, 11:13, Brian Drummond <brian_drumm...@btconnect.com> wrote: > > > On Wed, 30 Jul 2008 06:41:15 -0700 (PDT), Dave <dhsch...@gmail.com> > > wrote: > > > >Does anyone know of a way to modify which VHDL libraries ISE > > >automatically uses in VHDL files created by the new file wizard? It > > >seems to always use std_logic_arith and std_logic_unsigned, and I > > >can't find a setting anywhere to modify this. I remember from my days > > >of using Quartus that there was a text are in the settings menus where > > >this could be changed. There's got to be something similar in ISE, > > >right? > > > If enouch people raise WebCases on this, Xilinx might eventually do > > something about it. > > > - Brian > > I raised a webcase on this back in 2006, and was told a change request > (CR # 425340) has already been filed and is scheduled to be fixed in a > later software release. =A0I was running 8.2 at the time, so we've > already gone through a couple of software releases and still no fix. > > Maybe one of the Xilinx people here could chase up the CR and give us > an idea of when it will be fixed. FWIW, I opened up a WebCase and was told that Change Request CR #474759 was assigned to this same problem. Of course there is no way to determine what happens to a change request after it has been filed. I expect it was routed to /dev/null. -aArticle: 134258
On Aug 1, 7:05=A0am, fmostafa <fatma.abouele...@ugent.be> wrote: > hi all; > > I am using Edk =A0to create =A0IP =A0peripheral which contains RD and WR > Fifos. My question is, =A0if the required data to be written to the read > fifo is undefined =A0it will not be stored in the fifo or what. > > fatma Fatma, a FIFO is (conceptually) very simple: You store your data word by enabling the write clock, and you pull the data word out in the same sequence that you wrote it, by enabling the read clock. Use free- running clocks, and manipulate the Clock Enable. Remember: Data is never undefined, it is what it is, 0 or 1. Peter AlfkeArticle: 134259
It seems odd that the oscillator for that board is only 16Mhz...isn't the internal oscillator for the 3A even faster than that?Article: 134260
On 31 =D7=99=D7=95=D7=9C=D7=99, 06:31, andersod2 <thechrisander...@gmail.co= m> wrote: > Am using the free ISE Webpack, and wanted to know if it's possible > just to use the command line and code/config files...that counts for > things like package assignments and simulator stuff...can it be done > at all, or easily? > > Thanks for your insights... http://bknpk.no-ip.biz/leon_i2c_syn/leon_i2c_syn.htmlArticle: 134261
i'm dealing a board which has cpu,fpga, clock, adc etc. onboard. the clock is for board timing for both the fpga and adc. the init sequence was to load the fpga logic first, then the clock, then the adc. but fpga guys say it's wrong. should i init clock and adc first, then the fpga? what's the point here?Article: 134262
On Aug 2, 10:34 am, nub...@gmail.com wrote: > i'm dealing a board which has cpu,fpga, clock, adc etc. onboard. > the clock is for board timing for both the fpga and adc. > > the init sequence was to load the fpga logic first, then the clock, > then the adc. > but fpga guys say it's wrong. should i init clock and adc first, then > the fpga? > what's the point here? It's hard to see what you you should do in which order without more information on the system. What "clock", what "adc"? Is the FPGA in any way involved in the initialization of these circuits? If not, what is? A microcomputer? What sort of fpga? I'm guessing the "fpga guy" knows more about how the system should come up... Regards, GaborArticle: 134263
On Aug 1, 1:22 pm, andersod2 <thechrisander...@gmail.com> wrote: > Hi, just wondering about these...what are they, what hardware is > involved, what are the advantages etc... > > thanks PSoC is neither fish nor fowl. It's a strange combination of an 8-bit MCU (think 6502 levels of performance) with partially reconfigurable analog and digital arrays. It's great for low-cost applications requiring processing of slowly varying analog signals. The reconfigurable arrays are loaded at reset time with configuration info by the MCU from tables in flash memory that are defined with Cypress's design tools. Much of the run-time management of the various functions implemented in the arrays is dependent on interrupt service routines that are (mostly) hidden from the designer by the tools. The designer then ties these blocks together with hand-written assembly, or high-level point-n-click design flows. Analog functions include gain blocks, filters, ADCs and DACs. All functions are built using op-amps and switched capacitor blocks. Digital functions include counters, random number generators, UARTs, I2C slaves, etc. Neat parts if you've got a fairly low-end application. Not really FPGAs as such. EricArticle: 134264
andersod2 wrote: > Am using the free ISE Webpack, and wanted to know if it's possible just > to use the command line and code/config files...that counts for things > like package assignments and simulator stuff...can it be done at all, or > easily? Yes. The simplest is to take the .cmd_log file and use it as a script file. Under windows, rename this file to bat, and type that name at a command prompt to build the design. This is simple to set up, but fairly hard to modify. There are several other files that have been set up by ISE to control synthesis. These other files have the XST settings (not simple to modify) and the list of files used (the order the files are listed might be critical). The script might not work on Linux if produced on windows, and vice versa. You could also use a makefile. This is more complex to setup, but has the advantage of running only what is needed, and can be made OS independent. Starting with the script file and XST files generated above, convert the script to a makefile. Install the Cygwin package including gnu make. Then to run your make file at a command prompt type "make". Or you could use Tcl. Tcl is a built in scripting language. To get started, ISE under the project menu has "generate Tcl script". Edit the script as needed, or call it from another Tcl script. Tcl is a language used for scripting by both ISE many other CAD tools, such as Synplicity, ModelSim and PlanAhead. I've talked about this before: http://groups.google.com/group/comp.arch.fpga/msg/a6b1e400dd24d509?hl=en -- Phil HaysArticle: 134265
"John_H" <newsgroup@johnhandwork.com> wrote in message news:88fb24da-8f2b-4f3f-833a-059b79fc0eae@k30g2000hse.googlegroups.com... > fmostafa wrote: >> hi all; >> >> I am using Edk to create IP peripheral which contains RD and WR >> Fifos. My question is, if the required data to be written to the read >> fifo is undefined it will not be stored in the fifo or what. >> >> fatma > > Please define undefined data, electrically. ?? Undefined data is not defined, by definition. It is a simulation state, not an electrical state. JTWArticle: 134266
Thanks for your very informative answer Phil. I was wondering about using cygwin...good to know. Also, I just found out that many of the command line tools have pdf's that explain their operation...I forget the directory, but just search for "ngdbuild" in the xilinx directory and you'll see a bunch of pdfs.Article: 134267
On Aug 2, 6:37 pm, emeb <ebromba...@gmail.com> wrote: > On Aug 1, 1:22 pm, andersod2 <thechrisander...@gmail.com> wrote: > > > Hi, just wondering about these...what are they, what hardware is > > involved, what are the advantages etc... > > > thanks > > PSoC is neither fish nor fowl. It's a strange combination of an 8-bit > MCU (think 6502 levels of performance) with partially reconfigurable > analog and digital arrays. It's great for low-cost applications > requiring processing of slowly varying analog signals. Speaking of PSOC (will saying the name three times bring the CEO of Cypress forth?) what ever happened to their NEW, IMPROVED PSOC based on the ARM (CM3, IIRC)? My understanding is that the CEO said, thou shalt make a new PSOC with "NO EXCUSES" in the analog! I think it was originally supposed to be out at end of year 2006 or 2007 (can't remember which) and then put off for a bit. This is eight months later and I still haven't heard a peep about it. I expect it has gone the way of the T9000 transputer? I guess that is what happens when you are told to make it happen and "NO EXCUSES"! RickArticle: 134268
On Aug 3, 8:16 am, rickman <gnu...@gmail.com> wrote: > Speaking of PSOC (will saying the name three times bring the CEO of > Cypress forth?) what ever happened to their NEW, IMPROVED PSOC based > on the ARM (CM3, IIRC)? My understanding is that the CEO said, thou > shalt make a new PSOC with "NO EXCUSES" in the analog! I think it was > originally supposed to be out at end of year 2006 or 2007 (can't > remember which) and then put off for a bit. This is eight months > later and I still haven't heard a peep about it. I expect it has gone > the way of the T9000 transputer? I guess that is what happens when > you are told to make it happen and "NO EXCUSES"! (TJ Rogers appears in a puff of smoke) I hadn't heard of that. It's an interesting exercise to consider what an 'ideal' PSoC would consist of. An ARM-based MCU would be nice, as well as more flexible digital and analog arrays. There certainly are some attractive new ARM architectures out there (Cortex for instance) which are apparently more easily integrated. Cypress' recent additions to the PSoC line have tended to focus more on their capacitive touch senosors though - apparently they made a lot of money on those back at the start of the iPod days. Until they see a big pot-o-cash at the end of the design process though, I'd count an advanced PSoC as a low probability. EricArticle: 134269
On Aug 3, 12:31 pm, emeb <ebromba...@gmail.com> wrote: > On Aug 3, 8:16 am, rickman <gnu...@gmail.com> wrote: > > > Speaking of PSOC (will saying the name three times bring the CEO of > > Cypress forth?) what ever happened to their NEW, IMPROVED PSOC based > > on the ARM (CM3, IIRC)? My understanding is that the CEO said, thou > > shalt make a new PSOC with "NO EXCUSES" in the analog! I think it was > > originally supposed to be out at end of year 2006 or 2007 (can't > > remember which) and then put off for a bit. This is eight months > > later and I still haven't heard a peep about it. I expect it has gone > > the way of the T9000 transputer? I guess that is what happens when > > you are told to make it happen and "NO EXCUSES"! > > (TJ Rogers appears in a puff of smoke) > > I hadn't heard of that. It's an interesting exercise to consider what > an 'ideal' PSoC would consist of. An ARM-based MCU would be nice, as > well as more flexible digital and analog arrays. There certainly are > some attractive new ARM architectures out there (Cortex for instance) > which are apparently more easily integrated. Cypress' recent additions > to the PSoC line have tended to focus more on their capacitive touch > senosors though - apparently they made a lot of money on those back at > the start of the iPod days. Until they see a big pot-o-cash at the end > of the design process though, I'd count an advanced PSoC as a low > probability. I have to say I am getting tired of awaiting this "new" product. I think it is getting "old" in the planning. I did find this one public mention in a stock analyst's report. http://www.thestreet.com/files/k/tc/pdf/200807231712.pdf He gives some generally bullish info on Cypress with the PSOC part holding their own and the PSOC3 anticipated. Time will tell... if you can hold on long enough! RickArticle: 134270
>"kami" <kamran.wadood@yahoo.co.uk> wrote in message >news:wJOdnV4QFvPZ7w_V4p2dnAA@giganews.com... >> >"kami" <kamran.wadood@yahoo.co.uk> wrote in message >>>news:JJudnS58eI-AdwzV4p2dnAA@giganews.com... >>>> Now, I was wondering what will be the best option if I wanted to >>>> demonstrate the filter operation more clearly. I mean these are just >>>> numbers that I am showing on the 7-seg display. But if I want to give >> a >>>> sinusoidal input and get a filtered waveform at the output. >>> >>>It wouldn't take much to drive a VGA display. >>> >> Do you mean using a logic analyzer? But my friend is struggling to develop >> a logic analyzer in FPGA. So, how do you so it won't take much for VGA >> display? >> or do you mean using a cable (i've heard of a cable that can be connected >> to FPGA and then the other end to the PC) is that what you meant? > >A VGA display needs only a few signal lines to drive it, fairly easy for the >FPGA. I was maybe wrong to suggest it. Setting up a memory controller for >the frame buffer and writing the line draw routines is too much of a project >and distraction early on. Forget I mentioned it. > >Directly displaying the filtered waveform won't show the filtering as well a >spectrogram. Your ears are also pretty sensitive to spectral changes. Audio >will be the simplest demonstration. A DAC can drive earphones directly. > > Can you explain a little bit more about this application? where and how am I going to give input and how do I get the output? Is it just another (one or more) VHDL file I need to write? ThanksArticle: 134271
Hi all, I am doing a project involving PCI9054. I meet a problem of interrupt. I wanna assert a PCI interrupt using the LINT# pin which is set as input with the INTCSR register being setting as: 0X0f000900. But when I pull down the level of LINT# that is drived by FPGA, the INTCSR becomes 0X0f000100, that is, INTCSR[11](local interrupt input enable) is cleared and INTCSR[15](local input interrupt active) fails to be set 1. And also the interrupt handler is not called. I have no idea what the reason. However, when I set INTCSR as 0X0f000800 (PCI interrupt is not enabled) and then pull down LINT#, the INTCSR can come to the ideal value: 0X0f008800. I dont know its the reason of WinDriver diagnostic program or the PCI9054 itself. Any advice will be helpful, Thank u very much! Leon,Article: 134272
Hello all, Is it possible to use Cordic IP Core of Xilinx for Virtex 5 devices? The only solution I could come across for this problem is from the following URL: http://www.xilinx.com/support/answers/29055.htm Anyone who has tested this way or alternate solution please let me know. Thanks in advance, Venkat.Article: 134273
Hi,
I am trying to create a mex file that does fixed point FFT (512
point?). I am generally ok with creating a C code in single precision
to compute the the result and have ensured that it works fine as i get
the correct result. (i read it back and plotted it in matlab.)
the problem comes in when i try to convert it to fixed point. My
input data is 24 bits integer. In addition, I take the sine and cosine
twiddles to also be 24 bits... I do the cos(2*pi*n/N) and sin(2*pi/N)
for n from 0 to 255 the multply the result by ((2^23)-1) and store it
in a look up table.
What i really dun quite understand is how the scaling factors
work. In FFT books, they generally say that the output from each scale
should maybe be scaled by 1 bit to pre-empt bit growth problems. Also,
for unscaled bit-growth, it generally grows by log2(N) for an N point
FFT. But how does that work?
What i see here is the following:
1) 24 bit input data. If i dun convert it to anything, it becomes Q.24
format right?
2) 24 bit input data x 24 bit twiddle factor (Q.24 also). this becomes
48 bits. to prevent overflow, i scale by 24 say.
But this is too much and the output frequency spectrum becomes a mess.
I would forsee plenty of precision loss. If i scale by 1 from the
output of each stage, then the FFT gets clipped.
any ideas?what did i go wrong here? :(
could someone kindly help me with this? thanks for your help.
Article: 134274Hi, I'm new to FPGAs I just bought a Spartan 3E Starter Kit and I'm looking for documentation on Schematic capture with ISE or whatever would work for a good tutorial. It seems VERY hard to find ANY documentation though. I did find a starter video from digilent, but that was very short and seemed to be more of an intro to dataflow programming. Can anyone point me in the right direction? Thanks
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