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irfan.mohammed@gmail.com wrote: > i am having 8 point ifft implementation in vhdl,how can i convert it > to 64 point ifft(inverse fast forier transform). http://www.amethyst.co.il/imgs/Uploads/FFTS8KMR-Product-Brief.pdfArticle: 134301
On Aug 4, 5:02=A0pm, bishop...@gmail.com wrote: > Does anyone have any guidance into writing the timing constraints in > the UCF file to use RGMII on the ML405 development board from Xilinx? > Here is the relevant section in the UCF file: > > #### Module Ethernet_MAC constraints > > NET MDC_0 =A0 =A0 =A0 =A0 LOC =3D H11 | IOSTANDARD=3DLVCMOS33; > NET MDIO_0 =A0 =A0 =A0 =A0LOC =3D K13 | IOSTANDARD=3DLVCMOS33; > NET phy_rst_n =A0 =A0 LOC =3D J13 | IOSTANDARD=3DLVCMOS33; > Net phy_rst_n =A0 =A0 TIG; > > NET RGMII_TXD_0<3> LOC =3D G15 | IOSTANDARD=3DLVCMOS33 | SLEW=3DFAST; > NET RGMII_TXD_0<2> LOC =3D H12 | IOSTANDARD=3DLVCMOS33 | SLEW=3DFAST; > NET RGMII_TXD_0<1> LOC =3D H16 | IOSTANDARD=3DLVCMOS33 | SLEW=3DFAST; > NET RGMII_TXD_0<0> LOC =3D J16 | IOSTANDARD=3DLVCMOS33 | SLEW=3DFAST; > > NET RGMII_TX_CTL_0 LOC =3D K12 | IOSTANDARD=3DLVCMOS33 | SLEW=3DFAST; > NET RGMII_TXC_0 =A0 =A0LOC =3D D15 | IOSTANDARD=3DLVCMOS25 | SLEW=3DFAST; > > NET RGMII_RXD_0<3> LOC =3D G16 | IOSTANDARD=3DLVCMOS33; > NET RGMII_RXD_0<2> LOC =3D H14 | IOSTANDARD=3DLVCMOS33; > NET RGMII_RXD_0<1> LOC =3D G14 | IOSTANDARD=3DLVCMOS33; > NET RGMII_RXD_0<0> LOC =3D J15 | IOSTANDARD=3DLVCMOS33; > > NET RGMII_RX_CTL_0 LOC =3D J14 | IOSTANDARD=3DLVCMOS33; > NET RGMII_RXC_0 =A0 =A0LOC =3D F15 | IOSTANDARD=3DLVCMOS25; > > NET phy_rst_n =A0 =A0 =A0TIG; > > #### New GMAC Coregen Derived Constraints > > NET "*tx_gmii_mii_clk*" =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 TNM_N= ET =3D "clk_phy_tx_clk0"; > NET "*tx_gmii_mii_clk_in_0_i" =A0 =A0 =A0 =A0 TNM_NET =3D "clk_phy_tx_clk= 0"; > NET "*tx_gmii_mii_clk_out_0_i" =A0 =A0 =A0 =A0TNM_NET =3D "clk_phy_tx_clk= 0"; > TIMESPEC "TS_phy_tx_clk0" =A0 =A0 =A0 =A0 =A0 =A0=3D PERIOD "clk_phy_tx_c= lk0" 7200 > ps HIGH 50 %; > > NET "*gmii_rx_clk*" =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 TNM_NET =3D "clk_phy_rx_clk0"; > TIMESPEC "TS_phy_rx_clk0" =A0 =A0 =A0 =A0 =A0 =A0 =3D PERIOD "clk_phy_rx_= clk0" 7200 > ps HIGH 50 %; > > NET "*tx_client_clk*" =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 TNM= _NET =3D "clk_client_tx_clk0"; > TIMESPEC "TS_client_tx_clk0" =A0 =A0 =A0 =A0 =A0 =A0=3D PERIOD "clk_clien= t_tx_clk0" > 7200 ps HIGH 50 %; > > NET "*rx_client_clk*" =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 TNM= _NET =3D "clk_client_rx_clk0"; > TIMESPEC "TS_client_rx_clk0" =A0 =A0 =A0 =A0 =A0 =A0=3D PERIOD "clk_clien= t_rx_clk0" > 7200 ps HIGH 50 %; > > NET "*mii_tx_clk*" =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0TNM_NET =3D "clk_mii_tx_clk0"; > TIMESPEC "TS_mii_tx_clk0" =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D PERIOD "clk_mii= _tx_clk0" > 25000 ps HIGH 50 %; > > # Place flip flops in IOBs > INST "*gmii0?RXD_TO_MAC*" =A0 =A0IOB =3D true; > INST "*gmii0?RX_DV_TO_MAC" =A0 IOB =3D true; > INST "*gmii0?RX_ER_TO_MAC" =A0 IOB =3D true; > > # IDELAY on data path to align it with the clock > INST "*gmii_rxd?_delay" =A0 =A0 IOBDELAY_TYPE =3D FIXED; > INST "*gmii_rx_dv_delay" =A0 =A0IOBDELAY_TYPE =3D FIXED; > INST "*gmii_rx_er_delay" =A0 =A0IOBDELAY_TYPE =3D FIXED; > INST "*gmii_rxd?_delay" =A0 =A0 IOBDELAY_VALUE =3D 0; > INST "*gmii_rx_dv_delay" =A0 =A0IOBDELAY_VALUE =3D 0; > INST "*gmii_rx_er_delay" =A0 =A0IOBDELAY_VALUE =3D 0; > INST "*gmii_rx_clk_?_delay" IOBDELAY_TYPE =3D FIXED; > INST "*gmii_rx_clk_0_delay" IOBDELAY_VALUE =3D31 ; > > # Need to TIG between the LocalLink clock and the rx_client and > tx_client clocks > NET "*/LlinkTemac0_CLK*" TNM_NET =3D "LLCLK"; > > TIMESPEC "TS_LL_CLK_2_RX_CLIENT_CLK" =A0=3D FROM LLCLK TO > clk_client_rx_clk0 8000 ps DATAPATHONLY; > TIMESPEC "TS_LL_CLK_2_TX_CLIENT_CLK" =A0=3D FROM LLCLK TO > clk_client_tx_clk0 8000 ps DATAPATHONLY; > TIMESPEC "TS_RX_CLIENT_CLK_2_LL_CLK" =A0=3D FROM clk_client_rx_clk0 TO > LLCLK 10000 ps DATAPATHONLY; > TIMESPEC "TS_TX_CLIENT_CLK_2_LL_CLK" =A0=3D FROM clk_client_tx_clk0 TO > LLCLK 10000 ps DATAPATHONLY; > > I have tried the timing constraints generated from the wizard and from > the data sheet. =A0In both cases I get errors like this: > > ERROR:Place:872 - Delay element > =A0 =A0"TriMode_MAC_GMII/TriMode_MAC_GMII/V4HARD_SYS.I_TEMAC/ > SINGLE_RGMII2.I_EMAC_TO > =A0 =A0P/rgmii_rxd_rising_0_i<0>" has been placed at ILOGIC_X1Y95 due to > the > =A0 =A0following location constraint on component "RGMII_RXD_0<0>": > =A0 =A0 =A0 =A0 COMP "RGMII_RXD_0<0>" LOCATE =3D SITE "J15" LEVEL 1 > =A0 =A0However, the delay controller that calibrates this delay element > has not been > =A0 =A0used. Please instantiate a delay controller and apply appropriate > location > =A0 =A0constraint, or instantiate one delay controller for the design wit= h > out any > =A0 =A0location constraint. Please refer to the usage document to use the > controller > =A0 =A0efficiently. Well the error is quite simple. The IDELAYs are being LOC'd based upon the I/O pins for the RGMII. It looks like the IDELAYCTRL, is not being instantiated though. A quick perusal of the xps_ll_temac v1.00.b documentation shows that IDELAYCTRL should be instantiated. The name of it should be "dlyctrl0". Try opening up the NGC in floorplanner and see if you can find the name of the IDELAYCTRL. It still seems odd that it thinks there is no IDELAYCTRL, and its possible its a bug in the Xilinx core (that never happens ;P). What version(s) of ISE/EDK are you using? what core(s) are you using for your TEMAC implementation? -- MikeArticle: 134302
> i need yor valuable sugessions How valuable in USD or EUR?Article: 134303
If you already have a Xilinx board, check the the book "FPGA Prototyping by VHDL Examples" in amazon.com. Although not schematic based, it is a good hand-on introduction to VHDL and FPGA with many practical examples. I think a Verilog version is also available. Have fun. On Aug 4, 1:06=A0pm, laserbeak43 <laserbea...@gmail.com> wrote: > > > Schematic capture for FPGA design entry is moribund. > > > Consider learning vhdl or verilog instead. > > > If schematics are non-negotiable, consider quartus: > > > multimedia.ece.uic.edu/wahmad/quartus_ii_tutorial.pdf > > > Good luck. > > > > =A0 =A0 -- Mike Treseler > > Hmm, so i've heard. Everyone says Xilinx stuff is bad for beginners > and i must admit, > I've been doing nothing but troubleshooting ever since i got this > board, what a headache. > > > > > > > Since the OP already bought the Xilinx stuff, he may want to > > open ISE (or WebPack) and under Help --> Tutorials --> > > Tutorials on the Web, he can find what is available from > > Xilinx. =A0Look for "ECS" schematics. =A0By the way I have > > not looked at these myself. =A0I too use =A0HDL rather than > > schematics since I "upgraded" from version 4.1 - the > > last Foundation version with Aldec schematics. =A0Also > > go tohttp://forums.xilinx.com/andcheck out all of > > the chatter on schematics. =A0In my opinion, the ECS > > schematics are not ready for prime time. =A0The > > associated documentation is not likely to be better. > > > Oh, and before you get ideas of using Foundation > > 4.1 schematics, it is no longer available from Xilinx > > due to a termination of their agreement with Aldec. > > > Aldec has wonderful new software that supports > > Xilinx parts and others, but it would cost a lot more > > than a good Altera evaluation board and a copy of > > Quartus. > > > Just my 2 cents, > > Gabor > > I think i'm gonnna sell this board and go for an Altera board. > but i'll try that first. > > thanks guys.- Hide quoted text - > > - Show quoted text -Article: 134304
>Leon wrote: >> Hi all, >> >> I am doing a project involving PCI9054. >> >> I meet a problem of interrupt. I wanna assert a PCI interrupt using the >> LINT# pin which is set as input with the INTCSR register being setting >> as: >> 0X0f000900. But when I pull down the level of LINT# that is drived by >> FPGA, the INTCSR becomes 0X0f000100, that is, INTCSR[11](local interrupt >> input enable) is cleared and INTCSR[15](local input interrupt active) fails >> to be set 1. And also the interrupt handler is not called. I have no idea >> what the reason. >> >> However, when I set INTCSR as 0X0f000800 (PCI interrupt is not enabled) >> and then pull down LINT#, the INTCSR can come to the ideal value: >> 0X0f008800. I dont know its the reason of WinDriver diagnostic program or >> the PCI9054 itself. >> >> Any advice will be helpful, Thank u very much! >> >> Leon, > >While that's certainly not enough information for me to offer you any >help, I'll throw out that in my experience PLX, who makes the only >PCI9054 that I know of, has fairly responsive technical support when you >send them an email. They'll take a couple days to get back to you, but >what you get will be both thought out and relevant to your question. >Have you tried their guys yet? > >-- >Rob Gaddi, Highland Technology >Email address is currently out of order > Hi Rob, Actually, I am registering a technical support account from PLX. I think I have found the cause of that problem. Its the problem of the driver on the host PC. When I unintalled the PLX SDK, and used only WinDriver only, the INTA# could be asserted. But still, the WinDriver kernel interrupt handler failed to "acknowledge the interrupt" (that is, clear the interrupt enable bit in INTCSR register) and the user defined ISR was also not be perfomed. Someone says that its the problem of the version of WinDriver, and someone says that its the problem of windows OS. Actually, a new version of WinDriver also does not work for me. Motherboard, OS, WinDriver. How could them work together well? Thank u Rob. Leon,Article: 134305
Hello all,
I've been having trouble with this for a while, but I think I'm
extremely close to getting something working. I currently am using a
Spartan-3E starter board with an LCD. Before I was building a system
purely with VHDL, but I want to add a MicroBlaze core and connect my
hardware LCD module to the FSL bus instead of implementing software
drivers. The interface and description of the LCD module are shown
below:
entity LCD_top is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC_VECTOR (7 downto 0);
din_ready : in STD_LOGIC;
busy : out STD_LOGIC;
LCD_D : out STD_LOGIC_VECTOR (11 downto 8);
LCD_E : out STD_LOGIC;
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC);
end LCD_top;
The busy signal is set high the entire time data is being
written to the LCD. If busy = 0, then I set din_ready high and set
the 8-bits of
data. This is buffered within the LCD module and you only need to
hold din_ready for a single cycle to write to the LCD. The LCD is
connected over a 4-bit interface to the FPGA and this is taken care of
within the LCD module. When the writing operation begins busy is set
to '1' until complete.
Within Platform Studio I imported this module using the 'Create and
Import Peripheral' wizard. This generated the FSL wrapper file to
interface with the FSL FIFO. I instantiated my module as a component
within this wrapper. I also added the necessary output ports to drive
the external LCD on the board. The top level interface file is shown
below:
entity lcd_core is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : out std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
LCD_D : out std_logic_vector(0 to 3);
LCD_E : out std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic
);
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
attribute SIGIS of FSL_S_Clk : signal is "Clk";
end lcd_core;
architecture structure of lcd_core is
component lcd_top
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC_VECTOR (7 downto 0);
din_ready : in STD_LOGIC;
busy : out STD_LOGIC;
LCD_D : out STD_LOGIC_VECTOR (11 downto 8);
LCD_E : out STD_LOGIC;
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC);
end component;
signal dataIn : std_logic_vector(7 downto 0);
signal dataInReady : std_logic;
signal LCD_busy : std_logic;
type statetype is (S1, S2, S3);
signal state, next_state : statetype := S1;
begin
M1: lcd_top port map(FSL_Clk, FSL_Rst, dataIn, dataInReady, LCD_busy,
LCD_D, LCD_E, LCD_RS, LCD_RW);
state <= next_state;
process(FSL_Clk, FSL_Rst) is
begin
if(FSL_Rst = '1') then
next_state <= S1;
FSL_S_Read <= '0';
dataInReady <= '0';
test_out <= '0';
elsif(rising_edge(FSL_Clk)) then
case state is
when S1 =>
FSL_S_Read <= '0';
if (FSL_S_Exists = '1') then
dataIn(7 downto 0) <= FSL_S_Data(24 to 31);
dataInReady <= '1';
next_state <= S2;
end if;
when S2 =>
dataInReady <= '0';
next_state <= S3;
when S3 =>
if (LCD_busy = '0') then
FSL_S_Read <= '1';
next_state <= S1;
end if;
end case;
end if;
end process;
end architecture structure;
I have successfully downloaded this design to the board and believe I
have all the correct port connections. The software application is
very simple and the main loop is shown below:
while(1)
{
// Simple delay loop to allow for LCD initialization
procedures in hardware
do
{ i++;}
while(i < 25000000);
printOnce = TRUE;
// write a single character to the LCD
if(printOnce == TRUE && donePrinting == FALSE)
{
LCD_data = 0x42000000;
putdfslx(LCD_data, 0, FSL_DEFAULT);
fsl_isinvalid(isInvalid);
if(isInvalid == 1)
print("Invalid Operation!\r\n");
else
print("Valid Operation!\r\n");
donePrinting = TRUE;
}
}
First, my LCD peripheral is setup as a slave to the FSL bus while the
microblaze processor core is the master. With that said, are the
putdfslx() or putfslx() functions the correct way to pass data to the
LCD core? Based on my previous descriptions of my system, does it
seem as though this is implemented correctly? It runs and outputs
'Valid Operation', but the LCD is not reponsive whatsoever. I have
already tested this module before and had it working properly without
MicroBlaze. I also added a test_out port to lcd_core (interface
file), and mapped this to an unused pin on the Spartan board. This
output pin was set to '0' upon reset and then set to '1' permanently
if S3 was reached as shown below. I have confirmed that this state is
reached because the pin was indeed set high.
when S3 =>
if (LCD_busy = '0') then
test_out <= '1';
FSL_S_Read <= '1';
next_state <= S1;
end if;
Any idea as to why this might not be working? Am I missing some type
of software initialization of the FSL bus? I already had a response
saying you can directly connect the module to the FSL master interface
on Microblaze without going through the bus, but in the future I made
need to add several peripherals so I would kind of like to get this
working with the bus if possible. I GREATLY appreciate any input.
Thank you!
Article: 134306Mike, That is one of Ross Freeman's originals (before he left Zilog, and started Xilinx). AustinArticle: 134307
Jon Beniston wrote:
> Do you know what the relevant patents are?
>
I found the press release by Altera on August 4th rather unusal as they
had filed this suit back on May 23rd. I'm not sure why they waited 10
weeks to issue a press release.
The following is from the US District Court for the Eastern District of
Texas through PACER. If you want a patent lawsuit to go quickly you
file in this "rocket docket" district.
Case: 2:08-cv-00218-TJW
Altera Corporation v. Zilog, Inc.
T. John Ward, presiding
Date filed: 05/23/2008
Date of last filing: 07/08/2008
No. Dates Description
-- 05/23/2008 Case Assigned/Reassigned
1 05/23/2008 Complaint
2 05/23/2008 Notice of Filing of Patent/Trademark Form (AO 120)
3 05/23/2008 Magistrate Consent Form Mailed
4 06/04/2008 Notice of Attorney Appearance
-- 06/19/2008 Summons Issued
5 06/24/2008 Notice of Attorney Appearance
6 06/24/2008 Notice of Attorney Appearance
7 07/02/2008 Summons Returned Executed
8 07/07/2008 Unopposed Application for Extension of Time to Answer
-- 07/08/2008 Application Granted for Extension of Time to Answer
In Altera's Complaint they listed 3 patents.
6,097,211 - "Configuration Memory Integrated Circuit"
6,147,411 - "Overvoltage-Tolerant Interface For Integrated Circuits
6,314,550 - "Cascaded Programming With Multi-Purpose Pins"
I have not reviewed any of these patents so I'm not sure what the actual
patent claims are.
Ed McGettigan
--
Xilinx Inc.
Article: 134308I get the following error while trying to program a Vertex4 FPGA using impact 10.1. ERROR:Bitstream:14 - The device part "4vlx100ff1513" specified in the bitstream file "c:/work/fpga.bit" is invalid. This file may be corrupted and should be recreated. I've tried 3 different bitstreams with the same error. Impact is able to identify by FPGA as an xc4vlx100 from the boundary scan. My colleagues at a different location are able to program the same bitstream on an identical board with the same version of Xilinx Impact. I've tried installing impact on 2 PCs in my own office without any luck. I get the same error if I try to generate prom files for the onboard FLASH option. Possible solutions - 1) Download ISE 9.2i, 9.1i and pray. This is painful since the webpacks are 1GB+ and take a whole day to download. Can I download only Impact? 2) Am I missing any Service Packs? 3) Any other suggestions? Regards tushitArticle: 134309
laserbeak43 wrote: > Hmm, so i've heard. Everyone says Xilinx stuff is bad for beginners > and i must admit, > I've been doing nothing but troubleshooting ever since i got this > board, what a headache. Take a look at: ftp://137.193.164.130/pub/mproz/mproz3_e.pdf ftp://137.193.164.130/pub/mproz/mproz3.zip It's a step by step introduction for a simple design (ISE 9.2, Spartan3E) using schematic entry.Article: 134310
offer accepted!! :) On Aug 4, 5:03=A0pm, "Eric Crabill" <eric.crab...@xilinx.com> wrote: > Hi, > > If you have the time, I invite you to contact me directly (privately) to > discuss your experience with the Spartan-3E Starter Kit. =A0As you might > imagine, it is intended for "starters" and not intended to generate > frustration! > > I know you are interested in schematic based design entry, so the followi= ng > resource may be of limited interest (but I'll include it anyway): > > http://www.engr.sjsu.edu/crabill > > I look forward to hearing from you, > > Eric Crabill > > =3D=3D=3D=3D=3D > > "laserbeak43" <laserbea...@gmail.com> wrote in message > > news:38faf0eb-3746-49f1-84f3-1720ba98d399@r66g2000hsg.googlegroups.com... > > > > Schematic capture for FPGA design entry is moribund. > > > Consider learning vhdl or verilog instead. > > > If schematics are non-negotiable, consider quartus: > > > multimedia.ece.uic.edu/wahmad/quartus_ii_tutorial.pdf > > > Good luck. > > > > -- Mike Treseler > > Hmm, so i've heard. Everyone says Xilinx stuff is bad for beginners > and i must admit, > I've been doing nothing but troubleshooting ever since i got this > board, what a headache. > > > > > Since the OP already bought the Xilinx stuff, he may want to > > open ISE (or WebPack) and under Help --> Tutorials --> > > Tutorials on the Web, he can find what is available from > > Xilinx. Look for "ECS" schematics. By the way I have > > not looked at these myself. I too use HDL rather than > > schematics since I "upgraded" from version 4.1 - the > > last Foundation version with Aldec schematics. Also > > go tohttp://forums.xilinx.com/andcheck out all of > > the chatter on schematics. In my opinion, the ECS > > schematics are not ready for prime time. The > > associated documentation is not likely to be better. > > > Oh, and before you get ideas of using Foundation > > 4.1 schematics, it is no longer available from Xilinx > > due to a termination of their agreement with Aldec. > > > Aldec has wonderful new software that supports > > Xilinx parts and others, but it would cost a lot more > > than a good Altera evaluation board and a copy of > > Quartus. > > > Just my 2 cents, > > Gabor > > I think i'm gonnna sell this board and go for an Altera board. > but i'll try that first. > > thanks guys.Article: 134311
Yep,
have been considering that book. looks tempting. I did notice that
board he's using is different though.
On Aug 5, 12:38=A0pm, fp <fpga002...@yahoo.com> wrote:
> If you already have a Xilinx board, check the the book "FPGA
> Prototyping by VHDL Examples" in amazon.com. =A0Although not schematic
> based, it is a good hand-on introduction to VHDL and FPGA with many
> practical examples. =A0I think a Verilog version is also available.
>
> Have fun.
>
> On Aug 4, 1:06=A0pm, laserbeak43 <laserbea...@gmail.com> wrote:
>
> > > > Schematic capture for FPGA design entry is moribund.
> > > > Consider learning vhdl or verilog instead.
> > > > If schematics are non-negotiable, consider quartus:
> > > > multimedia.ece.uic.edu/wahmad/quartus_ii_tutorial.pdf
> > > > Good luck.
>
> > > > =A0 =A0 -- Mike Treseler
>
> > Hmm, so i've heard. Everyone says Xilinx stuff is bad for beginners
> > and i must admit,
> > I've been doing nothing but troubleshooting ever since i got this
> > board, what a headache.
>
> > > Since the OP already bought the Xilinx stuff, he may want to
> > > open ISE (or WebPack) and under Help --> Tutorials -->
> > > Tutorials on the Web, he can find what is available from
> > > Xilinx. =A0Look for "ECS" schematics. =A0By the way I have
> > > not looked at these myself. =A0I too use =A0HDL rather than
> > > schematics since I "upgraded" from version 4.1 - the
> > > last Foundation version with Aldec schematics. =A0Also
> > > go tohttp://forums.xilinx.com/andcheckout all of
> > > the chatter on schematics. =A0In my opinion, the ECS
> > > schematics are not ready for prime time. =A0The
> > > associated documentation is not likely to be better.
>
> > > Oh, and before you get ideas of using Foundation
> > > 4.1 schematics, it is no longer available from Xilinx
> > > due to a termination of their agreement with Aldec.
>
> > > Aldec has wonderful new software that supports
> > > Xilinx parts and others, but it would cost a lot more
> > > than a good Altera evaluation board and a copy of
> > > Quartus.
>
> > > Just my 2 cents,
> > > Gabor
>
> > I think i'm gonnna sell this board and go for an Altera board.
> > but i'll try that first.
>
> > thanks guys.- Hide quoted text -
>
> > - Show quoted text -
Article: 134312thanks for the offer, but the links seem to be dead, and the only version of ISE that truly works for me, is 7.1i(i haven't tried anything earlier than that, though) although, i'm sure i could easily change things around to get it to work in 7. On Aug 6, 4:07=A0am, Herbert Kleebauer <k...@unibwm.de> wrote: > laserbeak43 wrote: > > Hmm, so i've heard. Everyone says Xilinx stuff is bad for beginners > > and i must admit, > > I've been doing nothing but troubleshooting ever since i got this > > board, what a headache. > > Take a look at: > > ftp://137.193.164.130/pub/mproz/mproz3_e.pdfftp://137.193.164.130/pub/mpr= oz/mproz3.zip > > It's a step by step introduction for a simple design > (ISE 9.2, Spartan3E) using schematic entry.Article: 134313
laserbeak43 wrote: > > thanks for the offer, but the links seem to be dead, and the only > version > of ISE that truly works for me, is 7.1i(i haven't tried anything > earlier than that, though) > although, i'm sure i could easily change things around to get it to > work in 7. Sorry: ftp://137.193.64.130/pub/mproz/mproz3_e.pdf ftp://137.193.64.130/pub/mproz/mproz3.zip Or here a http mirror: http://www.ikomi.de/pub/ > On Aug 6, 4:07 am, Herbert Kleebauer <k...@unibwm.de> wrote: > > laserbeak43 wrote: > > > Hmm, so i've heard. Everyone says Xilinx stuff is bad for beginners > > > and i must admit, > > > I've been doing nothing but troubleshooting ever since i got this > > > board, what a headache. > > > > Take a look at: > > > > ftp://137.193.164.130/pub/mproz/mproz3_e.pdfftp://137.193.164.130/pub/mproz/mproz3.zip > > > > It's a step by step introduction for a simple design > > (ISE 9.2, Spartan3E) using schematic entry.Article: 134314
"devices" <me@home> ha scritto nel messaggio news:4888e604$0$1083$4fafbaef@reader2.news.tin.it... > > "RCIngham" <robert.ingham@gmail.com> ha scritto nel messaggio > news:GemdnXcN7tHaHxXVRVn_vwA@giganews.com... >> > >>>** Is there any way i can rise the spi clock while >>>keeping the sd connector "off board"? ** >>> >> >> Try terminating the signals appropriately. For instance, series >> terminations on the CS, SCK and MOSI lines at the master. >> >> And before you ask, the value depends on the characteristic impedance of >> the cable... >> > > Before deciding to go on with a lower clock, i tried a parallel > termination. I tried a single resistor close to the receiver's SCK > line. It didn't help. Now reading again something about Digital > Signal Integrity i noticed that if the parallel resistor is not really > close to the receiver it cannot work because there ia a part of > impedance left unmatched. Series termination should not pose > this issue, so i hope they would do. Anyway i remember i read > somewhere that the highest termination value is about 330 ohm, > as a rule of thumb... perhaps. I think it's not possible though, to > calculate the real impedance, since the signal path is broken into: > fpga board, cable, breadboard, the small sd card board. > After fixing a couple of bugs, i've finally replaced the short cable with four terminating resistors. 10 ohm killed the... iusse. I haven't checked data values yet but it never timed out at any speed. Usually when it doesn't time out data is ok. --Article: 134315
> =A0 =A06,097,211 - "Configuration Memory Integrated Circuit" After quickly scanning this - I'm struggling to see what the "invention" is. > 6,147,411 - "Overvoltage-Tolerant Interface For Integrated Circuits 5V tolerant I/O with a 3.3V supply. Hardly the first company to do that. Maybe the actual circuit to implement it was novel. > =A0 =A06,314,550 - "Cascaded Programming With Multi-Purpose Pins" LOL! They've invented multifunction I/O pins. > I have not reviewed any of these patents so I'm not sure what the actual > patent claims are. They all sound like the usual nonsense to me. Yet more evidence that the patent system needs serious reform. JonArticle: 134316
>> =A0 =A06,097,211 - "Configuration Memory Integrated Circuit" > >After quickly scanning this - I'm struggling to see what the >"invention" is. > >> 6,147,411 - "Overvoltage-Tolerant Interface For Integrated Circuits > >5V tolerant I/O with a 3.3V supply. Hardly the first company to do >that. Maybe the actual circuit to implement it was novel. > >> =A0 =A06,314,550 - "Cascaded Programming With Multi-Purpose Pins" > >LOL! They've invented multifunction I/O pins. > >> I have not reviewed any of these patents so I'm not sure what the actual >> patent claims are. > >They all sound like the usual nonsense to me. Yet more evidence that >the patent system needs serious reform. > >Jon > Ther is a fairly well argued rant against patents (or at least the USA's interpretation of patents) at http://www.embeddedtechjournal.com/articles_2008/20080729_patent.htm I'm not sure that the idea of patents is completely broken, but it certainly needs major reform so that innovation is reasonably protected and rewarded. A copiers' free-for-all would also be bad, IMHO.Article: 134317
On Aug 6, 4:41=A0am, Jon Beniston <j...@beniston.com> wrote: > > =A0 =A06,097,211 - "Configuration Memory Integrated Circuit" > > After quickly scanning this - I'm struggling to see what the > "invention" is. > Perhaps evaluation of novelty requires more than a 'quick scan'. > > 6,147,411 - "Overvoltage-Tolerant Interface For Integrated Circuits > > 5V tolerant I/O with a 3.3V supply. Hardly the first company to do > that. Maybe the actual circuit to implement it was novel. > A novel circuit (if that's the case) even to implement something that is not functionally new is patentable...you don't agree? > > I have not reviewed any of these patents so I'm not sure what the actua= l > > patent claims are. > Usually people don't boast about their lack of knowledge due to their own lack of effort to review the publicly available material...in a public forum no less. > They all sound like the usual nonsense to me. Yet more evidence that > the patent system needs serious reform. > If it interests you, perhaps you research beyond the titles of the patents. Until you can rebut the specific claims in the patents perhaps you should refrain from slamming the patent holders. I'm presuming that you wouldn't appreciate a slam against you or your work by someone who didn't take any time to look at the details so perhaps you could extend that same courtesy to others. KevinArticle: 134318
rickman wrote:
>
> One suggestion. When implementing counters, it is slightly more
> efficient to implement them as loadable down counters.
>
>
> This is because in most technologies there is a carry chain built in
> that can detect when counter is 0. If you are counting up to (M-1)
> the synthesizer has to use LUTs to detect the final state if M is not
> a power of 2.
>
> Rick
Good point, but remember up counters are fine too! E.g. divide by 200...
if count = 255 then
count <= 56;
else
count <= count + 1;
end if;
Or something like that.
HTH, Syms.
Article: 134319Cock up trying to post to comp.lang.vhdl, apologies.Article: 134320
Hi guys: I'm prototyping an application using a Xilinx Spartan-3 development board. I'm using this particular development kit because it is suited to the large amount of I/O I need. I'm new to FPGA, so I have written the code in Verilog using almost exclusively a high-level, behavioural style. The program works, but synthesizes using 99% of the available slices. So if I try to change or improve the code, it often synthesizes to over 100% and kicks out an error. I need to condense what I've got to give me some space to work with. The application is basically a large number of high-speed pulse inputs. I count them all independently and average several readings over time for each to produce a 21-bit number. Each of these 21-bit vectors (there are almost 100) is sent to a central processing module that evaluates and compares them using simple arithmetic. Based on these comparisons, another set of vectors is sent on to a couple of modules that arrange them into a special synchronous serial output. That's all it does. Are there any standard tips or general guidelines that you might offer to condense my synthesis? I have found, for example, that making the vectors smaller doesn't really change the overall slice count, yet commenting out a single line of the processing code can change it drastically. Any ideas or comments would be greatly appreciated. DonArticle: 134321
eromlignod wrote:
> The application is basically a large number of high-speed pulse
> inputs. I count them all independently and average several readings
> over time for each to produce a 21-bit number. Each of these 21-bit
> vectors (there are almost 100) is sent to a central processing module
> that evaluates and compares them using simple arithmetic. Based on
> these comparisons, another set of vectors is sent on to a couple of
> modules that arrange them into a special synchronous serial output.
Since the answer is shifted out in serial,
maybe it could be constructed a bit at a time
to save resources.
> Are there any standard tips or general guidelines that you might offer
> to condense my synthesis?
A basic trade is time for gates.
A serial crc is slower, but requires less resources
than the parallel version, for example.
-- Mike Treseler
Article: 134322> A novel circuit (if that's the case) even to implement something that > is not functionally new is patentable...you don't agree? No. Being novel is not the only requirement. > > > I have not reviewed any of these patents so I'm not sure what the actual > > > patent claims are. > > Usually people don't boast about their lack of knowledge due to their > own lack of effort to review the publicly available material...in a > public forum no less. You might want to check who you have quoted, especially given your next comment. > I'm presuming that you wouldn't appreciate a slam against you or your > work by someone who didn't take any time to look at the details so > perhaps you could extend that same courtesy to others. I have read through the patents and stand by my comments. JonArticle: 134323
eromlignod wrote: <snip> > > Are there any standard tips or general guidelines that you might offer > to condense my synthesis? I have found, for example, that making the > vectors smaller doesn't really change the overall slice count, yet > commenting out a single line of the processing code can change it > drastically. > > Any ideas or comments would be greatly appreciated. > > Don Time multiplexing can often help significantly. If you have 100 21-bit counters, the 2100 registers and associated muxing can take a lot of space. If you're not running near the limit of the part, you could increase the clock rate and share some counters in distributed memory. If things are really slow, you can go to BlockRAMs, eliminating the redundancy and reducing read mux logic significantly. If you can't increase the processing frequency, you could still count the LSbits and cycle through the counters, adding and clearing the LSbits to a BlockRAM worth of counter values. To cycle through 255 32-bit counters, you'd need 8-bit counters for each signal and a read-add-write cycle (using the dual-port mode) for each entry in your list. You end up only using half the BlockRAM for this extreme number of counters. It's more housekeeping but you use a fraction of the count resources.Article: 134324
> Ther is a fairly well argued rant against patents (or at least the USA's > interpretation of patents) athttp://www.embeddedtechjournal.com/articles_2008/20080729_patent.htm > > I'm not sure that the idea of patents is completely broken, but it > certainly needs major reform so that innovation is reasonably protected and > rewarded. A copiers' free-for-all would also be bad, IMHO.- Hide quoted text - It seems far too many companies seem to think that anything new they do is patentable. In the UK there is a requirement that the invention must also not be obvious to anyone with experience in the field. If the same problem that is solved by many inventions in recent patents were to be given to 10 other engineers, I'm fairly sure some of them would come up with similar or better solutions. If that is the case, then I don't think an invention should be patentable. If you solve something that others have struggled with, then maybe you have a case. Jon
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