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On 20 sep, 20:44, Jeff Cunningham <j...@sover.net> wrote: > cesarp wrote: > > Hi everyone. > > I'm trying to transfer data from DDR memory to a custom PLB_IPIF > > peripheral in a Virtex II Pro XUP card. I have some questions: > > 1. In EDK is not possible to configure a scatter-gather DMA access > > with PLB in the Peripheral wizard. Why? > > 2. I'm trying to transfer data using simple DMA under linux 2.4 > > compiled for PPC405, but the system crash when it is inicialized the > > DMA transfer. Totally dead. I'm keeping in mind the differences > > between physical and virtual addresses in source and destiny > > registers, in fact i have tried with a driver for kernel. In > > standalone mode the DMA transfer works fine. I'm working with EDK > > 8.2 . > > > I know there are many things can be wrong, but any help or suggestion > > is appreciated. > > Do you have access to chipscope and some spare block rams? With that you > could trace what the PLB is doing when it dies. > > -Jeff I'm trying it. i hope there are ram enough. Thanks!Article: 124426
I have a doc. named "Partial Reconfiguration Design with PlanAhead 9.2" and use PR_V5_DVI.zip for example. While following the step to Implementing the Static Logic and Implementing the PR Modules, there be a problem. After PAR completed the static Launch run and continue to Launch run for PR Modules, I got a error message said:"Static run needs to complete before any config runs are launched. Please reset this config run and complete the static run. Upon completion you can safely re- launch this config run." But the static run is already complete. Even I reset the PR Modules form the original source of PR_V5_DVI.zip, there stilled the same error. By the way, I follow the PR_install.pdf re-install all the software again in the order but nothing change. It still doesn't work. Could any environment setting problem casue this error or put the projecet file in wrong location? Did I miss some step or what? Could you help me fix up this problem? Thanks.Article: 124427
On Sep 21, 7:19 am, Thomas Stanka <usenet...@stanka-web.de> wrote: > On 20 Sep., 11:36, merche <dora...@gmail.com> wrote: > > > > > > > On Sep 20, 7:26 am, Thomas Stanka <usenet...@stanka-web.de> wrote: > > > > On 19 Sep., 17:56, merche <dora...@gmail.com> wrote: > > > > > Hi!, I have a big problem: > > > > > I use Libero to Proasic Plus Family of Actel. My FPGA has got 4 glo= bal > > > > pin (4 GL macro), I need put a clock in a global buffer but I can= =B4t > > > > because I have others signals with highest fanout. what can I do? > > > > Explain your real problem. Do you need more global inputs or is it a > > > problem of synthesis? Then instantiate a GL Buffer for the clk in your > > > code > > > thanks Thomas Stanka! But... > > > In my code I have instantiated a GL Buffer (is a fast clock). But in > > the synthesis: the log say... > > > Automatic dissolve during optimization of view:work.w_r9(w_r9) of > > GL2(GL) > > There exist no GL2 in the APA library AFAIK. Try GL25 instead. > Instantiating the clk-Buffer in code should work for Synplify. > > If nothing helps, you could edit the edif netlist to get a clk-buffer > for the clk input, but this should be done _very_ carefully. > > bye Thomas- Hide quoted text - > > - Show quoted text - GL2 is the name instanciated, the entity is a GL33. I put in the global pin, but in the chipplanner I see that don=B4t use de global macro, becouse the tool (sinplicity) put other signal. the edif netlist is only for the pins (external pad)?Article: 124428
For those of you frustrated with our PayPal payments system we have hopefully now got it sorted. Any more problems please let us know. Apologies to those that suffered. We are also hoping to offer Google Checkout soon as an alternative. John Adair Enterpoint Ltd.Article: 124429
On Sep 19, 3:55 am, "comp.arch.fpga" <ksuli...@googlemail.com> wrote: > On 18 Sep., 19:17, Weng Tianxiang <wtx...@gmail.com> wrote:> Hi, > > 1. I am talking about GUESSING the largest number of state machines a > > current finished design may have. Not ceiling. > > But you do not react if someone answers your question. Can you beat > the > 10k+ state machines of a smith-waterman DNA matcher? > > > 3. A synchronous or an asynchronous reset signal is vital, either with > > clear routing or a hidden within other procedures. > > Again, you did not read my post. Many state machines have no reset > signal. > For example the reset signal of a JTAG controller is optional. This is > a state machine that is implemented in virtually every complex piece > of silicon out there. > > Kolja Sulimma Hi Weng and all fellow engineers, I more or less agree with all of you on ur guesses and responses... I dont quite understand what Weng is up to? If you wanna twist ur question in any way to mislead us, u could do so forever, and no answer would SATISFY u, cus there is no real question.. Are u really trying to have an answer/discussion that benefit us all, OR u r just playing with ur words cus u probably finished clicking as to test the modules that design engineers handed u in....? For the sake of every one else, my share of the answer would be: I would subdivide the question as: 1. How many FSM can fit current chips? 2. How many FSM is appropriate for a given design? 3. How many states within each FSM should there be? My guess/answers: A.1: twice as much available Registers in the chip (after considering registers needed for other modules) A.2: Depending on the complexity of the design, as many as required, provided that each FSM do not exceed more than 15 states or so...(more than 15, becomes harder to debug, and follow..) A.3. Embedded in A.2, hence, max 15-20 states per FSM would be a best suit based on my experience...Larger than 20, the FSM should be broken down into 2 FSMs... But again, as others pointed out, the whole number of FSMs can be considered as one large FSM, cus they interact with each other through handshake signals anyways.... Amir, that it depends on design complexity, however,Article: 124430
Hi, I am interested in learning FPGA based processor for embedded systems. I have used both Altera and Xilinx software (for VHDL synthesis). Two boards I am considering are - Cyclone II FPGA Starter Development Kit http://www.altera.com/products/devkits/altera/kit-cyc2-2C20N.html - Xilinx Spartan-3E Starter Kit http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-SK-US-G I am looking for one with a simpler "tool chain" and user interface. Any suggestion? Thank you in advance. S. C.Article: 124431
"fp" <fpga002006@yahoo.com> wrote in message news:1190390295.516240.91540@50g2000hsm.googlegroups.com... > Hi, > > I am interested in learning FPGA based processor for embedded > systems. I have used both Altera and Xilinx software (for VHDL > synthesis). Two boards I am considering are > > - Cyclone II FPGA Starter Development Kit > http://www.altera.com/products/devkits/altera/kit-cyc2-2C20N.html > > - Xilinx Spartan-3E Starter Kit > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-SK-US-G > > I am looking for one with a simpler "tool chain" and user interface. > Any suggestion? Thank you in advance. > > S. C. Are you interested in the 32-bit cores that aren't free such as Nios-II and MicroBlaze? If so, you may want to ask the vendor about Nios-II or MicroBlaze development kits that would have much greater existing support than any generic starter board. If you're using the Mico32, your choices are broadened but your support is probably much less than the fee-based cores. I know Xilinx has an XC3S1600E on their MicroBlaze Development Kit; otherwise it's much like the 500E-based board that you referenced. If you use the starter board, any reference designs they provide will need to be slightly altered. If you use the MicroBlaze Development Kit, the reference designs are drop-in. http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DO-SP3E1600E-DK-UNI-G - John_HArticle: 124432
Alan Nishioka wrote: > On Sep 20, 11:47 am, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal > Murray) wrote: >>(Isn't it great that FPGAs have so many FFs? :) > A pessimist would complain about paying for all those FF's he can't > use :-) I have mentioned that previously in discussions on doing asynchronous (self timed) logic in FPGAs. There is then no use for FFs. -- glenArticle: 124433
>A.2: Depending on the complexity of the design, as many as required, >provided that each FSM do not exceed more than 15 states or so...(more >than 15, becomes harder to debug, and follow..) >A.3. Embedded in A.2, hence, max 15-20 states per FSM would be a best >suit based on my experience...Larger than 20, the FSM should be broken >down into 2 FSMs... It's perfectly reasonable to build FSMs with hundreds or even thousands of states. The trick is to think of it as software and build yourself an assembler so you can really implement it that way. People have been using ROMs for this type of state machine for a long time. 256x8 ROMs were common back in the old TTL/DIP days. That style of FSMs usually has clumps of states that don't branch. If you draw the typical circles and arrows state diagram, you might want to include each clump in one circle. It just takes several cycles/states to do the "action" associated with a state transition. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 124434
Weng Tianxiang wrote: (snip) > Scrambler cannot meet the requirements. If it were, every circuit > would be counted as a state machine. There is a class of circuits call combinatorial logic. Generally that means no state, no memory, and so no state machine. With combinatorial logic the outputs will come to a value that only depends on the inputs after the appropriate propagation delay. Otherwise, yes, every circuit that has a state memory counts as a state machine. > Shift registers can be counted as a state machine only when only one > bit is set or reset among all its bits. Otherwise it cannot be counted > as a state machine. I don't understand this restriction at all. -- glenArticle: 124435
Symon wrote: (snip, someone wrote) >> The >>metastability will be so short in duartion you may as well ignore is >>effect unless you have a clock period above 500Mhz. > That's not true. (You did say you were up for an argument!) Flipflops can go > metastable for any (unlimited) amount of time, with rapidly decreasing > probability as the metastable time increases. Also, it is not necessarily > the case that the FF's output goes crazy during metastability. The effect > can manifest itself as an arbtrarily long clock to out. There is always the probability that your FF could get hit by a cosmic ray with enough charge to flip it. If you get the metastability probability below that, it should be good enough. > As to ignoring this effect unless you're going at 500MHz or more, I hope you > don't work on any safety critical systems! In FPGA-land, the timing closure > tools only aim to meet the clock timing for non-metastable FFs. The place > and route could easily leave a circuit vulnerable to a slight increase in > clock to out delay caused by metastability. There has to be some margin in the timing calculation in addition to the specified setup and hold times. Below some frequency, the probability will be low enough not to worry about it. I don't know what that frequency is, though. Have you ever calculated the probability that all the air molecules will move to one half of the room and suffocate you? -- glenArticle: 124436
Allan Herriman wrote: (snip) > A few years ago, I designed what I believe was the first 10Gb/s AES256 > encryptor on the market. It used CTR mode, because that was the only > mode suitable to run at those rates in the FPGAs that were available > then. (snip) > For the crypto naive: The throughput of a block cypher with feedback > is determined by the delay through the block cypher calculation. > Pipelining is good for getting impressive clock numbers, but it > actually hurts throughput. You should be able to process multiple data streams, though. (Similar to the multithreading processors popular a few years ago.) I would expect that anyone needed such high speed would have more than one document to encrypt or decrypt. > http://en.wikipedia.org/wiki/Block_cipher_modes_of_operation -- glenArticle: 124437
merche wrote:
> GL2 is the name instanciated, the entity is a GL33. I put in the
> global pin, but in the chipplanner I see that donīt use de global
> macro, becouse the tool (sinplicity) put other signal. the edif
> netlist is only for the pins (external pad)?
If you have Synplicity why not let it
infer the buffers? You shouldn't
have to instance any buffers in your code.
-- Mike Treseler
Article: 124438"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:uYmdneQmW_sFaW7bnZ2dneKdnZydnZ2d@comcast.com... > > There is always the probability that your FF could get hit by a cosmic > ray with enough charge to flip it. If you get the metastability > probability below that, it should be good enough. > Hi Glen, Good point, although, to be pedantic, it's not the charge of the particle, it's its energy that's important. Especially if one of these buggers scores a bullseye. http://en.wikipedia.org/wiki/Ultra-high-energy_cosmic_ray Protons with as much kinetic energy as a 60mph cricket ball. > > Have you ever calculated the probability that all the air molecules will > move to one half of > the room and suffocate you? > You need a tame Maxwell's demon for that to happen! Cheers, Syms.Article: 124439
On Sep 20, 6:42 am, merche <dora...@gmail.com> wrote: > thanks Thomas Stanka! But... > > In my code I have instantiated a GL Buffer (is a fast clock). But in > the synthesis: the log say... > > Automatic dissolve during optimization of view:work.w_r9(w_r9) of > GL2(GL) > > then, others signals with highest fanout promoted to global buffer. > This synthesis is made with Synplify. > > I don=B4t know how change this automatic options. Use the following in your constrains file (filename.gcf) dont_fix_globals; set_auto_global 0; set_global <your clock name >; It works for meArticle: 124440
On 21 Sep, 18:53, "John_H" <newsgr...@johnhandwork.com> wrote: > "fp" <fpga002...@yahoo.com> wrote in message > > news:1190390295.516240.91540@50g2000hsm.googlegroups.com... > > > > > Hi, > > > I am interested in learning FPGA based processor for embedded > > systems. I have used both Altera and Xilinx software (for VHDL > > synthesis). Two boards I am considering are > > > - Cyclone II FPGA Starter Development Kit > >http://www.altera.com/products/devkits/altera/kit-cyc2-2C20N.html > > > - Xilinx Spartan-3E Starter Kit > >http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.j... > > > I am looking for one with a simpler "tool chain" and user interface. > > Any suggestion? Thank you in advance. > > > S. C. > > Are you interested in the 32-bit cores that aren't free such as Nios-II and > MicroBlaze? If so, you may want to ask the vendor about Nios-II or > MicroBlaze development kits that would have much greater existing support > than any generic starter board. If you're using the Mico32, your choices > are broadened but your support is probably much less than the fee-based > cores. > > I know Xilinx has an XC3S1600E on their MicroBlaze Development Kit; > otherwise it's much like the 500E-based board that you referenced. If you > use the starter board, any reference designs they provide will need to be > slightly altered. If you use the MicroBlaze Development Kit, the reference > designs are drop-in. > > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.j... > > - John_H I have used the ML403 development board from Xilinx. The EDK software makes it very easy to develop an embedded processor system. See my blog : http://www.fpgafromscratch.com SvenArticle: 124441
"Shift registers can be counted as a state machine only when only one bit is set or reset among all its bits. Otherwise it cannot be counted as a state machine." "I don't understand this restriction at all. -- glen" Hi Glen, For a 4-bit shift register to be counted as a state machine, it must have data: "0001", "0010", "0100" and "1000" for an active high state machine, or "1110", "1101", "1011" and "0111" for an active low state machine. It must meet state machine requirements: A state machine can be defined in such a scientific way: 1. All states in a state machine have their own names; 2. All states in a state machine are mutually exclusive; 3. Only one state is active in any cycle; 4. The number of states in a state machine must be 2 or more; 5. There must be clear asynchronous or a synchronous reset signal, or hidden procedure for the state machine. After their assertion or initialization the state machine must be in known initial state. For a 4-bit shift register that has data "1100" cannot be counted as a state machine. Even though they may be used for state machine functions. In such cases, they are called shift registers, not state machines. Roughly speaking, in VHDL, it is used to be declared in the following way: type xxx (...); signal StateMachine, NextState : xxx; If you use above format to declare a state machine, the statistics would be shown in Xilinx compilation result. And the declared state machine would meet all above 5 requirements. Xilinx compiler does the right thing. Hi Amir, My question is very clear: "What is the largest number of state machines in a current chip design: 1k, 10k or ... " If you know, please give the answer and why. If you don't know and are interested in it, please be quiet and patient, or don't join the topics discussion if you think it is wasting your time. I will disclose my answer at appropriate time. It is not a trivial quiz. You may hear it before, but forget to remember to connect it with the question. My question is not how to design a state machine, or how many states a state machine may have, or how many state machines a FPGA/IC can construct. Those questions are beyond interest of my topics. WengArticle: 124442
>For a 4-bit shift register to be counted as a state machine, it must >have data: >"0001", "0010", "0100" and "1000" for an active high state machine, or >"1110", "1101", "1011" and "0111" for an active low state machine. That's total nonsense. Your pattern describes a one-hot state machine. That simplifies decoding states, but there is nothing in the rules of state machines that says I have to use that encoding. It's common to encode states in kludgy ways that make decoding convenient. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 124443
On Sep 21, 2:32 pm, "Symon" <symon_bre...@hotmail.com> wrote: > "glen herrmannsfeldt" <g...@ugcs.caltech.edu> wrote in message > > news:uYmdneQmW_sFaW7bnZ2dneKdnZydnZ2d@comcast.com... > > > There is always the probability that your FF could get hit by a cosmic > > ray with enough charge to flip it. If you get the metastability > > probability below that, it should be good enough. > > Hi Glen, > Good point, although, to be pedantic, it's not the charge of the particle, > it's its energy that's important. Especially if one of these buggers scores > a bullseye.http://en.wikipedia.org/wiki/Ultra-high-energy_cosmic_ray > Protons with as much kinetic energy as a 60mph cricket ball. > > > Have you ever calculated the probability that all the air molecules will > > move to one half of > > the room and suffocate you? > > You need a tame Maxwell's demon for that to happen! > > Cheers, Syms. This thread seems to have gone way off the original topic. To address the OP's original issues: 1) Metastability will limit the best theoretically possible detection threshold for measurement. i.e. when the two signals are very close in time, there will be a chance of metastability. The degree to which this matters depends on the tme between receiving the input signals and making the decision based on the detector outputs. 2) Routing delays will afftect the accuracy of the "detector". i.e. if routing delay to clock differs from routing delay to D by more than the time difference between the incoming signals you may get an incorrect result. This routing delay difference is probably much larger than the metastability window for the D flip-flop. This is also why he gets a warning about "gated clocks". 3) The removal of 3/4 of his slices is probably unrelated to the "gated clock" warning. This usually occurs when an output is unused or a necessary signal (like a clock to a section of the design) is not provided, resulting in the removal of unused or undriven sections. The map report should shed some light on this. It may be necessary to set a verbose flag to get the logic removal details. HTH, Gabor PS - I dropped out of a statistical mechanics course when the professor explained how multiplying a very large number by 10 resulted in essentially the same number. As I recall we were looking at numbers described as 10 to the 10 to the 23rd power (for example), and therefore the 10x bigger number was 10 to the ((10 to the 23rd power) plus 1). In any case it would take numbers of this magnitude to describe the chances of some large number of atoms drifting to one half of a room. By comparison, the age of the universe expressed in units of the time it takes light to traverse the electron orbit of a hydrogen atom can be expressed in numbers around 10 to the 40th power (IIRC). In other words, no way in hell :)Article: 124444
In comp.arch.fpga, Hal Murray <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote: >>If the clock to out can be arbitrary long, how would the above proposed >>solution with the extra synchronizer DFF solve the problem? If the setup >>of the synchronizer DFF is violated (which is inevitable as the D-input >>is an external signal), it's output may violate the input setup time >>of the synchronous system for the next clock edge. > > You have to wait long enough. Long "enough" has to be defined by > your application. > > Metastability decays exponentially so waiting a little longer is a big help. > In many cases, waiting a clock cycle gives a probability of trouble > that is very very very low. You see jokes about 1 event until the > sun goes nova, but numbers like that are reasonable. > Thank you Symon, Mk and Hal for your amazingly synchrounous (pun intended :-) answers, rarity on usenet. So far I've only seen talk of violated setup times in relation with the metastability problem. No problems with hold times? I've done a resonable amount of logic designs (TTL/CPLD/FPGA), but never have run into this problem. Maybe because most of my designs run fairly slow and I always like to clock everithing through dff's anyway. :-) -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)Article: 124445
>So far I've only seen talk of violated setup times in relation with the >metastability problem. No problems with hold times? Yes, you have to meet hold times too. Xilinx has decided to make all their hold times 0. That avoids calculating hold times. Well, not really. There is clock skew. So what they really guarantee is that the clock-to-out and shortest routing will provide enough hold time for the worst case clock skew. So sometimes I/we get sloppy and forget to mention hold times. >I've done a resonable amount of logic designs (TTL/CPLD/FPGA), but never >have run into this problem. Maybe because most of my designs run fairly >slow and I always like to clock everithing through dff's anyway. :-) Beware. It's not how slow your clock is running, it the ratio of your clock speed to the speed of your logic family. Metastability resolution scales (handwave, roughly) with logic speed. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 124446
On Sun, 16 Sep 2007 17:26:42 -0700, Weng Tianxiang <wtxwtx@gmail.com> wrote: >Hi, >I would like to pose an interesting guess topics for experienced >engineers: >What is the largest number of state machines in a current chip design: >1k, 10k or ... > >I have finished 8 projects and only counted 27 state machines in one >of my biggest designs. > >I may know the answer. The final result may surprise everyone who >gives a guess. > >Weng According to a show I just saw on the History Channel, during the last days of World War II, Adolph Hitler paced up and down the halls of his bunker, trying to determine the number of state machines you could fit into a 12AU7. By the power vested in me by the First Corollary of Godwin's Law, I declare this thread officially over. No need to thank me, Bob Perlman Cambrian Design Works http://www.cambriandesign.comArticle: 124447
On Sep 21, 7:07 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Weng Tianxiang wrote: > > (snip) > > > For a 4-bit shift register to be counted as a state machine, it must > > have data: > > "0001", "0010", "0100" and "1000" for an active high state machine, or > > "1110", "1101", "1011" and "0111" for an active low state machine. > > It must meet state machine requirements: > > A state machine can be defined in such a scientific way: > > 1. All states in a state machine have their own names; > > 2. All states in a state machine are mutually exclusive; > > 3. Only one state is active in any cycle; > > 4. The number of states in a state machine must be 2 or more; > > 5. There must be clear asynchronous or a synchronous reset signal, or > > hidden > > procedure for the state machine. After their assertion or > > initialization > > the state machine must be in known initial state. > > There are many restricted types of state machines, usually named > after the first person to publish the description. > > I would say that you have now defined the weng machine, which > is fine. That doesn't have anything to do with the state > machines that others may define and use. > > You requirement on naming states reminds me of an old saying: > "If a tree falls in the forest and nobody is around to > hear it does it make any noise?" > > Whether the states are named or not has no effect on > the logic. That states are mutually exclusive and > only one state active in each cycle are sort of obvious > requirements. (That doesn't restrict it to one hot > state machines, an active state is any specific > combination of the state variables.) > > Also that there must be more than one state is > a reasonable restriction. Many state machines > are self synchronizing so don't need a reset signal. > Others do need one. There are some that can start > in an illegal state and never reach a legal state > without a reset. Most try not to design that way > if it is reasonable not to do so. > > -- glen Hi Glen, "That doesn't restrict it to one hot state machines, an active state is any specific combination of the state variables" I agree with your opinion. WengArticle: 124448
Weng Tianxiang wrote: (snip) > For a 4-bit shift register to be counted as a state machine, it must > have data: > "0001", "0010", "0100" and "1000" for an active high state machine, or > "1110", "1101", "1011" and "0111" for an active low state machine. > It must meet state machine requirements: > A state machine can be defined in such a scientific way: > 1. All states in a state machine have their own names; > 2. All states in a state machine are mutually exclusive; > 3. Only one state is active in any cycle; > 4. The number of states in a state machine must be 2 or more; > 5. There must be clear asynchronous or a synchronous reset signal, or > hidden > procedure for the state machine. After their assertion or > initialization > the state machine must be in known initial state. There are many restricted types of state machines, usually named after the first person to publish the description. I would say that you have now defined the weng machine, which is fine. That doesn't have anything to do with the state machines that others may define and use. You requirement on naming states reminds me of an old saying: "If a tree falls in the forest and nobody is around to hear it does it make any noise?" Whether the states are named or not has no effect on the logic. That states are mutually exclusive and only one state active in each cycle are sort of obvious requirements. (That doesn't restrict it to one hot state machines, an active state is any specific combination of the state variables.) Also that there must be more than one state is a reasonable restriction. Many state machines are self synchronizing so don't need a reset signal. Others do need one. There are some that can start in an illegal state and never reach a legal state without a reset. Most try not to design that way if it is reasonable not to do so. -- glenArticle: 124449
Jim Lewis wrote: >>> IF OP = "Weng Tianxiang" AND group = comp_arch_fpga THEN >>> be_prepared_for_a_long_thread; >>> ORIF crossposted = to_comp_lang_vhdl THEN >>> this_could_go_on_all_week; >>> ANDIF both_the_above THEN >>> make_that_a_month; >>> BUTIF plonk! THEN >>> blessed_relief; >>> ELSIF experiences < imagination THEN >>> OP_question <= not(sense); >>> ELSE >>> possibly_on_topic; >>> END IF; > ... >> >> What's this ANDIF, BUTIF ?!?! >> > > And I was hoping for an ORELSE :) Coming soon to a thread near you: ELSEMAYBEIF, ELSECONFUSEDIF, ELSERANDOMIF, etc. I wonder if Weng will ever quit creating and feeding these very much pointless threads. Maybe he's just a bad comedian.
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