Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 124450

Article: 124450
Subject: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Fri, 21 Sep 2007 21:01:32 -0700
Links: << >>  << T >>  << A >>
On Sep 19, 9:54 am, Shannon <sgo...@sbcglobal.net> wrote:
> I gave my guess.  Why haven't you responded?  You told me you would
> tell me the answer after I guessed.  Now tell me.
>
> Shannon

Hi Sannon,
1. It is L2 cache that uses a lot of state machines;
http://en.wikipedia.org/wiki/Cache_coherence

2. IBM/Intel uses MESI protocol (Modified, Eclusive, Shared and
Invalid);
http://en.wikipedia.org/wiki/MESI_protocol

3. Please visit Intel product website to get the latest news:
http://download.intel.com/products/processor/xeon/7300_prodbrief.pdf

4. "with up to 8 MB of L2 cache per processor" and 4 cores.
It means 4*8MB = 32MB L2 cache;

5. Each 32Bytes is a cache line;

6. 32MB/32 = 1M cache lines and 1M state machines.

The final answer is:
There is at least 1M state machines in Intel chip.

a. It is available to every users in the topics groups;
b. They are written in Verilog, not in VHDL;
c. FPGA has never had a design using L2 cache.

Any more questions?

Weng


Article: 124451
Subject: Re: Looking for fast AES cores with low latency
From: Allan Herriman <allanherriman@hotmail.com>
Date: Sat, 22 Sep 2007 15:42:27 +1000
Links: << >>  << T >>  << A >>
On Fri, 21 Sep 2007 09:52:39 -0800, glen herrmannsfeldt
<gah@ugcs.caltech.edu> wrote:

>Allan Herriman wrote:
>
>(snip)
>
>> A few years ago, I designed what I believe was the first 10Gb/s AES256
>> encryptor on the market.  It used CTR mode, because that was the only
>> mode suitable to run at those rates in the FPGAs that were available
>> then.
>(snip)
>
>> For the crypto naive:  The throughput of a block cypher with feedback
>> is determined by the delay through the block cypher calculation.
>> Pipelining is good for getting impressive clock numbers, but it
>> actually hurts throughput.
>
>You should be able to process multiple data streams, though.
>(Similar to the multithreading processors popular a few
>years ago.)  I would expect that anyone needed such high
>speed would have more than one document to encrypt or
>decrypt.
>
>> http://en.wikipedia.org/wiki/Block_cipher_modes_of_operation


I wish it could work that way.  But the problem is that you don't use
10Gb/s encryptors to encrypt "documents", just a single continuous
stream (or context) at 10Gb/s.

Well, at least that's the way our customers use them.


On a brighter note, it is possible to interleave CFB, so that each
"engine" has to sample every 2nd (for two way interleave) 128 bit
block.  This is discussed in Schneier.

Regards,
Allan

Article: 124452
Subject: Configuring Impact on any version of linux
From: Ankit <ankitanand1986@gmail.com>
Date: Sat, 22 Sep 2007 03:02:18 -0700
Links: << >>  << T >>  << A >>
Hi guys i want to use Xilinx 8.2i or 9.1i or even 7.1i for burning
codes on my FPGA board using the Parallel port on Linux..The linux
which i have are Fedora Core 6,Ubuntu and Open Suse 10.2..I have been
able to install Xilinx on all of them but till now i have not been
able to configure Impact..I have gone through loads of stuff on net
but somehow it has not worked out so it would be really great if 1 of
you could please write down the exact procedure that you did so that
Impact started working on linux..I have tried installing Windriver
many times but most of the times the kernel version of the linux which
i have does not matches with 1 they say it should work with..I have
tried many other things so please do not forward a link which you have
not tried please tell me the method that worked for you...Waiting for
replies..


Regards
Ankit Anand


Article: 124453
Subject: Re: Configuring Impact on any version of linux
From: svenand <svenand@comhem.se>
Date: Sat, 22 Sep 2007 06:52:32 -0700
Links: << >>  << T >>  << A >>
On Sep 22, 12:02 pm, Ankit <ankitanand1...@gmail.com> wrote:
> Hi guys i want to use Xilinx 8.2i or 9.1i or even 7.1i for burning
> codes on my FPGA board using the Parallel port on Linux..The linux
> which i have are Fedora Core 6,Ubuntu and Open Suse 10.2..I have been
> able to install Xilinx on all of them but till now i have not been
> able to configure Impact..I have gone through loads of stuff on net
> but somehow it has not worked out so it would be really great if 1 of
> you could please write down the exact procedure that you did so that
> Impact started working on linux..I have tried installing Windriver
> many times but most of the times the kernel version of the linux which
> i have does not matches with 1 they say it should work with..I have
> tried many other things so please do not forward a link which you have
> not tried please tell me the method that worked for you...Waiting for
> replies..
>
> Regards
> Ankit Anand

This worked for me. See my blog : http://svenand.blogdrive.com/archive/55.html

Sven



Article: 124454
Subject: DDR RAM timing contraints
From: pwie42 <paul@sisyphus.teil.cc>
Date: Sat, 22 Sep 2007 07:39:10 -0700
Links: << >>  << T >>  << A >>
hei list,

i am working on a DDR-Ram controller for the ml401 board from xilinx.
the controller i am using is generated by the MIG tool provided by
xilinx. I have adapted this design to be used with the ml401, and
everything works fine in the simulation,

BUT: when i am running a backannotated sdf simulation of the PAR model
i get some VITAL timing error from one in die dqs input out block
located FF which looks something like this:

# ** Warning: /X_FF SETUP  Low VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.108 ns; Observed := 0.07 ns; At : 285545.237 ns
#    Time: 285545237 ps  Iteration: 3
Instance: /mem_interface_top_tb/dut/
main_00_top_00_iobs_00_data_path_iobs_00_v4_dqs_iob3_dqs_pipe1

a setup time violation in the X_FF primitve! so i tried to constraint
the design properly to tell the par tools to take care of this:
first of all i was following the quide provided by:
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iCountryID=1&iLanguageID=1&getPagePath=12819&BV_SessionID=@@@@1652334992.1190471362@@@@&BV_EngineID=ccceaddllfjgmlecefeceihdffhdfkf.0

#constrains the main clock after the DCM
NET "CLK_0" TNM_NET = "clk0_grp"; # Group FFs that are clocked by DCM
CLK0 output
TIMESPEC "TS01" = PERIOD "clk0_grp" 10 ns HIGH 50%;

#reates the timing group that contains all the DDR input pads:
#INST cntrl0_DDR_DQ[*]  TNM="IN_DDR_grp";
INST cntrl0_DDR_DQS[3] TNM="IN_DDR_grp";

#create the separate timing groups for the rising and falling-edge
registers.
TIMEGRP "DDRInRisingGrp"  = RISING  "clk0_grp";
TIMEGRP "DDRInFallingGrp" = FALLING "clk0_grp";

#we apply the OFFSET IN BEFORE constraint to the rising edge timing
group -
#the data to be clocked on the rising edge has a setup time of 2.5ns
before the rising edge
TIMEGRP "IN_DDR_grp" OFFSET = IN  2.5 ns BEFORE "sysclk_in" TIMEGRP
"DDRInRisingGrp";
TIMEGRP "IN_DDR_grp" OFFSET = IN -2.5 ns BEFORE "sysclk_in" TIMEGRP
"DDRInFallingGrp";


without any results, i was also trying to run the design at a lower
clk speed of 50Mhz -> no results... btw. the synthesis tools reports
that speeds up to 200 Mhz are possible. i would like to run the design
with a 100Mhz clk,

i also tryed to constrain the net with an AFTER constraint:

NET "main_00/tNET "sysclk_in" TNM_NET = "sysclk_in";
TIMESPEC TS_sysclk_in = PERIOD "sysclk_in" 10 ns HIGH 50%;

NET "main_00/top_00/iobs_00/data_path_iobs_00/v4_dqs_iob3/DDR_DQS"
OFFSET=IN 1 ns AFTER "sysclk_in";
without any results.

i also tryed a FROM TO constraint like this:
TIMESPEC TS_offset = FROM "clk0_grp" to "IN_DDR_grp" 2.781 ns;
without any results.

with all the tries i have done so far, not even the time of the
violation changes.

has anyone please some suggestions what else i could try, or how this
has to be done?


thanks a lot in advance,

paul


Article: 124455
Subject: Answer: maximum number of state machines in a current chip: > 500k
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Sat, 22 Sep 2007 07:49:35 -0700
Links: << >>  << T >>  << A >>
Hi,
Here is the answer to the maximum number of state machines in a
current chip: > 500k.

My original answer posing has some errors.

1. It is L2 cache that uses a lot of state machines;
http://en.wikipedia.org/wiki/Cache_coherence

2. IBM/Intel uses MESI protocol (4 states: Modified, Exclusive, Shared
and
Invalid);
http://en.wikipedia.org/wiki/MESI_protocol


3. Please visit Intel product website to get the latest news:
http://download.intel.com/products/processor/xeon/7300_prodbrief.pdf


4. "with up to 8 MB of L2 cache per processor" and 4 processors.
It means 4*8MB = 32MB L2 cache;

5. L2 cache is divided into data L2 cache and instruction L2 cache and
only data L2 cache uses MESI protocol.

6. Each 32Bytes is a cache line;

7. 32MB/2/32 = 500k cache lines in data L2 cache and 500k state
machines using MESI protocol.

8. L1/L3 cache and instruction L2 cache use several independent 1-bit
flip-flops to recode their states so that they are not counted as
state machines.

The final answer is:
There is at least 500k state machines in Intel chip.

a. It is available to every users in the topics groups;
b. They are written in Verilog, not in VHDL;
c. FPGA has never had a design using L2 cache.

Weng


Article: 124456
Subject: Re: Answer: maximum number of state machines in a current chip: > 500k
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Sat, 22 Sep 2007 17:37:19 +0100
Links: << >>  << T >>  << A >>
On Sat, 22 Sep 2007 07:49:35 -0700, 
Weng Tianxiang <wtxwtx@gmail.com> wrote:
>The final answer is:
>There is at least 500k state machines in Intel chip.

>a. It is available to every users in the topics groups;
Likewise, the mediaeval discussions about how many angels
can dance on the head of a pin are accessible to all.
In both cases, most of us don't care.

>b. They are written in Verilog, not in VHDL;
Utterly unimportant, and possibly not even true.
Intel uses a range of proprietary in-house tools
and languages in addition to Verilog.

>c. FPGA has never had a design using L2 cache.
Even if that is true, I defy you to prove it.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 124457
Subject: Xilinx Microblaze EDK and Virtex5/LXT TEMAC core?
From: "Helpme" <helpme@nowhere.net>
Date: Sat, 22 Sep 2007 16:39:28 GMT
Links: << >>  << T >>  << A >>
I've looked through Xilinx's website, but I can't determine whether the 
embedded
10/100/1000 gigabit MAC is supported in the EDK.

The reference designs and various appnotes only cover the embedded TEMAC
only the Virtex4/FX platform (PowerPC).  But I found nothing on using
the embedded TEMAC in a Microblaze environment.

Can it be done?  Can the Virtex5/LXT's embedded TEMAC be put into
an EDK-project?  Does it have the same level of embedded/OS device-driver 
support
as the TEMAC on PowerPC? 



Article: 124458
Subject: Re: Gated Clock Problems
From: mk <kal*@dspia.*comdelete>
Date: Sat, 22 Sep 2007 09:45:43 -0700
Links: << >>  << T >>  << A >>
On Sat, 22 Sep 2007 00:12:42 +0200, Stef
<stef33d@yahooI-N-V-A-L-I-D.com.invalid> wrote:
>
>So far I've only seen talk of violated setup times in relation with the
>metastability problem. No problems with hold times?
>

Exactly the same problems with hold  times. Actually the truth is
there are no such things as setup & hold times, there is only one data
valid window where the data should not change in a window near (not
necessarily around) the clock in order not to change the clk to Q
delay more than a certain percentage.

Article: 124459
Subject: Does Modelsim work under Windows Vista?
From: "Helpme" <helpme@nowhere.net>
Date: Sat, 22 Sep 2007 17:02:02 GMT
Links: << >>  << T >>  << A >>
Xilinx's ISE 9.2 now supports Windows Vista (32-bit only.)

Do other tools like (Mentor Modelsim and Xilinx XPS/EDK) run under Windows 
Vista? 



Article: 124460
Subject: CRC calculation of Virtex 4 bitstream
From: lembke.stefan@googlemail.com
Date: Sat, 22 Sep 2007 10:18:17 -0700
Links: << >>  << T >>  << A >>
hi.
i have to calculate the crc checksums of a virtex 4 bitstream. there
are two ckecksums: one direct after the configuration frames and one
at the end of the bitstream.
no i want to know, if all bytes are used to generate the checksum?
i already implemented the an algorithm, whch works fine with an test
input. but when i try to recalculate a checksum of a bitfile, it does
not match ... the algorithm i use is from rocksoft:

http://www.ross.net/crc/download/crc_v3.txt

i use it with the parameters for crc32:
Poly   : 04C11DB7
initial value 0xFFFFFFFF
input is reflected
checksum reflected on end of generation
checksum xored with FFFFFFFF


 maybe you can help me.


Article: 124461
Subject: Re: Does Modelsim work under Windows Vista?
From: "John Retta" <jretta@rtc-inc.com>
Date: Sat, 22 Sep 2007 11:49:00 -0600
Links: << >>  << T >>  << A >>
I bought a laptop with Microsoft Vista Home,
installed Modelsim PE 6.3a , and ran without
problem.

-- 
Regards,
John Retta
Owner and Designer
Retta Technical Consulting Inc.

email : jretta@rtc-inc.com
web :  www.rtc-inc.com


"Helpme" <helpme@nowhere.net> wrote in message 
news:eUbJi.28321$eY.3105@newssvr13.news.prodigy.net...
> Xilinx's ISE 9.2 now supports Windows Vista (32-bit only.)
>
> Do other tools like (Mentor Modelsim and Xilinx XPS/EDK) run under Windows 
> Vista?
> 



Article: 124462
Subject: Re: Answer: maximum number of state machines in a current chip: > 500k
From: "John Retta" <jretta@rtc-inc.com>
Date: Sat, 22 Sep 2007 11:53:46 -0600
Links: << >>  << T >>  << A >>
Which leads us to another interesting question ....

What are the maximium number of lemons that
the human mind can imagine being rotated
simultaneously?

[Please note the lemons can not be bruised.
This is a degenerate case that the theorem does
not apply]

-- 
Regards,
John Retta
Owner and Designer
Retta Technical Consulting Inc.

email : jretta@rtc-inc.com
web :  www.rtc-inc.com


"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message 
news:1190472575.025542.322800@w3g2000hsg.googlegroups.com...
> Hi,
> Here is the answer to the maximum number of state machines in a
> current chip: > 500k.
>
> My original answer posing has some errors.
>
> 1. It is L2 cache that uses a lot of state machines;
> http://en.wikipedia.org/wiki/Cache_coherence
>
> 2. IBM/Intel uses MESI protocol (4 states: Modified, Exclusive, Shared
> and
> Invalid);
> http://en.wikipedia.org/wiki/MESI_protocol
>
>
> 3. Please visit Intel product website to get the latest news:
> http://download.intel.com/products/processor/xeon/7300_prodbrief.pdf
>
>
> 4. "with up to 8 MB of L2 cache per processor" and 4 processors.
> It means 4*8MB = 32MB L2 cache;
>
> 5. L2 cache is divided into data L2 cache and instruction L2 cache and
> only data L2 cache uses MESI protocol.
>
> 6. Each 32Bytes is a cache line;
>
> 7. 32MB/2/32 = 500k cache lines in data L2 cache and 500k state
> machines using MESI protocol.
>
> 8. L1/L3 cache and instruction L2 cache use several independent 1-bit
> flip-flops to recode their states so that they are not counted as
> state machines.
>
> The final answer is:
> There is at least 500k state machines in Intel chip.
>
> a. It is available to every users in the topics groups;
> b. They are written in Verilog, not in VHDL;
> c. FPGA has never had a design using L2 cache.
>
> Weng
> 



Article: 124463
Subject: Re: Answer: maximum number of state machines in a current chip: > 500k
From: Evan Lavelle <nospam@nospam.com>
Date: Sat, 22 Sep 2007 23:09:48 +0100
Links: << >>  << T >>  << A >>
At last - something interesting in this thread.

On Sat, 22 Sep 2007 17:37:19 +0100, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:

>On Sat, 22 Sep 2007 07:49:35 -0700, 
>Weng Tianxiang <wtxwtx@gmail.com> wrote:
>>The final answer is:
>>There is at least 500k state machines in Intel chip.

Why? Wouldn't the smart thing be to build *one* cache coherency
controller in your chip, and to save your 2 state bits as two extra
bits in the 256 memory bits in your cache block?

>>a. It is available to every users in the topics groups;
>Likewise, the mediaeval discussions about how many angels
>can dance on the head of a pin are accessible to all.
>In both cases, most of us don't care.

Actually, to the religiously inclined (among whose number I am not,
alas, to be counted) this is potentially a very interesting question.
The debate was actually about whether or not Angels had a corporeal
existence; the title was just whimsy. Thomas Aquinas's answer, for the
case of a pinhead which was a geometrical point, was, I think, 'one'. 

So, maybe there was something fundamental we missed in the original
question. Was it just an allegory? One FSM, one Angel. Spooky.

Article: 124464
Subject: Re: CRC calculation of Virtex 4 bitstream
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sat, 22 Sep 2007 15:27:49 -0700
Links: << >>  << T >>  << A >>
lembke.stefan@googlemail.com wrote:
> hi.
> i have to calculate the crc checksums of a virtex 4 bitstream. 

http://groups.google.com/groups?q=vhdl+crc+ethernet+bit+order

Article: 124465
Subject: Re: Looking for fast AES cores with low latency
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Sat, 22 Sep 2007 18:18:19 -0800
Links: << >>  << T >>  << A >>
Allan Herriman wrote:

(snip)

> I wish it could work that way.  But the problem is that you don't use
> 10Gb/s encryptors to encrypt "documents", just a single continuous
> stream (or context) at 10Gb/s.

> Well, at least that's the way our customers use them.

I would think that would be dangerous with block chaining,
if you miss one block you are stuck.  Presumably with
error correction it can work.

Still, it seems surprising that you have only one stream.

> On a brighter note, it is possible to interleave CFB, so that each
> "engine" has to sample every 2nd (for two way interleave) 128 bit
> block.  This is discussed in Schneier.

I would think you would want more than two way, though.

-- glen



Article: 124466
Subject: Any advice on Steve Kilts' "Advanced FPGA Design: Architecture, Implementation,
From: James Peters <james@nospam.com>
Date: Sun, 23 Sep 2007 14:55:58 +1000
Links: << >>  << T >>  << A >>
Greetings,

Have any of you read Steve Kilts' book "Advanced FPGA Design: 
Architecture, Implementation, and Optimization"? If so, I'm interested 
in your opinion. I consider myself an intermediate level logic designer, 
and am looking for books that will help me to understand the finer 
points of reliably getting a synthesizable design that works under 
behavioral simulation to one that works in an FPGA. I have not been very 
impressed with some of the FPGA books out there. If people think that 
this book is worth the money, please let us all know.

Thanks and regards,
James.

Article: 124467
Subject: Re: Gated Clock Problems
From: vasile <piclist9@gmail.com>
Date: Sun, 23 Sep 2007 06:51:19 -0000
Links: << >>  << T >>  << A >>
On Sep 20, 5:41 am, "Mike Lewis" <some...@micrsoft.com> wrote:
> "vasile" <picli...@gmail.com> wrote in message
>
> news:1190286570.416365.21640@19g2000hsx.googlegroups.com...
>
> > Data on D must be stable before CLK, else you'll got garbage,
> > scientificaly called "metastability" problems.
> >http://www.interfacebus.com/Design_MetaStable.html
>
> > Vasile
>
> I feel I need to argue this morning ... you won't get garbage. If you
> violate setup, the output will go metastable for a short period of time and
> then settle on either the previous value or the new value.

Right. This could be defined as a glitch if it's short enough and a
glitch is garbage if it's propagate further in the logic design. Is
just a way of interpretation.

I think we have not argued at all.

Vasile


The metastability
> will be so short in duartion you may as well ignore is effect unless you
> have a clock period above 500Mhz.
>
> Mike



Article: 124468
Subject: Xilinx GTP based serial link
From: Sanka Piyaratna <jayasanka.piyaratna@gmail.com>
Date: Sun, 23 Sep 2007 18:50:39 +0930
Links: << >>  << T >>  << A >>
Hi everyone,

I am investigating about the best communication link protocol for my 
high throughput data link. I am required to support >= 2.0Gb/s average 
transfer rate and one way only optical cables need to carry data (I 
don't have a feedback link to the transmitter) . I would like to have a 
mechanism to control the frame sizes and widely available FPGA cores 
would be a bonus. I was thinking about RapidIO or FPDP and I am not sure 
if there are any better protocols around. Any help would be greatly 
appreciated.

Thank you.

Regards,

Sanka

Article: 124469
Subject: Re: Gated Clock Problems
From: Marlboro <ccon67@netscape.net>
Date: Sun, 23 Sep 2007 08:41:20 -0700
Links: << >>  << T >>  << A >>
On Sep 23, 1:51 am, vasile <picli...@gmail.com> wrote:
> On Sep 20, 5:41 am, "Mike Lewis" <some...@micrsoft.com> wrote:
>
> > "vasile" <picli...@gmail.com> wrote in message
>
> >news:1190286570.416365.21640@19g2000hsx.googlegroups.com...
>
> > > Data on D must be stable before CLK, else you'll got garbage,
> > > scientificaly called "metastability" problems.
> > >http://www.interfacebus.com/Design_MetaStable.html
>
> > > Vasile
>
> > I feel I need to argue this morning ... you won't get garbage. If you
> > violate setup, the output will go metastable for a short period of time and
> > then settle on either the previous value or the new value.
>
> Right. This could be defined as a glitch if it's short enough and a
> glitch is garbage if it's propagate further in the logic design. Is
> just a way of interpretation.
>
> I think we have not argued at all.
>
> Vasile
>
> The metastability
>
>
>
> > will be so short in duartion you may as well ignore is effect unless you
> > have a clock period above 500Mhz.
>
> > Mike- Hide quoted text -
>
> - Show quoted text -

What happened to the OP, he has just vanished after the first post?



Article: 124470
Subject: Re: Gated Clock Problems
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Sun, 23 Sep 2007 09:00:41 -0700
Links: << >>  << T >>  << A >>
Hi,
I am not interested in metastability, not because it is very complex,
but because we cannot do anything to eliminate it.

Let us help the problem poster to resolve his problem:
How to differentiate two closely pulses.

The only method to resolve it is:
1. Using as high frequency as possible;
2. Feed two pulses to D input terminals for two adjacent FF,
respectively;
3. When there are different outputs, it says one is faster than
another;
4. Its time resolution is limited by the input clock frequency: 1/f in
second.
If a 400MHz frequency is used, its time resolution is 1/400M in
second.

One cannot expect to get a 1/800M in second resolution with 400MHz
clock.

With introduction of time resolution, we don't have to talk about
metastability.

The reason is:
1. If a metastability happens in clock 1; 2 FF would still tell the
differences between them, because output data are not reached to a
stable data, either 0 or 1. If one were 1, it tells the truth: it is
faster than another whose data is 0. If not, it tells the truth that
both are equal because of time resolution.
2. With clock 2, its data input absolutely meets set up time and clock
2 outputs are stable and tell the truth: if one is 0, another is 1, it
determine which is faster. If data are the same, it cannot tell the
difference between them in the time resolution.

The way I suggested is a synchronous process and has no violations of
any design principles.

Any comments?

Weng


Article: 124471
Subject: Re: Gated Clock Problems
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Sun, 23 Sep 2007 19:19:06 +0000 (UTC)
Links: << >>  << T >>  << A >>
Marlboro <ccon67@netscape.net> wrote:

> What happened to the OP, he has just vanished after the first post?

Ask once, read never...

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 124472
Subject: Re: Gated Clock Problems
From: Eric Smith <eric@brouhaha.com>
Date: Sun, 23 Sep 2007 12:52:34 -0700
Links: << >>  << T >>  << A >>
Weng Tianxiang <wtxwtx@gmail.com> writes:
> I am not interested in metastability, not because it is very complex,
> but because we cannot do anything to eliminate it.

If something is a problem but can't be eliminated, that doesn't mean that
it should be ignored.  There are techniques for minimizing the impact
when it does occur.

Article: 124473
Subject: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
From: Eric Smith <eric@brouhaha.com>
Date: Sun, 23 Sep 2007 12:54:08 -0700
Links: << >>  << T >>  << A >>
Antti <Antti.Lukats@googlemail.com> writes:
> If this is really so - this can only be verified when buying Actel M1
> silicon and non-M1 at same time from same vendor, then it means that
> there really is no hidden fee any more in the ARM softcore.

No, it may mean that the chip vendor is absorbing the license cost, and
making more profit on the non-M1.

Article: 124474
Subject: ANNOUNCE: Embedded hw/sw developer freebies by Nikolaos Kavvadias
From: Uncle Noah <nkavv@skiathos.physics.auth.gr>
Date: Sun, 23 Sep 2007 19:44:00 -0700
Links: << >>  << T >>  << A >>
Hello fellow developers, users and friends

This is a list of free (some of them GPL'ed) tools that I have written
over the course of the few last years. You can access and download the
tools from:

http://electronics.physics.auth.gr/tomeas/en/kavvadias.html

Everyone is welcome to comment on the tools by posting to this thread
or via email.

Enjoy
Nikolaos Kavvadias
Computer Architecture Developer and Compiler Specialist
Ph.D. candidate

======================================================
= List of architecture, compiler, and hardware tools =
======================================================

1. A data-dependence graph construction pass for the Machine-SUIF
research compiler
infrastructure, called bbpart. It generates a textual representation
for the data dependence graphs of the basic blocks found in all the
procedures of a given ANSI C source file. There is also an older
version that generates a visual representation in the VCG format for
each DDG.

2. SUIFvm instruction set support for the CDIF (Connected Dataflow
Idiom Finder) instruction generation tool.

3. A patch for the OLIVE code generator-generator tool, currently only
available as part of the SPAM research compiler, which is built on top
of SUIF 1.

4. Instruction-accurate ArchC model for the (integer ISA) DLX
processor.

5. A patch applying modifications to archc-2.0beta2 so that it can
compile with a gcc-2.x-based compiler.

6. An implementation of a hardware looping unit (HWLU) in VHDL had
been posted to OpenCores around April 2004. The HWLU can be used for
developing non-programmable engines for multi-dimensional signal
processing algorithms that are comprised of fully nested loops. It is
accompanied by software tools for generating parts of the VHDL
description of the hardware.

There is also a couple of specialized compiler passes related to zero-
overhead loop control (ZOLC) in embedded programmable processors.

7. tcfggen is an analysis pass built to be used with the SUIF2/
MachSUIF2 compiler infrastructure. tcfggen performs (natural) loop
analysis in order to map the control flow of a given optimization unit
(i.e. a procedure in the input program) to its task control flow graph
(TCFG). It is also used to pass the static information for the loops
in the given procedure to the subsequent stage(s) in the form of
pseudo-instructions.

8. zolcgen is a transformation pass operating on SUIFrm assembly
files, utilizing the SALTO (System for Assembly Language
Transformation and Optimization) API. This pass produces the actual
ZOLC initialization code that has to be inserted in a preceding basic
block to the loop nest to update the ZOLC storage resources and is
typically the first basic block of the targeted procedure.

9. Kernel benchmarks for evaluating the ZOLC optimizations.




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search