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John_H wrote: > <dudesinmexico@gmail.com> wrote in message > news:1190849356.286625.69510@d55g2000hsg.googlegroups.com... > >>Ray, nice to hear from you. Yes, I have considered BRAMs as lookup >>tables. >>In fact, we noticed that Synplify does something pretty cool: it packs >>two multipliers >>in a single BRAM18, using one port for each multiplier. Of course this >>is possible since >>they share the same table. >>According to the documentation, one can use a BRAM36 as two BRAM18s, >>however >>PlanAhead refuses to place a pblock with two BRAM18s on any area with >>just one BRAM36. >>This could be either a PlanAhead bug or simply that the BRAM36 still >>has just two ports... > > > From p 125 of ug190.pdf (v3.1 Virtex-5 User Guide, 9/11/2007) > > Two RAMB18s can be placed in the same RAMB36 location by using the BEL > UPPER/LOWER constraint: > inst "my_ramb18" LOC = RAMB36_X0Y0 | BEL = UPPER > inst "my_ramb18" LOC = RAMB36_X0Y0 | BEL = LOWER > > which is echoed in Ansew Record 25115 > > http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=25115 > > though I think the note's author forgot to write UPPER for the last line. > Darned cut & paste! > > Whether PlanAhead supports these constraints natively isn't obvious. Ask > the hotline or your FAE! > > - John_H > > Oops, I misread what you were saying here, I thought you were trying to use the BRAM36 dual ported. I don't often use plan ahead. Putting the bel constraints on instantiated BRAM18's works fine for placing them together.Article: 124576
On Sep 24, 11:01 am, Jon Elson <el...@wustl.edu> wrote: > vasile wrote: > > Data on D must be stable before CLK, else you'll got garbage, > > scientificaly called "metastability" problems. > >http://www.interfacebus.com/Design_MetaStable.html > > Actually, the metastability window on modern FPGA flip-flops > is INCREDIBLY small, probably less than 10 ps on most modern architectures. > > Jon After measuring Virtex 2 Pro behavior, I calculated the metastability capture window to be less than 0.1 femtoseconds. Pretty small indeeed. Peter Alfke (back from vacation)Article: 124577
Hello. I'm getting a better outline of what's available and the differences between the different options, such as FPGAs and CPLDs. Although, I've just come across Alteras "Nios II Embedded Processor" and to be honest it's thrown me off completely. - What is a soft-core processor? - It seems that Nios II isn't a physical product I buy, it appears to be an emulator running on top of any FPGA (Stratix, Cyclone etc...)? - Programming the Nios II is done through the Nios II IDE, although this uses C/C++? Is this then converted into a netlist (along with the Nios core) to run on a certain FPGA? - Does using Nios II mean a reduction in performance in comparison to an FPGA/CPLD? Thank you. Nick.Article: 124578
On Sep 27, 7:34 am, NickNitro <NickHo...@googlemail.com> wrote: > Hello. > > I'm getting a better outline of what's available and the differences > between the different options, such as FPGAs and CPLDs. Although, I've > just come across Alteras "Nios II Embedded Processor" and to be honest > it's thrown me off completely. > > - What is a soft-core processor? A synthesizable implementation of a processor microarchitecture, probably at the RT level. It is supposed to be targetable across different technologies (FPGAs and or standard cell ASICs). > - It seems that Nios II isn't a physical product I buy, it appears to > be an emulator running on top of any FPGA (Stratix, Cyclone etc...)? It is a soft-core processor written in the VHDL hardware description language. > - Programming the Nios II is done through the Nios II IDE, although > this uses C/C++? Is this then converted into a netlist (along with the > Nios core) to run on a certain FPGA? As Nios-II is a processor, you can use standard ways to program (HLL down to object code or assembly down to object code). The program memory is kept within the embedded block memories of the FPGA or could be SRAM, SDRAM etc storage. > - Does using Nios II mean a reduction in performance in comparison to > an FPGA/CPLD? It means that it is a way to bind the available FPGA resources to do something for you. > > Thank you. > Nick. You are welcome. Do you come from a COTS (commercial-off-the-shelf) discipline? Your enquiries are archetypical of this kind of engineers (or students).Article: 124579
On Sep 27, 6:08 am, Uncle Noah <nk...@skiathos.physics.auth.gr> wrote: <snip> >>It is supposed to be targetable across different technologies (FPGAs and or standard cell ASICs). Ok, that clears quite a bit up! >>It is a soft-core processor written in the VHDL hardware description language. So essentially I'm buying the 'blueprint' as it were for a RISC processor. >>It means that it is a way to bind the available FPGA resources to do something for you. Ok, again that clears much up. But programming my algorithms in VHDL then placing them on an FGPA would result in far superior than using the Nios II core? It is probably a 'how long is a piece of string' type of question, but what performance penalties are there in using the Nios II core in comparison to direct VHDL programming? >>Do you come from a COTS (commercial-off-the-shelf) discipline? If that refers to a software engineer (typically for me ASM & C/C++), then yes. :) Thanks again, Nick.Article: 124580
Sorry, I forgot to add how does the C2H fit into the Nios architecture?Article: 124581
Hi, I have a behavior in Synplify Pro for Actel Fpgas I would call a bug (seen in each old version I could find up to the newest 9.0) If having a register file which is accessed only in words with fixed width and an asynchronous reset, synplify detects a ram structure in the compile step. If the ram isn't used later (due to constrained ram- style register, or due to resource usage), synplify uses FF without an asynchronous reset for the register bank and a hell of logic to force the circuit to behave like it uses asynchnous reset. I have a simple example(6x8 bit), were synplicity uses twice the register normaly necessary. This behavior is only seen when using a technology which provides ram at all. So I like to know if there is a reason to consider this a problem of the tech library? Is there anybody out seeing the same behavior in other technologies than Actel (APA, AX)? regards ThomasArticle: 124582
> >>It means that it is a way to bind the available FPGA resources to do something for you. > > Ok, again that clears much up. But programming my algorithms in VHDL > then placing them on an FGPA would result in far superior than using > the Nios II core? It is probably a 'how long is a piece of string' > type of question, but what performance penalties are there in using > the Nios II core in comparison to direct VHDL programming? If you mean that you are thinking of designing customized hardware for a single purpose (let's say one algorithm) and take advantage of the vast parallelism available in FPGAs, then yes, you can get a far superior than a given soft-core processor. Then again, it is possible that the soft-core lets you "communicate" to your piece of hardware and put it under software control without losing too much. > Thanks again, > Nick. You are welcome.Article: 124583
On Sep 27, 8:34 am, NickNitro <NickHo...@googlemail.com> wrote: > Sorry, I forgot to add how does the C2H fit into the Nios architecture? I believe that you mark a C procedure for hardware implementation. Then the C2H would generate legitimate VHDL for that procedure. Of course it should be carefully written in a C subset or use some form of intrinsics to make this work.Article: 124584
On Sep 27, 6:50 am, Uncle Noah <nk...@skiathos.physics.auth.gr> wrote: > On Sep 27, 8:34 am, NickNitro <NickHo...@googlemail.com> wrote: > > > Sorry, I forgot to add how does the C2H fit into the Nios architecture? > > I believe that you mark a C procedure for hardware implementation. > Then the C2H would generate legitimate VHDL for that procedure. Of > course it should be carefully written in a C subset or use some form > of intrinsics to make this work. Why is Nios required for C2H if C2H creates VHDL code?Article: 124585
> > I believe that you mark a C procedure for hardware implementation. > > Then the C2H would generate legitimate VHDL for that procedure. Of > > course it should be carefully written in a C subset or use some form > > of intrinsics to make this work. > > Why is Nios required for C2H if C2H creates VHDL code? It seems to only be accessible under the Nios-II IDE. Maybe the C2H generates VHDL with taking a certain interface to Nios-II into account. That does not mean that the VHDL generated is not generic (in the sense of needing some strange libraries).Article: 124586
On Sep 27, 7:24 am, Uncle Noah <nk...@skiathos.physics.auth.gr> wrote: > > > I believe that you mark a C procedure for hardware implementation. > > > Then the C2H would generate legitimate VHDL for that procedure. Of > > > course it should be carefully written in a C subset or use some form > > > of intrinsics to make this work. > > > Why is Nios required for C2H if C2H creates VHDL code? > > It seems to only be accessible under the Nios-II IDE. Maybe the C2H > generates VHDL with taking a certain interface to Nios-II into > account. That does not mean that the VHDL generated is not generic (in > the sense of needing some strange libraries). Ok wonderful. Thanks for all your help, it is much appreciated. (-: Nick.Article: 124587
On 27 Sep., 00:20, dudesinmex...@gmail.com wrote: > On Sep 25, 8:48 pm, Marc Randolph <mr...@my-deja.com> wrote: > > > On Sep 25, 4:30 pm, dudesinmex...@gmail.com wrote: > > > > I am looking for open source software for logic minimization (a la > > > espresso) targeted to a lookup table based architecture that can take advantage > > > of six inputs LUTs (as you can imagine I have in mind a LUT6/Virtex 5 > > > implementation). Is there such a beast? > > > Howdy, > > > You peaked my curiosity. Could you explain why you need this? > > Sure. I am working at a Virtex 5 design with *lots* of squarer > circuits (Z=A*B with A=B) where the input > is a signed 9 bit value in the [-255,255] range. I am wondering if > the LUT6 would give any advantage > compared to other implementations. Then, looking at Ray Andraka's page > on multipliers I realized that > a "Partial product LUT multiplier" looks like a good architecture for > the squarer (since A=B the number of LUTs is cut in half), and that > the LUT6 probably does not buy you more than a LUT4 since the carry > chain limits the number of bits to four per slice. > > -Arrigo How about this (A Virtex-5 CLB can be used as an 8 input lookup table): 8 LUTs compute the absolute value of the input. 6*1 LUTs form a lookup table for the lower 6 bits of the result (they depend only on 6 inputs) 1*2 LUTs form a lookup table for bit 6 9*4 LUTs form lookup tables for bits 7 to 15 This is about the size of four partial products, but it might be faster. (Depending of the performance of the CLB-Muxes compared to the carry chain) Kolja SulimmaArticle: 124588
On Sep 26, 1:22 pm, Wei Wang <camww...@gmail.com> wrote:
> On Sep 26, 3:14 pm, Wei Wang <camww...@gmail.com> wrote:
>
>
>
> > On Sep 26, 1:37 pm, Gabor <ga...@alacron.com> wrote:
>
> > > On Sep 25, 6:48 pm, Wei Wang <camww...@gmail.com> wrote:
>
> > > > On Sep 25, 9:31 pm, Gabor <ga...@alacron.com> wrote:
>
> > > > > On Sep 25, 2:12 pm, Weng Tianxiang <wtx...@gmail.com> wrote:
>
> > > > > > On Sep 25, 8:51 am, Wei Wang <camww...@gmail.com> wrote:
>
> > > > > > > All I can find is a one-page specification of "Kingston
> > > > > > > KVR100X64C2/128", but I do not know about the input and output
> > > > > > > interface of this SDRAM, e.g., what are the input and output signals,
> > > > > > > and how the input and output signals are wired into each Synchronous
> > > > > > > DRAM (Infineon HYB39S128800CT-8) module. Many thanks, -Wei
>
> > > > > > Hi,
> > > > > > Go to Infineon or Micron, or Samsung to search for similar SDRAM
> > > > > > chips.
>
> > > > > > Kingston is not a chip manufacture, but a DIMM manufacture.
>
> > > > > > All SDRAM chips are almost same with Micron having the tighest
> > > > > > requirements.
>
> > > > > > You may print Micron 128800CT-8 SDRAM to see if there is a document
> > > > > > over there. Maybe they are all out of date.
>
> > > > > > Weng
>
> > > > > A good source for DIMM data is JEDEC. On their website, jedec.org,
> > > > > you
> > > > > can find standard connections for all standard DIMM types. If you
> > > > > know
> > > > > the type of chip and number of chips on your module you can generally
> > > > > narrow down the choices to one JEDEC standard.
>
> > > > > Their website is a little hard to navigate, but the search feature
> > > > > generally gets you to the information you need, and all of the
> > > > > standards
> > > > > include reference schematics so you can see the chip connections.
>
> > > > > HTH,
> > > > > Gabor- Hide quoted text -
>
> > > > > - Show quoted text -
>
> > > > Thanks Tianxiang and Gabor for your inputs, but I was a little
> > > > confused with the description in Kingston KVR100X64C2/128 "The
> > > > components on this module
> > > > include sixteen 8M x 8-bit (2M x 8-bit x 4 Bank / PC100 components)
> > > > SDRAM in TSOP packages", but when I look at Infineon HYB39S128800CT-8,
> > > > the chip has four banks inside,
> > > > each bank is 8 bits wide with 4M address, so each chip is 4Mx8bitx4,
> > > > which is 16MB. As the Kingston is 128 MB big and it has 8 Infineon
> > > > chips fitted, so I don't see why the KVR specification says the module
> > > > contains sixteeen 8Mx8-bit SDRAM. Should it be 8 16Mx8-bit SDRAM, then
> > > > I could not find this in JEDEC standard while I could find the JEDEC
> > > > standard for sixteen 8Mx8bit? Could somebody give me some hints on
> > > > this, thanks!!!
>
> > > The data sheet also notes:
>
> > > "Note: The module defined in this data sheet is one of several
> > > configurations available under this part number. While all
> > > configurations are compatible, the DRAM combination and/or the
> > > module height may vary from what is described here."
>
> > > I'm not sure what they consider "compatible" in the case of modules
> > > with different memory organizations under the same part number,
> > > but I also noticed that they offer "Free Technical Support".
>
> > > Perhaps someone at Kingston can address the issue?
>
> > > Regards,
> > > Gabor- Hide quoted text -
>
> > > - Show quoted text -
>
> > Many thanks again for your input, I've called Kingston US support line
> > yesterday, but I was told that they could not provide anything in more
> > detail beyond the one-page specification found on their website. I've
> > however managed to find something very similar, such as the Samsung
> > KMM366S1723T datasheet which provides a better view of chip
> > organization.- Hide quoted text -
>
> > - Show quoted text -
>
> The signals are pretty similar in either Samsung or Kingston, but I'm
> not entirely sure with the chip select signals. Just wondering whether
> the select signals should be the same for sdrams with same number of
> chips.
The chip select should be the same for the same total number of
data bits, i.e. # of chips times # bits per chip. If there is
only enough for one bank (or DIMM "side" as it is sometimes called)
only the first chip select is used. When the total number of data
pins is twice the DIMM data width ("two-sided" DIMM) both chip
selects are used.
Article: 124589Thomas Stanka wrote: > Hi, > > I have a behavior in Synplify Pro for Actel Fpgas I would call a bug > (seen in each old version I could find up to the newest 9.0) > > If having a register file which is accessed only in words with fixed > width and an asynchronous reset, synplify detects a ram structure in > the compile step. If the ram isn't used later (due to constrained ram- > style register, or due to resource usage), synplify uses FF without an > asynchronous reset for the register bank and a hell of logic to force > the circuit to behave like it uses asynchnous reset. I have a simple > example(6x8 bit), were synplicity uses twice the register normaly > necessary. This behavior is only seen when using a technology which > provides ram at all. So I like to know if there is a reason to > consider this a problem of the tech library? Is there anybody out > seeing the same behavior in other technologies than Actel (APA, AX)? > > regards Thomas If you don't want a RAM attempted in the first place but the tool is trying anyway, use the syn_ramstyle attribute to force flops, allowing a clean async reset, perhaps.Article: 124590
Hi Everyone, Are there any hardware modules that I can buy to convert a data stream (serial FPDP over fibre) into PCI express and connect to a PC using the PCIe port? I have not been able to find a module that does this and so I am thinking about implementing the conversion in V5 ML555 evaluation board. In this case I need to find a good place to get hold of an serial FPDP core for Virtex 5. Could you please help me with this? Thanks, Regards, SankaArticle: 124591
Hi, I need some help in this design: I use a design in which I have detected some skew problems. I have seen the archive.ucf (with the constraints), so "slew" and "drive" properties are used in some pins. I suppose that these properties are used for delays, but I don't know for what. Can anyone explain me the meaning of these properties? Best RegardsArticle: 124592
On Sep 26, 11:16 am, jon <j...@pyramidemail.com> wrote: > Can anyone help on finding a home for the AlteraStratixGXchips. I > am in a situation where one of my contracted accounts has purchased > the AlteraStratixGXproduct prematurely. They are not going to be > doing the build the product was procured for. Basically they are in > a situation where they will let product go significantly below factory > direct pricing. Please let me know if you know anyone who would be > interested in the following chips. > > 106pcs EP2SGX90FF40C3N > 60pcs EP2C35F672C6N > 400pcs EP2S60F672C5N > > Regards, > Jon E. Hansen > (949)864-7745 I have more excess than originaly thought. I need to move these ASAP, so I will be very flexible on price. 106pcs EP2SGX90FF1508C3N 2pcs EP2S180F1020C3N Jon E. Hansen (949)864-7745 directArticle: 124593
On Sep 27, 12:46 pm, Pablo <pbantu...@gmail.com> wrote: > Hi, I need some help in this design: > > I use a design in which I have detected some skew problems. I have > seen the archive.ucf (with the constraints), so "slew" and "drive" > properties are used in some pins. I suppose that these properties are > used for delays, but I don't know for what. > > Can anyone explain me the meaning of these properties? > > Best Regards For LVCMOS and LVTTL outputs, there are selectable drive strengths ans slew rates (Xilinx parts). SLEW=SLOW or SLEW=FAST select the two possible output slew rates. Unconstrained LVTTL and LVCMOS outputs default to SLEW=SLOW to reduce ground bounce and noise. DRIVE=n, where n is the strength in milliamperes, defines the drive strength. For most outputs the default frive is 12 mA. Available strengths depend on the I/O standard used. In the electrical specifications for your part, there are tables of timing adders for the various output standards, drive strengths and slew rates. It is possible to address skew issues between source-synchronous pins by assigning differing SLEW or DRIVE properties, but it's probably a Band-Aid approach to fixing a problem. Usually, at least in the recent parts containing DCM's, it's better to handle timing shifts with clock phase shifting, or in the newest parts using variable delay elements in the IOB's. Regards, GaborArticle: 124594
please i=B4m very new on this, whats the difference between Xilinx ISE and Xilinx=B4s EDK, and what for is the IP ???Article: 124595
On Sep 27, 12:45 am, Thomas Stanka <usenet...@stanka-web.de> wrote: > Hi, > > I have a behavior in Synplify Pro for Actel Fpgas I would call a bug > (seen in each old version I could find up to the newest 9.0) > > If having a register file which is accessed only in words with fixed > width and an asynchronous reset, synplify detects a ram structure in > the compile step. If the ram isn't used later (due to constrained ram- > style register, or due to resource usage), synplify uses FF without an > asynchronous reset for the register bank and a hell of logic to force > the circuit to behave like it uses asynchnous reset. I have a simple > example(6x8 bit), were synplicity uses twice the register normaly > necessary. This behavior is only seen when using a technology which > provides ram at all. So I like to know if there is a reason to > consider this a problem of the tech library? Is there anybody out > seeing the same behavior in other technologies than Actel (APA, AX)? > > regards Thomas Can you post some code? It is difficult to understand what you want, let alone the problem with what you are getting, without seeing some example code. Also, does your target even support async reset on RAMs? AndyArticle: 124596
John_H wrote: > Have you ever priced support? > With the software license comes an expectation for quick, accurate > support. If anybody and their brother got support free of charge, the > cost to support the hobbyist in designs becomes severe. You have a bit of a point, but these tools and the methodology of FPGAs are WAY too arcane for the average PIC-chip hobbyist. And, I have to say that my several experiences with Xilinx tech support have not been stellar. The last one turned up a major discrepancy between data sheet power consumption and what actually happens on the 5 V XC9500 CPLDs, and they told me flatly they would not even correct the on-line data sheets! Yes, sure, an obsolete product, but they still sell them and I'm still buying them. Most of the other times I've needed Xilinx tech support, I ended up figuring out the problem before they did - if ever. JonArticle: 124597
I am simulating the PowerPC and can't find the damn program counter. I have looked in the reference manuals that come with the EDK but can't find any helpful info!! Anyone know where to point me? I am using ModelSim by the way. Thanks!Article: 124598
Andy Peters wrote: > > Somebody PLEASE explain to me why a license key is needed for software > that does one thing only: implement designs in the vendor's specific > logic family. > > I can't use Altera's software to do Xilinx chips, nor can I use it to > play Doom 3, nor can I use it to make my morning coffee. So why why > why why why do the FPGA vendors insist on license keys for their > tools? My guess is that these complete packages DO contain some software components that can potentially be pulled out and used standalone. Some components are bought outside, like Xilinx uses ModelSim. (I don't know why anyone would WANT to use ModelSim, it seems insanely creaky and cumbersome, and I have to relearn the DAMN thing every time I use it.) But, I'm sure that it and other components could be pulled out and used separately, given the right support files and libraries. Actually, if you have the entire package with the license key, you can probably use those packages separely, too, if you know enough. So, I think it is mostly smoke - anyone who actually knows enough about the package's internals could circumvent the security anyway. JonArticle: 124599
On Sep 27, 2:17 pm, emr...@gmail.com wrote: > please i=B4m very new on this, whats the difference between Xilinx ISE > and Xilinx=B4s EDK, and what for is the IP ??? Have you taken a look at Xilinx' website? There is a wealth of infomation there...but.... EDK =3D Used to develop FPGA systems that use either a MicroBlaze soft processor or a PowerPC hard processor. ISE =3D Used to develop FPGA or CPLD systems that may or may not contain a processor (probably don't - that is why the EDK is nice). IP =3D Intellectual Property...or specifically related to what you are asking...predesigned hardware blocks that do some prescribed function.
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