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Threads Starting Aug 2007

122583: 07/08/01: Ioiod: Xilinx Webpack 9.2 and Windows 2000 Pro?
    122593: 07/08/01: HT-Lab: Re: Xilinx Webpack 9.2 and Windows 2000 Pro?
        122634: 07/08/01: Eric Smith: Re: Xilinx Webpack 9.2 and Windows 2000 Pro?
            122656: 07/08/02: Brian Drummond: Re: Xilinx Webpack 9.2 and Windows 2000 Pro?
                122665: 07/08/02: Duane Clark: Re: Xilinx Webpack 9.2 and Windows 2000 Pro?
    122607: 07/08/01: jacobusn@xilinx.com: Re: Xilinx Webpack 9.2 and Windows 2000 Pro?
    122611: 07/08/01: <ghelbig@lycos.com>: Re: Xilinx Webpack 9.2 and Windows 2000 Pro?
122586: 07/08/01: Ioiod: Altera Cyclone II and Cyclone III "distributed" RAM?
    122587: 07/08/01: Ben Twijnstra: Re: Altera Cyclone II and Cyclone III "distributed" RAM?
    122588: 07/07/31: Tommy Thorn: Re: Altera Cyclone II and Cyclone III "distributed" RAM?
    122641: 07/08/02: Paul Leventis: Re: Altera Cyclone II and Cyclone III "distributed" RAM?
122591: 07/08/01: Dolphin: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
    122597: 07/08/01: Georg Acher: Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
        122602: 07/08/01: Georg Acher: Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
    122598: 07/08/01: Dolphin: Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
    122601: 07/08/01: Dolphin: Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
    122603: 07/08/01: Dolphin: Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
    122708: 07/08/03: John_H: Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
    122759: 07/08/06: Dolphin: Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
122596: 07/08/01: <martin.leibetseder@ge.com>: Fatal Error ISE 9.1
    122612: 07/08/01: davide: Re: Fatal Error ISE 9.1
    122614: 07/08/01: johnp: Re: Fatal Error ISE 9.1
122610: 07/08/01: Christopher Cole: Xilinx Webpack for Linux 64 bit?
    122613: 07/08/01: davide: Re: Xilinx Webpack for Linux 64 bit?
    122615: 07/08/01: <ghelbig@lycos.com>: Re: Xilinx Webpack for Linux 64 bit?
    122635: 07/08/01: Eric Smith: Re: Xilinx Webpack for Linux 64 bit?
122617: 07/08/01: sriman: help on basics of ethernet interface
122620: 07/08/01: <ctaniguchi1@gmail.com>: Static Timing Analysis Using Primetime for FPGAs
    122622: 07/08/01: Mike Lewis: Re: Static Timing Analysis Using Primetime for FPGAs
        122697: 07/08/03: Evan Lavelle: Re: Static Timing Analysis Using Primetime for FPGAs
            122699: 07/08/03: Mike Treseler: Re: Static Timing Analysis Using Primetime for FPGAs
                122701: 07/08/03: Evan Lavelle: Re: Static Timing Analysis Using Primetime for FPGAs
                    122705: 07/08/03: Mike Treseler: Re: Static Timing Analysis Using Primetime for FPGAs
    122623: 07/08/01: <ctaniguchi1@gmail.com>: Re: Static Timing Analysis Using Primetime for FPGAs
    122624: 07/08/01: Jon Beniston: Re: Static Timing Analysis Using Primetime for FPGAs
    122625: 07/08/01: Mike Treseler: Re: Static Timing Analysis Using Primetime for FPGAs
    122640: 07/08/02: Paul Leventis: Re: Static Timing Analysis Using Primetime for FPGAs
    122643: 07/08/02: Tommy Thorn: Re: Static Timing Analysis Using Primetime for FPGAs
    122644: 07/08/02: Paul Leventis: Re: Static Timing Analysis Using Primetime for FPGAs
    122663: 07/08/02: <dkarchmer@gmail.com>: Re: Static Timing Analysis Using Primetime for FPGAs
    122677: 07/08/02: <jjohnson@cs.ucf.edu>: Re: Static Timing Analysis Using Primetime for FPGAs
122647: 07/08/02: mfgunes: Writing data to bram with microblaze
    122838: 07/08/08: svenand: Re: Writing data to bram with microblaze
122650: 07/08/02: <jcr_alr@xplornet.com>: DOSFS for EDK
    122651: 07/08/02: Antti: Re: DOSFS for EDK
    122653: 07/08/02: Antti: Re: DOSFS for EDK
122657: 07/08/02: eromlignod: Inputs as an Array in Verilog??
    122658: 07/08/02: Jonathan Bromley: Re: Inputs as an Array in Verilog??
122664: 07/08/02: Jeff Cunningham: V4 DSOCM always reads back zeroes
    122731: 07/08/05: Jeff Cunningham: Re: V4 DSOCM always reads back zeroes
122666: 07/08/02: vasile: Altera-Xilinx interfacing SERDES transcievers problem
    122678: 07/08/02: <jjohnson@cs.ucf.edu>: Re: Altera-Xilinx interfacing SERDES transcievers problem
    122693: 07/08/03: dimtsios@ix.netcom.com: Re: Altera-Xilinx interfacing SERDES transcievers problem
    122710: 07/08/04: vasile: Re: Altera-Xilinx interfacing SERDES transcievers problem
122667: 07/08/02: Richard Klingler: Forwarding engines
122675: 07/08/02: EEngineer: Download the contents of the FPGA's RAM block
    122729: 07/08/05: fpgauser: Re: Download the contents of the FPGA's RAM block
    122742: 07/08/06: EEngineer: Re: Download the contents of the FPGA's RAM block
    122748: 07/08/06: makhan: Re: Download the contents of the FPGA's RAM block
    122766: 07/08/06: EEngineer: Re: Download the contents of the FPGA's RAM block
        122769: 07/08/06: Matthew Hicks: Re: Download the contents of the FPGA's RAM block
    122835: 07/08/08: makhan: Re: Download the contents of the FPGA's RAM block
122676: 07/08/02: cpope: V4FX PPC suspend/resume
    122704: 07/08/03: austin: Re: V4FX PPC suspend/resume
        122706: 07/08/03: Matthew Hicks: Re: V4FX PPC suspend/resume
            122707: 07/08/03: austin: Re: V4FX PPC suspend/resume
        122711: 07/08/04: cpope: Re: V4FX PPC suspend/resume
            122903: 07/08/09: Peter Ryser: Re: V4FX PPC suspend/resume
122679: 07/08/02: fpgauser: Spartan 3E starter kit DDR SDRAM
    122680: 07/08/02: Tommy Thorn: Re: Spartan 3E starter kit DDR SDRAM
    122689: 07/08/03: jacobusn@xilinx.com: Re: Spartan 3E starter kit DDR SDRAM
    122691: 07/08/03: jacobusn@xilinx.com: Re: Spartan 3E starter kit DDR SDRAM
    122716: 07/08/04: fpgauser: Re: Spartan 3E starter kit DDR SDRAM
    122724: 07/08/04: fpgauser: Re: Spartan 3E starter kit DDR SDRAM
122686: 07/08/03: sriman: camera module interface to FPGA
    122688: 07/08/03: David Binnie: Re: camera module interface to FPGA
122709: 07/08/03: <vkr101@gmail.com>: World's 1st FPGA Centric Portal goes LIVE!!
122713: 07/08/04: Eli Billauer: SDR SDRAM controller for Xilinx Spartan-3E
    122714: 07/08/04: Mike Treseler: Re: SDR SDRAM controller for Xilinx Spartan-3E
    122715: 07/08/04: Eli Billauer: Re: SDR SDRAM controller for Xilinx Spartan-3E
    122717: 07/08/04: jacobusn@xilinx.com: Re: SDR SDRAM controller for Xilinx Spartan-3E
    122754: 07/08/06: Guru: Re: SDR SDRAM controller for Xilinx Spartan-3E
    122755: 07/08/06: Martin Thompson: Re: SDR SDRAM controller for Xilinx Spartan-3E
        122791: 07/08/07: PFC: Re: SDR SDRAM controller for Xilinx Spartan-3E
            122802: 07/08/07: Georg Acher: Re: SDR SDRAM controller for Xilinx Spartan-3E
                122813: 07/08/07: PFC: Re: SDR SDRAM controller for Xilinx Spartan-3E
                    122819: 07/08/07: Georg Acher: Re: SDR SDRAM controller for Xilinx Spartan-3E
            122851: 07/08/08: Antonio Pasini: Re: SDR SDRAM controller for Xilinx Spartan-3E
    122776: 07/08/06: Andy Peters: Re: SDR SDRAM controller for Xilinx Spartan-3E
    122790: 07/08/07: Eli Billauer: Re: SDR SDRAM controller for Xilinx Spartan-3E
    122797: 07/08/07: Guru: Re: SDR SDRAM controller for Xilinx Spartan-3E
    122880: 07/08/09: Guru: Re: SDR SDRAM controller for Xilinx Spartan-3E
    122950: 07/08/12: <ghelbig@lycos.com>: Re: SDR SDRAM controller for Xilinx Spartan-3E
122718: 07/08/04: <mvarman@gmail.com>: Xilinx XC4VLX40-10FFG1148C - Available New
122719: 07/08/04: N.V. Chandramouli: EDK =>"Virtex4_PPC_Example_9_1" on ubuntu, not able to change LEDs blinking through minicom hyperterminal
122720: 07/08/04: N.V. Chandramouli: EDK =>"Virtex4_PPC_Example_9_1" on ubuntu, not able to change LEDs blinking through minicom hyperterminal
122721: 07/08/04: N.V. Chandramouli: xps error never seen before: google reveals nothing; help!
    122752: 07/08/06: Torsten Landschoff: Re: xps error never seen before: google reveals nothing; help!
    122764: 07/08/06: Alan Nishioka: Re: xps error never seen before: google reveals nothing; help!
    122773: 07/08/06: N.V. Chandramouli: Re: xps error never seen before: google reveals nothing; help!
    122774: 07/08/06: N.V. Chandramouli: Re: xps error never seen before: google reveals nothing; help!
122722: 07/08/04: <manuel-lozano@mixmail.com>: mb-gdb: problem simulating memory mapped i/o devices
122723: 07/08/04: ZHI: Area report
    122728: 07/08/05: nezhate: Re: Area report
    122737: 07/08/05: John McCaskill: Re: Area report
    122900: 07/08/09: ZHI: Re: Area report
122725: 07/08/04: <bob.zigon@gmail.com>: Confused about my behavioral simulation under ISE 9.1
    122726: 07/08/05: Matthew Hicks: Re: Confused about my behavioral simulation under ISE 9.1
        122727: 07/08/05: John Retta: Re: Confused about my behavioral simulation under ISE 9.1
122730: 07/08/05: fpgauser: bare bone PCI cards with FPGAs
    122736: 07/08/05: Jeremy Harris: Re: bare bone PCI cards with FPGAs
122732: 07/08/05: <drop669@gmail.com>: OpenSPARC
    122734: 07/08/05: Antti: Re: OpenSPARC
    122735: 07/08/05: <drop669@gmail.com>: Re: OpenSPARC
        122739: 07/08/05: Matthew Hicks: Re: OpenSPARC
122733: 07/08/05: <drop669@gmail.com>: FPGA accelerator service
    122843: 07/08/08: davem: Re: FPGA accelerator service
122738: 07/08/05: Zorjak: bidirectional pin
    122740: 07/08/05: Matthew Hicks: Re: bidirectional pin
        122761: 07/08/06: Jeff Cunningham: Re: bidirectional pin
    122750: 07/08/06: Zorjak: Re: bidirectional pin
        122756: 07/08/06: Matthew Hicks: Re: bidirectional pin
    122770: 07/08/06: EEngineer: Re: bidirectional pin
    122783: 07/08/06: Eric Smith: Re: bidirectional pin
    122788: 07/08/07: Zorjak: Re: bidirectional pin
122741: 07/08/05: Eddie H: Single Ended signal in sync with V5 GTP
    122743: 07/08/06: Marc Randolph: Re: Single Ended signal in sync with V5 GTP
    122744: 07/08/05: Eddie H: Re: Single Ended signal in sync with V5 GTP
    122768: 07/08/06: Eddie H: Re: Single Ended signal in sync with V5 GTP
        122785: 07/08/07: Sylvain Munaut: Re: Single Ended signal in sync with V5 GTP
            122798: 07/08/07: Eddie H: Re: Single Ended signal in sync with V5 GTP
122745: 07/08/06: archana: how to test the FPGA on the board
    122746: 07/08/06: makhan: Re: how to test the FPGA on the board
122747: 07/08/05: sriman: DSP design into FPGA
122749: 07/08/06: jitendra: new to the group
    122751: 07/08/06: Antti: Re: new to the group
    122753: 07/08/06: nezhate: Re: new to the group
    122775: 07/08/06: John Adair: Re: new to the group
    122837: 07/08/08: svenand: Re: new to the group
122757: 07/08/06: cpope: xilinx plb_ddr to self refresh mode
    122839: 07/08/08: svenand: Re: xilinx plb_ddr to self refresh mode
    122842: 07/08/08: svenand: Re: xilinx plb_ddr to self refresh mode
122758: 07/08/06: IDDLife: Need suggestion for my project
    122762: 07/08/06: Antti: Re: Need suggestion for my project
    122763: 07/08/06: <randomdude@gmail.com>: Re: Need suggestion for my project
    122765: 07/08/06: austin: Re: Need suggestion for my project
        122767: 07/08/06: John_H: Re: Need suggestion for my project
    122782: 07/08/06: IDDLife: Re: Need suggestion for my project
    122787: 07/08/07: Antti: Re: Need suggestion for my project
    122789: 07/08/07: IDDLife: Re: Need suggestion for my project
122760: 07/08/06: X.Y.: Problem about clock switch in Quartus II 6.0
    122771: 07/08/06: Mike Treseler: Re: Problem about clock switch in Quartus II 6.0
    122781: 07/08/06: <dkarchmer@gmail.com>: Re: Problem about clock switch in Quartus II 6.0
    122805: 07/08/07: X.Y.: Re: Problem about clock switch in Quartus II 6.0
    122820: 07/08/07: <dkarchmer@gmail.com>: Re: Problem about clock switch in Quartus II 6.0
122772: 07/08/06: Matthew Hicks: AREA_GROUP Map Error
    122780: 07/08/06: Matthew Hicks: Re: AREA_GROUP Map Error
122777: 07/08/06: EEngineer: FPGA board connected to CMOS chip: ESD hazards?
    122778: 07/08/06: Andy Botterill: Re: FPGA board connected to CMOS chip: ESD hazards?
    122779: 07/08/06: austin: Re: FPGA board connected to CMOS chip: ESD hazards?
        122809: 07/08/07: Symon: Re: FPGA board connected to CMOS chip: ESD hazards?
        122810: 07/08/07: austin: Re: FPGA board connected to CMOS chip: ESD hazards?
    122803: 07/08/07: EEngineer: Re: FPGA board connected to CMOS chip: ESD hazards?
122784: 07/08/07: Andreas Gauckler: Digilent USB module linux
    122801: 07/08/07: Guenter Dannoritzer: Re: Digilent USB module linux
122793: 07/08/07: <ryufrank@hotmail.com>: TEMAC Performance Issues with Virtex 4FX
    122796: 07/08/07: PFC: Re: TEMAC Performance Issues with Virtex 4FX
        122807: 07/08/07: Sylvain Munaut: Re: TEMAC Performance Issues with Virtex 4FX
        122812: 07/08/07: PFC: Re: TEMAC Performance Issues with Virtex 4FX
        122815: 07/08/07: PFC: Re: TEMAC Performance Issues with Virtex 4FX
        122822: 07/08/08: John Williams: Re: TEMAC Performance Issues with Virtex 4FX
    122799: 07/08/07: <ryufrank@hotmail.com>: Re: TEMAC Performance Issues with Virtex 4FX
    122800: 07/08/07: <ryufrank@hotmail.com>: Re: TEMAC Performance Issues with Virtex 4FX
    122808: 07/08/07: morphiend: Re: TEMAC Performance Issues with Virtex 4FX
    122811: 07/08/07: <ryufrank@hotmail.com>: Re: TEMAC Performance Issues with Virtex 4FX
    122840: 07/08/08: Guru: Re: TEMAC Performance Issues with Virtex 4FX
    122954: 07/08/12: <ryufrank@hotmail.com>: Re: TEMAC Performance Issues with Virtex 4FX
    123016: 07/08/14: Torsten Landschoff: Re: TEMAC Performance Issues with Virtex 4FX
122816: 07/08/07: echo: EDK 8.1
    122817: 07/08/07: John_H: Re: EDK 8.1
        122823: 07/08/07: echo: Re: EDK 8.1
            122825: 07/08/07: Ed McGettigan: Re: EDK 8.1
                122853: 07/08/08: echo: Re: EDK 8.1
122818: 07/08/07: <markmcmahon@hotmail.com>: Microblaze GPIO interrupt
    122821: 07/08/08: John Williams: Re: Microblaze GPIO interrupt
122824: 07/08/08: Symon: New Xilinx forum.
    122826: 07/08/07: austin: Re: New Xilinx forum.
        122828: 07/08/07: DJ Delorie: Re: New Xilinx forum.
            122846: 07/08/08: austin: Re: New Xilinx forum.
                122858: 07/08/08: Sylvain Munaut: Re: New Xilinx forum.
        122831: 07/08/08: Jim Granville: Re: New Xilinx forum.
            122847: 07/08/08: austin: Re: New Xilinx forum.
        122863: 07/08/08: Nico Coesel: Re: New Xilinx forum.
    122827: 07/08/08: Tommy Thorn: Re: New Xilinx forum.
        122849: 07/08/08: austin: Re: New Xilinx forum.
    122829: 07/08/08: John_H: Re: New Xilinx forum.
    122830: 07/08/08: Jim Granville: Re: New Xilinx forum.
        122907: 07/08/10: Ken Ryan: Re: New Xilinx forum.
    122857: 07/08/08: <kempaj@yahoo.com>: Re: New Xilinx forum.
        122859: 07/08/08: Symon: Re: New Xilinx forum.
        122860: 07/08/08: Mike Treseler: Re: New Xilinx forum.
            122979: 07/08/13: David Binnie: Re: New Xilinx forum.
                122986: 07/08/13: austin: Re: New Xilinx forum.
        122879: 07/08/09: Colin Paul Gloster: Re: New Xilinx forum.
            122893: 07/08/09: Mike Treseler: Re: New Xilinx forum.
                122908: 07/08/10: Colin Paul Gloster: Re: New Xilinx forum.
    122862: 07/08/08: Peter Alfke: Re: New Xilinx forum.
    122892: 07/08/09: KJ: Re: New Xilinx forum.
        122897: 07/08/09: austin: Re: New Xilinx forum.
    122894: 07/08/09: Peter Alfke: Re: New Xilinx forum.
    122971: 07/08/13: Antti: Re: New Xilinx forum.
    122980: 07/08/13: Antti: Re: New Xilinx forum.
    122983: 07/08/13: Antti: Re: New Xilinx forum.
    122984: 07/08/13: Antti: Re: New Xilinx forum.
    123565: 07/08/30: Gabor: Re: New Xilinx forum.
122832: 07/08/08: Aida: Regional Clock Resources
122834: 07/08/08: comp.arch.fpga: Re: New Xilinx forum.
122836: 07/08/08: comp.arch.fpga: Re: New Xilinx forum.
    122848: 07/08/08: austin: Re: New Xilinx forum.
122841: 07/08/08: M Ihsan Baig: Ph.D in France
122844: 07/08/08: Richard Klingler: Mico32
122845: 07/08/08: IDDLife: Exception handling code in the OR1200
    122869: 07/08/08: IDDLife: Re: Exception handling code in the OR1200
122850: 07/08/08: Barry: Re: New Xilinx forum.
    122852: 07/08/08: austin: Re: New Xilinx forum.
122854: 07/08/08: ferorcue: Write of 64 from PowerPC to my IP conected to the PLB?
    122866: 07/08/08: Alan Nishioka: Re: Write of 64 from PowerPC to my IP conected to the PLB?
    122867: 07/08/08: Eric Smith: Re: Write of 64 from PowerPC to my IP conected to the PLB?
    122881: 07/08/09: Guru: Re: Write of 64 from PowerPC to my IP conected to the PLB?
    122884: 07/08/09: comp.arch.fpga: Re: Write of 64 from PowerPC to my IP conected to the PLB?
    122917: 07/08/10: ferorcue: Re: Write of 64 from PowerPC to my IP conected to the PLB?
    122925: 07/08/10: comp.arch.fpga: Re: Write of 64 from PowerPC to my IP conected to the PLB?
122855: 07/08/08: <moogyd@yahoo.co.uk>: Specifying LVDS I/O's in Xilinx FPGA's
    122856: 07/08/08: Symon: Re: Specifying LVDS I/O's in Xilinx FPGA's
    122861: 07/08/08: John_H: Re: Specifying LVDS I/O's in Xilinx FPGA's
    122868: 07/08/09: John Retta: Re: Specifying LVDS I/O's in Xilinx FPGA's
    122955: 07/08/12: <moogyd@yahoo.co.uk>: Re: Specifying LVDS I/O's in Xilinx FPGA's
122864: 07/08/08: Andreas Schwarz: Synthesizing fixed_pkg in ISE 9.2
    122896: 07/08/09: Mike Treseler: Re: Synthesizing fixed_pkg in ISE 9.2
        122999: 07/08/13: David Bishop: Re: Synthesizing fixed_pkg in ISE 9.2
            123193: 07/08/19: David Bishop: Re: Synthesizing fixed_pkg in ISE 9.2
            123222: 07/08/20: <steve.lass@xilinx.com>: Re: Synthesizing fixed_pkg in ISE 9.2
    123072: 07/08/15: Andreas Schwarz: Re: Synthesizing fixed_pkg in ISE 9.2
    123245: 07/08/21: Manny: Re: Synthesizing fixed_pkg in ISE 9.2
        123247: 07/08/21: Jonathan Bromley: Re: Synthesizing fixed_pkg in ISE 9.2
    123322: 07/08/23: <eli.billauer@gmail.com>: Re: Synthesizing fixed_pkg in ISE 9.2
    123374: 07/08/25: Andreas Schwarz: Re: Synthesizing fixed_pkg in ISE 9.2
    123452: 07/08/28: Andreas Schwarz: Re: Synthesizing fixed_pkg in ISE 9.2
122865: 07/08/08: Clement: High Speed ADC
    122876: 07/08/09: comp.arch.fpga: Re: High Speed ADC
    122889: 07/08/09: Joe: Re: High Speed ADC
    122898: 07/08/09: comp.arch.fpga: Re: High Speed ADC
122870: 07/08/09: neil3w@gmail.com: what the AC exactly short for here...
122871: 07/08/09: fpga_engineer: Xilinx Webpack 9.1: How do I export a netlist to another project?
    122878: 07/08/09: jacobusn@xilinx.com: Re: Xilinx Webpack 9.1: How do I export a netlist to another project?
        122882: 07/08/09: Brian Drummond: Re: Xilinx Webpack 9.1: How do I export a netlist to another project?
122872: 07/08/09: fpgabuilder: secure interfacing between an fpga and a connected device
    122877: 07/08/09: Colin Paul Gloster: Re: secure interfacing between an fpga and a connected device
        122902: 07/08/09: PFC: Re: secure interfacing between an fpga and a connected device
    122883: 07/08/09: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: secure interfacing between an fpga and a connected device
    122886: 07/08/09: fpgabuilder: Re: secure interfacing between an fpga and a connected device
    122899: 07/08/09: comp.arch.fpga: Re: secure interfacing between an fpga and a connected device
    122901: 07/08/09: Andreas Schwarz: Re: secure interfacing between an fpga and a connected device
122873: 07/08/09: Bart van Deenen: spartan3 picoblaze how to make .bmm file work
    122874: 07/08/09: Bart van Deenen: mem file
    122875: 07/08/09: svenand: Re: spartan3 picoblaze how to make .bmm file work
        122885: 07/08/09: Bart van Deenen: Re: spartan3 picoblaze how to make .bmm file work
    122887: 07/08/09: Bart van Deenen: got it!
    122939: 07/08/11: Walter Dvorak: Re: spartan3 picoblaze how to make .bmm file work
122888: 07/08/09: <danielgutierrezcastro@hotmail.com>: Reset and DCM
    122890: 07/08/09: austin: Re: Reset and DCM
    122891: 07/08/09: Barry: Re: Reset and DCM
122895: 07/08/09: Philip Potter: SystemACE, xilfatfs and feof()
122904: 07/08/10: Fred: EDK speed issue
    122905: 07/08/10: John Williams: Re: EDK speed issue
    122906: 07/08/09: Duane Clark: Re: EDK speed issue
        122930: 07/08/10: Fred: Re: EDK speed issue
    122910: 07/08/10: Göran Bilski: Re: EDK speed issue
        122928: 07/08/10: Fred: Re: EDK speed issue
            133804: 08/07/15: forrestoff: Re: EDK speed issue
    122931: 07/08/10: John McCaskill: Re: EDK speed issue
122909: 07/08/10: PretzelX: EDK (XPS) - Path problem causing "Generate Libraries and BSPs" to
122911: 07/08/10: Pinhas: I2C master connected and tested with LEON Processor
122912: 07/08/10: pgw: DDR/DDR2 controller - core
    122941: 07/08/11: dimtsios@ix.netcom.com: Re: DDR/DDR2 controller - core
        122943: 07/08/11: pgw: Re: DDR/DDR2 controller - core
    122952: 07/08/12: Nico Coesel: Re: DDR/DDR2 controller - core
        122953: 07/08/12: pgw: Re: DDR/DDR2 controller - core
            122960: 07/08/12: Nico Coesel: Re: DDR/DDR2 controller - core
    122988: 07/08/13: Andrew Burnside: Re: DDR/DDR2 controller - core
        122994: 07/08/13: pgw: Re: DDR/DDR2 controller - core
            123063: 07/08/15: RCIngham: Re: DDR/DDR2 controller - core
                123375: 07/08/25: Daniel S.: Re: DDR/DDR2 controller - core
    123054: 07/08/15: Andrew Burnside: Re: DDR/DDR2 controller - core
122913: 07/08/10: Pasacco: Amount of wire and logic
    122915: 07/08/10: Zara: Re: Amount of wire and logic
        122919: 07/08/10: John_H: Re: Amount of wire and logic
        122923: 07/08/10: Symon: Re: Amount of wire and logic
            122924: 07/08/10: Frank Buss: Re: Amount of wire and logic
                122927: 07/08/10: Frank Buss: Re: Amount of wire and logic
        123243: 07/08/21: Markus: Re: Amount of wire and logic
        123265: 07/08/22: Daniel S.: Re: Amount of wire and logic
    122916: 07/08/10: Pasacco: Re: Amount of wire and logic
    122920: 07/08/10: Peter Alfke: Re: Amount of wire and logic
    122921: 07/08/10: austin: Re: Amount of wire and logic
    122926: 07/08/10: Peter Alfke: Re: Amount of wire and logic
    122937: 07/08/11: Pasacco: Re: Amount of wire and logic
    122940: 07/08/11: Peter Alfke: Re: Amount of wire and logic
        122947: 07/08/12: Matthew Hicks: Re: Amount of wire and logic
            122961: 07/08/12: Eric Smith: Re: Amount of wire and logic
                122997: 07/08/13: Eric Smith: Re: Amount of wire and logic
        122948: 07/08/11: Peter Alfke: Re: Amount of wire and logic
        122964: 07/08/12: Peter Alfke: Re: Amount of wire and logic
    123017: 07/08/14: comp.arch.fpga: Re: Amount of wire and logic
    123069: 07/08/15: Pasacco: Re: Amount of wire and logic
    123071: 07/08/15: Peter Alfke: Re: Amount of wire and logic
    123099: 07/08/16: comp.arch.fpga: Re: Amount of wire and logic
    123105: 07/08/16: Pasacco: Re: Amount of wire and logic
    123237: 07/08/20: Pasacco: Re: Amount of wire and logic
    123239: 07/08/20: Pasacco: Re: Amount of wire and logic
    123241: 07/08/20: Peter Alfke: Re: Amount of wire and logic
122914: 07/08/10: <antoine.vernay@gmail.com>: Xilinx Xilfatfs SystemACE library and partition format
122918: 07/08/10: <ed.agunos@gmail.com>: embedded tips
    122922: 07/08/10: austin: Re: embedded tips
    122935: 07/08/10: IDDLife: Re: embedded tips
    122936: 07/08/11: svenand: Re: embedded tips
122929: 07/08/10: Albert Nguyen: How to locate the internal state machine in timing simulation
    122933: 07/08/10: John_H: Re: How to locate the internal state machine in timing simulation
    122942: 07/08/11: Albert Nguyen: Re: How to locate the internal state machine in timing
        122956: 07/08/12: John_H: Re: How to locate the internal state machine in timing simulation
            122958: 07/08/12: Albert Nguyen: Re: How to locate the internal state machine in timing
                122959: 07/08/12: John_H: Re: How to locate the internal state machine in timing simulation
    122944: 07/08/11: John Retta: Re: How to locate the internal state machine in timing simulation
        122945: 07/08/11: Albert Nguyen: Re: How to locate the internal state machine in timing
            122946: 07/08/11: John Retta: Re: How to locate the internal state machine in timing simulation
                122949: 07/08/11: Albert Nguyen: Re: How to locate the internal state machine in timing
    122957: 07/08/12: David Binnie: Re: How to locate the internal state machine in timing simulation
122932: 07/08/10: <ghelbig@lycos.com>: Re: Webpack 9.1 and Samba
    122934: 07/08/10: Peter Wallace: Re: Webpack 9.1 and Samba
122938: 07/08/11: u_stadler@yahoo.de: ucf editor edk
    122965: 07/08/13: Zara: Re: ucf editor edk
122951: 07/08/12: <eswar.saladi@gmail.com>: Used Stratix II FPGA's
122962: 07/08/12: <tlenomade@googlemail.com>: LUT distributed memory in FPGA devices
    122963: 07/08/12: Peter Alfke: Re: LUT distributed memory in FPGA devices
    122990: 07/08/13: austin: Re: LUT distributed memory in FPGA devices
    122996: 07/08/13: <tlenomade@googlemail.com>: Re: LUT distributed memory in FPGA devices
122966: 07/08/12: ekavirsrikanth@gmail.com: regarding the clock issues in the fpga...
    122981: 07/08/13: John_H: Re: regarding the clock issues in the fpga...
        123018: 07/08/14: John_H: Re: regarding the clock issues in the fpga...
    123001: 07/08/13: ekavirsrikanth@gmail.com: Re: regarding the clock issues in the fpga...
122967: 07/08/12: <kobelai15@gmail.com>: edk+uclinux ??? <about make dep>
    122972: 07/08/13: Gerhard Hoffmann: Re: edk+uclinux ??? <about make dep>
    122976: 07/08/13: <kobelai15@gmail.com>: Re: edk+uclinux ??? <about make dep>
    123006: 07/08/14: backhus: Re: edk+uclinux ??? <about make dep>
    123264: 07/08/21: RODWILL: Re: edk+uclinux ??? <about make dep>
122968: 07/08/13: Antti: Xilinx 13th August opportunity
    122973: 07/08/13: Jon Beniston: Re: Xilinx 13th August opportunity
    122974: 07/08/13: Jim Granville: Re: Xilinx 13th August opportunity
        122978: 07/08/13: KJ: Re: Xilinx 13th August opportunity
    122975: 07/08/13: Antti: Re: Xilinx 13th August opportunity
    122977: 07/08/13: jacobusn@xilinx.com: Re: Xilinx 13th August opportunity
    122985: 07/08/13: Peter Alfke: Re: Xilinx 13th August opportunity
    122987: 07/08/13: Antti: Re: Xilinx 13th August opportunity
122969: 07/08/13: Antti: Re: New Xilinx forum.
    122970: 07/08/13: mk: Re: New Xilinx forum.
    122982: 07/08/13: John_H: Re: New Xilinx forum.
122989: 07/08/13: Philip Potter: Problems using xilfatfs on XUP V2Pro board
    122991: 07/08/13: Siva Velusamy: Re: Problems using xilfatfs on XUP V2Pro board
        122992: 07/08/13: Philip Potter: Re: Problems using xilfatfs on XUP V2Pro board
122993: 07/08/13: MNiegl: Design Behavior affected by use of Chipscope
    123000: 07/08/14: John Retta: Re: Design Behavior affected by use of Chipscope
    123062: 07/08/15: MNiegl: Re: Design Behavior affected by use of Chipscope
122995: 07/08/13: <jeff.johnson.au@gmail.com>: Using Virtex-II Pro MGT with external CDR
122998: 07/08/13: bwilson79@gmail.com: Virtex-4 router failures when trying to mux multiple clocks (WARNING:Route:438)
    123019: 07/08/14: Gabor: Re: Virtex-4 router failures when trying to mux multiple clocks (WARNING:Route:438)
    123020: 07/08/14: bwilson79@gmail.com: Re: Virtex-4 router failures when trying to mux multiple clocks (WARNING:Route:438)
    123023: 07/08/14: Gabor: Re: Virtex-4 router failures when trying to mux multiple clocks (WARNING:Route:438)
123002: 07/08/14: Antti: new xilinx forums
123003: 07/08/13: u_stadler@yahoo.de: edk + spi
    123005: 07/08/14: Antti: Re: edk + spi
    123051: 07/08/15: u_stadler@yahoo.de: Re: edk + spi
123004: 07/08/14: <mkumarsampath@gmail.com>: SATA OOB using Rocket IO (Virtex 5)
123007: 07/08/14: Richard Klingler: mixed Verilog/VHDL in ispLever 7.0 broken
    123010: 07/08/14: Jon Beniston: Re: mixed Verilog/VHDL in ispLever 7.0 broken
        123011: 07/08/14: Richard Klingler: Re: mixed Verilog/VHDL in ispLever 7.0 broken
123008: 07/08/14: Matthias Alles: xst fails...
    123009: 07/08/14: Jon Beniston: Re: xst fails...
        123012: 07/08/14: Gerhard Hoffmann: Re: xst fails...
            123014: 07/08/14: Matthias Alles: Re: xst fails...
        123013: 07/08/14: Matthias Alles: Re: xst fails...
            123024: 07/08/14: Brian Drummond: Re: xst fails...
                123047: 07/08/15: Matthias Alles: Re: xst fails...
123015: 07/08/14: Torsten Landschoff: Virtex4+PPC+ext. RAM: Problems generating ACE files (solved!?)
123021: 07/08/14: <moogyd@yahoo.co.uk>: Xilinx Spartan FPGA : Strange Errors
    123025: 07/08/14: <ghelbig@lycos.com>: Re: Xilinx Spartan FPGA : Strange Errors
    123031: 07/08/14: Dave Pollum: Re: Xilinx Spartan FPGA : Strange Errors
    123033: 07/08/14: <moogyd@yahoo.co.uk>: Re: Xilinx Spartan FPGA : Strange Errors
123022: 07/08/14: <moogyd@yahoo.co.uk>: Xilinx Spartan FPGA : Strange Errors
    123026: 07/08/14: Symon: Re: Xilinx Spartan FPGA : Strange Errors
123027: 07/08/14: maxascent: SDRAM Controller
    123058: 07/08/15: Gabor: Re: SDRAM Controller
123028: 07/08/14: m: Delaying a pulse train
    123029: 07/08/14: Peter Alfke: Re: Delaying a pulse train
        123036: 07/08/14: John_H: Re: Delaying a pulse train
        123038: 07/08/15: Jim Granville: Re: Delaying a pulse train
            123045: 07/08/15: Jim Granville: Re: Delaying a pulse train
                123134: 07/08/17: Jim Granville: Re: Delaying a pulse train
            123067: 07/08/15: nospam: Re: Delaying a pulse train
                123074: 07/08/16: Jim Granville: Re: Delaying a pulse train
                    123080: 07/08/15: John_H: Re: Delaying a pulse train
                        123081: 07/08/16: Jim Granville: Re: Delaying a pulse train
        123039: 07/08/15: Jim Granville: Re: Delaying a pulse train
    123030: 07/08/14: m: Re: Delaying a pulse train
    123032: 07/08/14: John_H: Re: Delaying a pulse train
    123034: 07/08/14: Peter Alfke: Re: Delaying a pulse train
    123037: 07/08/14: m: Re: Delaying a pulse train
    123041: 07/08/14: Peter Alfke: Re: Delaying a pulse train
    123044: 07/08/15: m: Re: Delaying a pulse train
    123046: 07/08/14: Peter Alfke: Re: Delaying a pulse train
    123057: 07/08/15: <lb.edc@telenet.be>: Re: Delaying a pulse train
    123119: 07/08/16: m: Re: Delaying a pulse train
    123123: 07/08/16: Peter Alfke: Re: Delaying a pulse train
    123132: 07/08/16: m: Re: Delaying a pulse train
123035: 07/08/14: <bruce_hw_guy@hotmail.com>: Xilinx DDR2 SDRAM controller performance
    123053: 07/08/15: Andrew Burnside: Re: Xilinx DDR2 SDRAM controller performance
        123068: 07/08/15: Nico Coesel: Re: Xilinx DDR2 SDRAM controller performance
    123060: 07/08/15: <bruce_hw_guy@hotmail.com>: Re: Xilinx DDR2 SDRAM controller performance
123040: 07/08/14: Telenochek: How to save simulation results in Xilinx ISE ?
    123078: 07/08/15: Duth: Re: How to save simulation results in Xilinx ISE ?
123042: 07/08/15: Kunal: System ACE failure on ML405
    123048: 07/08/15: Torsten Landschoff: Re: System ACE failure on ML405
    123049: 07/08/15: comp.arch.fpga: Re: System ACE failure on ML405
    123082: 07/08/15: Kunal: Re: System ACE failure on ML405
123043: 07/08/14: Brad Smallridge: Xilinx PACKER warning bout carry
    123055: 07/08/15: Alan Nishioka: Re: Xilinx PACKER warning bout carry
        123121: 07/08/16: Brad Smallridge: Re: Xilinx PACKER warning bout carry
            123126: 07/08/16: Mike Treseler: Re: Xilinx PACKER warning bout carry
                123139: 07/08/16: Brad Smallridge: Re: Xilinx PACKER warning bout carry
                    123141: 07/08/16: Mike Treseler: Re: Xilinx PACKER warning bout carry
    123066: 07/08/15: Andy: Re: Xilinx PACKER warning bout carry
        123122: 07/08/16: Brad Smallridge: Re: Xilinx PACKER warning bout carry
    123073: 07/08/15: Mike Treseler: Re: Xilinx PACKER warning bout carry
        123124: 07/08/16: Brad Smallridge: Re: Xilinx PACKER warning bout carry
            123131: 07/08/16: Mike Treseler: Re: Xilinx PACKER warning bout carry
                123140: 07/08/16: Brad Smallridge: Re: Xilinx PACKER warning bout carry
123050: 07/08/15: mfgunes: Multiplication Problem on Microblaze Software
    123052: 07/08/15: Jon Beniston: Re: Multiplication Problem on Microblaze Software
        123056: 07/08/15: mfgunes: Re: Multiplication Problem on Microblaze Software
            123059: 07/08/15: Göran Bilski: Re: Multiplication Problem on Microblaze Software
            123061: 07/08/15: RCIngham: Re: Multiplication Problem on Microblaze Software
                123097: 07/08/16: Martin Thompson: Re: Multiplication Problem on Microblaze Software
            123094: 07/08/16: mfgunes: Re: Multiplication Problem on Microblaze Software
                123095: 07/08/16: Göran Bilski: Re: Multiplication Problem on Microblaze Software
                    123100: 07/08/16: mfgunes: Re: Multiplication Problem on Microblaze Software
                        123103: 07/08/16: Göran Bilski: Re: Multiplication Problem on Microblaze Software
                            123106: 07/08/16: mfgunes: Re: Multiplication Problem on Microblaze Software
                                123107: 07/08/16: Göran Bilski: Re: Multiplication Problem on Microblaze Software
                                    123204: 07/08/20: mfgunes: Re: Multiplication Problem on Microblaze Software
                                        123206: 07/08/20: Göran Bilski: Re: Multiplication Problem on Microblaze Software
                                            123207: 07/08/20: mfgunes: Re: Multiplication Problem on Microblaze Software
                                    123205: 07/08/20: mfgunes: Re: Multiplication Problem on Microblaze Software
123064: 07/08/15: ted: ChipHit: ASIC, FPGA, EDA Search Engine
    123065: 07/08/15: RCIngham: Re: ChipHit: ASIC, FPGA, EDA Search Engine
    123070: 07/08/15: yttrium: Re: ChipHit: ASIC, FPGA, EDA Search Engine
    123102: 07/08/16: Symon: Re: ChipHit: ASIC, FPGA, EDA Search Engine
    123158: 07/08/17: ted: Re: ChipHit: ASIC, FPGA, EDA Search Engine
123075: 07/08/15: MikeJ: Virtex 4 IBUFG to DCM routing question
    123076: 07/08/15: austin: Re: Virtex 4 IBUFG to DCM routing question
        123077: 07/08/15: austin: Re: Virtex 4 IBUFG to DCM routing question
        123093: 07/08/16: MikeJ: Re: Virtex 4 IBUFG to DCM routing question
            123104: 07/08/16: Symon: Re: Virtex 4 IBUFG to DCM routing question
                123117: 07/08/16: MikeJ: Re: Virtex 4 IBUFG to DCM routing question
                    123118: 07/08/16: MikeJ: Re: Virtex 4 IBUFG to DCM routing question
                    123130: 07/08/16: MikeJ: Re: Virtex 4 IBUFG to DCM routing question
123079: 07/08/15: Richard Klingler: Mico32 bootloader
123083: 07/08/15: Tommy Thorn: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits
    123084: 07/08/16: John_H: Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits
    123085: 07/08/15: Tommy Thorn: Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits
    123086: 07/08/15: Eric Crabill: Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits
        123087: 07/08/15: Eric Crabill: Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits
        123138: 07/08/16: Eric Smith: Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits
            123142: 07/08/16: Eric Crabill: Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits
    123089: 07/08/16: Antti: Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits
123088: 07/08/15: <kobelai15@gmail.com>: about mb-gcc error???
    123090: 07/08/16: backhus: Re: about mb-gcc error???
    123109: 07/08/16: beeraka@gmail.com: Re: about mb-gcc error???
    123136: 07/08/17: John Williams: Re: about mb-gcc error???
123091: 07/08/16: ankur: synthesis showing warning (replicated 1 time(s) to handle iob=true attribute.)
123092: 07/08/16: ankur: synthesis showing warning (replicated 1 time(s) to handle iob=true attribute.)
    123165: 07/08/17: Gabor: Re: synthesis showing warning (replicated 1 time(s) to handle iob=true attribute.)
123096: 07/08/16: kron: Fighting with Compact Flash
    123098: 07/08/16: Antti: Re: Fighting with Compact Flash
    123114: 07/08/16: Mike Treseler: Re: Fighting with Compact Flash
    124055: 07/09/11: kron: Re: Fighting with Compact Flash
123101: 07/08/16: Jim Wu: Re: Virtex 4 IBUFG to DCM routing question
123110: 07/08/16: maxascent: MGT Link
    123112: 07/08/16: comp.arch.fpga: Re: MGT Link
    123120: 07/08/16: MM: Re: MGT Link
        123146: 07/08/17: maxascent: Re: MGT Link
            123446: 07/08/28: Daniel S.: Re: MGT Link
123111: 07/08/16: bhb: Scilab / Matrix
    123113: 07/08/16: comp.arch.fpga: Re: Scilab / Matrix
123115: 07/08/16: bijoy: FPGA :'define not allowed in ISE ?
    123116: 07/08/16: Jon Beniston: Re: FPGA :'define not allowed in ISE ?
123125: 07/08/16: vu3rdd: Routing JTAG pins thru FPGA
    123133: 07/08/16: Andrew Holme: Re: Routing JTAG pins thru FPGA
    123145: 07/08/17: vu3rdd: Re: Routing JTAG pins thru FPGA
    123173: 07/08/18: JK: Re: Routing JTAG pins thru FPGA
123127: 07/08/16: Jim Wu: Re: Virtex 4 IBUFG to DCM routing question
123128: 07/08/16: Symon: Reconfiguring a Virtex4 DCM_ADV.
    123135: 07/08/16: davide: Re: Reconfiguring a Virtex4 DCM_ADV.
        123187: 07/08/19: Symon: Re: Reconfiguring a Virtex4 DCM_ADV.
123129: 07/08/16: Tommy Thorn: Re: New Xilinx forum.
123137: 07/08/16: Chao: FIFO16 on virtex4 error?
    123144: 07/08/17: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: FIFO16 on virtex4 error?
    123164: 07/08/17: <bruce_hw_guy@hotmail.com>: Re: FIFO16 on virtex4 error?
        123231: 07/08/20: Chao: Re: FIFO16 on virtex4 error?
    123166: 07/08/17: Peter Alfke: Re: FIFO16 on virtex4 error?
123143: 07/08/17: Marcel van de Burgwal: iMPACT command for selecting remote host running CableServer?
123147: 07/08/17: <lembke.stefan@googlemail.com>: Slice equation in bitstream
    123150: 07/08/17: Antti: Re: Slice equation in bitstream
        123155: 07/08/17: Symon: Re: Slice equation in bitstream
            123156: 07/08/17: Symon: Re: Slice equation in bitstream
                123161: 07/08/17: Symon: Re: Slice equation in bitstream
                    124312: 07/09/18: Symon: Re: Slice equation in bitstream
    123151: 07/08/17: <lembke.stefan@googlemail.com>: Re: Slice equation in bitstream
    123152: 07/08/17: Symon: Re: Slice equation in bitstream
    123153: 07/08/17: <lembke.stefan@googlemail.com>: Re: Slice equation in bitstream
    123154: 07/08/17: Antti: Re: Slice equation in bitstream
    123157: 07/08/17: <lembke.stefan@googlemail.com>: Re: Slice equation in bitstream
    123159: 07/08/17: <lembke.stefan@googlemail.com>: Re: Slice equation in bitstream
    123160: 07/08/17: Antti: Re: Slice equation in bitstream
    123162: 07/08/17: <lembke.stefan@googlemail.com>: Re: Slice equation in bitstream
    124302: 07/09/18: <lembke.stefan@googlemail.com>: Re: Slice equation in bitstream
123148: 07/08/17: Niv: Actel APA1000 and JTAG
    123149: 07/08/17: Antti: Re: Actel APA1000 and JTAG
    123163: 07/08/17: <SKatsyuba@gmail.com>: Re: Actel APA1000 and JTAG
123167: 07/08/17: amerdsp: Minimal power?
    123168: 07/08/17: Antti: Re: Minimal power?
        123170: 07/08/17: cpope: Re: Minimal power?
            123171: 07/08/17: John_H: Re: Minimal power?
    123169: 07/08/17: John_H: Re: Minimal power?
123172: 07/08/17: <moogyd@yahoo.co.uk>: Xilinx Constraints Question
    123174: 07/08/18: kenm: Re: Xilinx Constraints Question
    123175: 07/08/18: Symon: Re: Xilinx Constraints Question
        123208: 07/08/20: Symon: Re: Xilinx Constraints Question
    123203: 07/08/19: <moogyd@yahoo.co.uk>: Re: Xilinx Constraints Question
123176: 07/08/18: sriman: help on camera ports
    123177: 07/08/18: Donald: Re: help on camera ports
123179: 07/08/18: pgw: DDR controller - best device to perform
    123181: 07/08/18: Nico Coesel: Re: DDR controller - best device to perform
        123183: 07/08/19: pgw: Re: DDR controller - best device to perform
        123184: 07/08/19: Nico Coesel: Re: DDR controller - best device to perform
        123185: 07/08/19: pgw: Re: DDR controller - best device to perform
        123188: 07/08/19: PeteS: Re: DDR controller - best device to perform
            123196: 07/08/19: Nico Coesel: Re: DDR controller - best device to perform
                123200: 07/08/20: Tim (one of many): Re: DDR controller - best device to perform
            123201: 07/08/19: PeteS: Re: DDR controller - best device to perform
            123448: 07/08/28: Daniel S.: Re: DDR controller - best device to perform
        123189: 07/08/19: PeteS: Re: DDR controller - best device to perform
    123182: 07/08/18: Peter Alfke: Re: DDR controller - best device to perform
    123192: 07/08/19: fpgabuilder: Re: DDR controller - best device to perform
    123225: 07/08/20: pgw: Re: DDR controller - best device to perform
        123809: 07/09/05: pgw: Re: DDR controller - best device to perform
    123403: 07/08/27: <rkruger@altera.com>: Re: DDR controller - best device to perform
    123404: 07/08/27: <rkruger@altera.com>: Re: DDR controller - best device to perform
123186: 07/08/19: <eli.billauer@gmail.com>: Xilinx / ISE multi-cycle path constraint pitfall
    123190: 07/08/19: Mike Treseler: Re: Xilinx / ISE multi-cycle path constraint pitfall
    123191: 07/08/19: John Retta: Re: Xilinx / ISE multi-cycle path constraint pitfall
        123197: 07/08/19: John Retta: Re: Xilinx / ISE multi-cycle path constraint pitfall
            123202: 07/08/19: Mike Treseler: Re: Xilinx / ISE multi-cycle path constraint pitfall
                123256: 07/08/21: Ray Andraka: Re: Xilinx / ISE multi-cycle path constraint pitfall
                    123371: 07/08/25: John Retta: Re: Xilinx / ISE multi-cycle path constraint pitfall
                        123372: 07/08/25: Mike Treseler: Re: Xilinx / ISE multi-cycle path constraint pitfall
                    123454: 07/08/28: Mike Treseler: Re: Xilinx / ISE multi-cycle path constraint pitfall
                        123466: 07/08/28: Symon: Re: Xilinx / ISE multi-cycle path constraint pitfall
                            123506: 07/08/29: Symon: Re: Xilinx / ISE multi-cycle path constraint pitfall
                                123560: 07/08/30: Symon: Re: Xilinx / ISE multi-cycle path constraint pitfall
                                    123588: 07/08/30: Symon: Re: Xilinx / ISE multi-cycle path constraint pitfall
                                        123589: 07/08/30: Symon: Re: Xilinx / ISE multi-cycle path constraint pitfall
                                123605: 07/08/30: Mike Treseler: Re: Xilinx / ISE multi-cycle path constraint pitfall
    123194: 07/08/19: mk: Re: Xilinx / ISE multi-cycle path constraint pitfall
    123195: 07/08/19: <eli.billauer@gmail.com>: Re: Xilinx / ISE multi-cycle path constraint pitfall
    123214: 07/08/20: Symon: Re: Xilinx / ISE multi-cycle path constraint pitfall
    123319: 07/08/23: Andy: Re: Xilinx / ISE multi-cycle path constraint pitfall
        123323: 07/08/23: Matthew Hicks: Re: Xilinx / ISE multi-cycle path constraint pitfall
            123324: 07/08/23: Jonathan Bromley: Re: Xilinx / ISE multi-cycle path constraint pitfall
                123325: 07/08/23: Mike Treseler: Re: Xilinx / ISE multi-cycle path constraint pitfall
    123435: 07/08/28: <eli.billauer@gmail.com>: Re: Xilinx / ISE multi-cycle path constraint pitfall
    123505: 07/08/29: <eli.billauer@gmail.com>: Re: Xilinx / ISE multi-cycle path constraint pitfall
    123554: 07/08/30: <eli.billauer@gmail.com>: Re: Xilinx / ISE multi-cycle path constraint pitfall
    123584: 07/08/30: <eli.billauer@gmail.com>: Re: Xilinx / ISE multi-cycle path constraint pitfall
    123657: 07/08/31: <eli.billauer@gmail.com>: Re: Xilinx / ISE multi-cycle path constraint pitfall
123198: 07/08/19: Pasacco: Globally Asynchronous in FPGA
    123199: 07/08/20: Symon: Re: Globally Asynchronous in FPGA
        123254: 07/08/21: Mike Treseler: Re: Globally Asynchronous in FPGA
        123266: 07/08/22: RCIngham: Re: Globally Asynchronous in FPGA
            123279: 07/08/23: David R Brooks: Re: Globally Asynchronous in FPGA
    123234: 07/08/20: Pasacco: Re: Globally Asynchronous in FPGA
    123242: 07/08/20: Thomas Stanka: Re: Globally Asynchronous in FPGA
123209: 07/08/20: LilacSkin: MCS -> BIT
    123210: 07/08/20: Antti: Re: MCS -> BIT
        123223: 07/08/20: davide: Re: MCS -> BIT
    123211: 07/08/20: LilacSkin: Re: MCS -> BIT
    123212: 07/08/20: LilacSkin: Re: MCS -> BIT
    123280: 07/08/22: Jon Elson: Re: MCS -> BIT
        143401: 09/10/09: gkonstan: Re: MCS -> BIT
            143413: 09/10/10: Uwe Bonnes: Re: MCS -> BIT
123213: 07/08/20: Vangelis: GPIO_performance
    123220: 07/08/20: Antti: Re: GPIO_performance
        123221: 07/08/20: Vangelis: Re: GPIO_performance
123215: 07/08/20: Eddie H: Voltage translation question
    123217: 07/08/20: Gabor: Re: Voltage translation question
        123219: 07/08/20: Eddie H: Re: Voltage translation question
    123235: 07/08/20: John Larkin: Re: Voltage translation question
        123236: 07/08/20: Eddie H: Re: Voltage translation question
            123296: 07/08/22: John Larkin: Re: Voltage translation question
                123316: 07/08/23: Eddie H: Re: Voltage translation question
                    123320: 07/08/23: John Larkin: Re: Voltage translation question
                        123327: 07/08/24: Jim Granville: Re: Voltage translation question
                            123328: 07/08/23: John Larkin: Re: Voltage translation question
    123248: 07/08/21: Brian Drummond: Re: Voltage translation question
        123249: 07/08/21: Eddie H: Re: Voltage translation question
            123261: 07/08/21: Symon: Re: Voltage translation question
    123258: 07/08/22: Jim Granville: Re: Voltage translation question
    123263: 07/08/21: Peter Alfke: Re: Voltage translation question
123216: 07/08/20: young: Re: Reconfiguring a Virtex4 DCM_ADV.
123218: 07/08/20: young: Multiple MicroBlazes error
    123244: 07/08/21: Göran Bilski: Re: Multiple MicroBlazes error
123224: 07/08/20: fazulu deen: exe file in modelsim
    123226: 07/08/20: HT-Lab: Re: exe file in modelsim
123227: 07/08/20: bwilson79@gmail.com: At what frequencies is it acceptable to generate a clock from a register?
    123228: 07/08/20: Duane Clark: Re: At what frequencies is it acceptable to generate a clock from
    123229: 07/08/20: KJ: Re: At what frequencies is it acceptable to generate a clock from a register?
    123232: 07/08/20: Gabor: Re: At what frequencies is it acceptable to generate a clock from a register?
    123233: 07/08/20: Peter Alfke: Re: At what frequencies is it acceptable to generate a clock from a register?
    123301: 07/08/23: bwilson79@gmail.com: Re: At what frequencies is it acceptable to generate a clock from a register?
    123303: 07/08/22: Peter Alfke: Re: At what frequencies is it acceptable to generate a clock from a register?
    123334: 07/08/24: bwilson79@gmail.com: Re: At what frequencies is it acceptable to generate a clock from a register?
    123335: 07/08/23: Peter Alfke: Re: At what frequencies is it acceptable to generate a clock from a register?
    123366: 07/08/24: bwilson79@gmail.com: Re: At what frequencies is it acceptable to generate a clock from a register?
123230: 07/08/20: Peter Alfke: Old issues of XCell magazine
    123282: 07/08/22: Weng Tianxiang: Re: Old issues of XCell magazine
    123286: 07/08/22: svenand: Re: Old issues of XCell magazine
123238: 07/08/20: David Thomas: FPL 2007 : Final call for participation
123240: 07/08/21: sriman: help on how to assign data to the function of nios program
123246: 07/08/21: Manny: Spartan-3A DSP vs. Cyclone III Power-wise
    123250: 07/08/21: Fredrik: Re: Spartan-3A DSP vs. Cyclone III Power-wise
    123252: 07/08/21: austin: Re: Spartan-3A DSP vs. Cyclone III Power-wise
    123260: 07/08/21: <rkruger@altera.com>: Re: Spartan-3A DSP vs. Cyclone III Power-wise
    123285: 07/08/22: Manny: Re: Spartan-3A DSP vs. Cyclone III Power-wise
        123317: 07/08/23: austin: Re: Spartan-3A DSP vs. Cyclone III Power-wise
    123297: 07/08/23: Paul Leventis: Re: Spartan-3A DSP vs. Cyclone III Power-wise
    123306: 07/08/22: <xeinth@hotmail.com>: Re: Spartan-3A DSP vs. Cyclone III Power-wise
123251: 07/08/21: Phil: System Generator Question: Flopping the inputs and outputs
    123255: 07/08/21: Phil: Re: System Generator Question: Flopping the inputs and outputs
123253: 07/08/21: icegray: MicroBlaze and ChipScope
    123262: 07/08/21: motty: Re: MicroBlaze and ChipScope
123257: 07/08/21: sriman: help to sort out the errors
    123259: 07/08/21: <ghelbig@lycos.com>: Re: help to sort out the errors
    123338: 07/08/24: sriman: Re: help to sort out the errors
123267: 07/08/22: <alleynb@gmail.com>: ML401 (Virtex 4 development board) as a USB peripheral
    123273: 07/08/22: John McGrath: Re: ML401 (Virtex 4 development board) as a USB peripheral
        123278: 07/08/22: Hal Murray: Re: ML401 (Virtex 4 development board) as a USB peripheral
            123284: 07/08/22: Hal Murray: Re: ML401 (Virtex 4 development board) as a USB peripheral
    123281: 07/08/22: John McGrath: Re: ML401 (Virtex 4 development board) as a USB peripheral
    123290: 07/08/22: John McGrath: Re: ML401 (Virtex 4 development board) as a USB peripheral
    123291: 07/08/22: <alleynb@gmail.com>: Re: ML401 (Virtex 4 development board) as a USB peripheral
    123292: 07/08/22: John McGrath: Re: ML401 (Virtex 4 development board) as a USB peripheral
123268: 07/08/22: <wittenjon@googlemail.com>: Need to force all signals in a design to a known value at start of simulation
    123271: 07/08/22: Andy: Re: Need to force all signals in a design to a known value at start of simulation
        123275: 07/08/22: Jonathan Bromley: Re: Need to force all signals in a design to a known value at start of simulation
            123314: 07/08/23: Jonathan Bromley: Re: Need to force all signals in a design to a known value at start of simulation
    123274: 07/08/22: Mike Treseler: Re: Need to force all signals in a design to a known value at start
    123276: 07/08/22: Jonathan Bromley: Re: Need to force all signals in a design to a known value at start of simulation
    123295: 07/08/22: Andy: Re: Need to force all signals in a design to a known value at start of simulation
    123307: 07/08/23: fpgabuilder: Re: Need to force all signals in a design to a known value at start of simulation
    123313: 07/08/23: diogratia: Re: Need to force all signals in a design to a known value at start of simulation
    123315: 07/08/23: Andy: Re: Need to force all signals in a design to a known value at start of simulation
123269: 07/08/22: <tgschwind@tiscalinet.ch>: Power Reduction Strategy
    123270: 07/08/22: Andy: Re: Power Reduction Strategy
        123283: 07/08/22: Hal Murray: Re: Power Reduction Strategy
    123272: 07/08/22: Andreas Ehliar: Re: Power Reduction Strategy
        123289: 07/08/22: Ray Andraka: Re: Power Reduction Strategy
        123294: 07/08/23: Jim Granville: Re: Power Reduction Strategy
    123277: 07/08/22: Ray Andraka: Re: Power Reduction Strategy
    123287: 07/08/22: Peter Alfke: Re: Power Reduction Strategy
    123288: 07/08/22: Nico Coesel: Re: Power Reduction Strategy
    123293: 07/08/22: Andy: Re: Power Reduction Strategy
    123298: 07/08/23: Paul Leventis: Re: Power Reduction Strategy
    123299: 07/08/22: John Larkin: Re: Power Reduction Strategy
    123300: 07/08/23: Jim Granville: Re: Power Reduction Strategy
123302: 07/08/22: lordwolf: Burst Memory Transfer Request from PPC
    123304: 07/08/22: Peter Ryser: Re: Burst Memory Transfer Request from PPC
123305: 07/08/23: <kmk1978@gmail.com>: how to bidirectional signal in xilinx EDK tool ?
    123310: 07/08/23: Guru: Re: how to bidirectional signal in xilinx EDK tool ?
        124345: 07/09/18: lionheart70: Re: how to bidirectional signal in xilinx EDK tool ?
123308: 07/08/23: bhb: comparison with embedded processor
    123311: 07/08/23: Jon Beniston: Re: comparison with embedded processor
    123312: 07/08/23: Frank Buss: Re: comparison with embedded processor
        123684: 07/09/01: Daniel S.: Re: comparison with embedded processor
    123321: 07/08/23: mmihai: Re: comparison with embedded processor
    123333: 07/08/23: mmihai: Re: comparison with embedded processor
123309: 07/08/23: bert: xilinx usb cable question
    123337: 07/08/23: svenand: Re: xilinx usb cable question
        123346: 07/08/24: Bert: Re: xilinx usb cable question
            123392: 07/08/27: taco: Re: xilinx usb cable question
    123347: 07/08/24: morphiend: Re: xilinx usb cable question
123318: 07/08/23: maxascent: ML365
123326: 07/08/23: fpgabuilder: Altera DDR Controller, Modelsim and Verilog
123329: 07/08/23: <jasuris@gmail.com>: ROUTING=CLOSED in Xilinx 9.1 PR tools
    123330: 07/08/23: Matthew Hicks: Re: ROUTING=CLOSED in Xilinx 9.1 PR tools
    123356: 07/08/24: <jasuris@gmail.com>: Re: ROUTING=CLOSED in Xilinx 9.1 PR tools
123331: 07/08/24: Christian Obel: Annoying
123332: 07/08/23: John_H: Re: Annoying
    123340: 07/08/24: Uwe Bonnes: Re: Annoying
        123344: 07/08/24: RCIngham: Re: Annoying
            123383: 07/08/27: Mark McDougall: Re: Annoying
123336: 07/08/23: Koustav: Inout ports in EDK
123339: 07/08/23: Pablo: Speed test between FPGA and DSP or PC.
    123345: 07/08/24: RCIngham: Re: Speed test between FPGA and DSP or PC.
        123365: 07/08/24: Hal Murray: Re: Speed test between FPGA and DSP or PC.
    123348: 07/08/24: comp.arch.fpga: Re: Speed test between FPGA and DSP or PC.
123341: 07/08/24: Sylvain Munaut <SomeOne@SomeDomain.com>: DDR2 controller V4 vs V5 differences ?
    123370: 07/08/25: Sean Durkin: Re: DDR2 controller V4 vs V5 differences ?
        123386: 07/08/27: John Schmitz: Re: DDR2 controller V4 vs V5 differences ?
            123475: 07/08/28: John Schmitz: Re: DDR2 controller V4 vs V5 differences ?
    123385: 07/08/27: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: DDR2 controller V4 vs V5 differences ?
    123388: 07/08/27: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: DDR2 controller V4 vs V5 differences ?
    123496: 07/08/29: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: DDR2 controller V4 vs V5 differences ?
123342: 07/08/24: xenix: OCM BRAM and PCC issues...
123343: 07/08/24: Rutger Stoots: xilinx impact 9.2 problem
    123352: 07/08/24: Gabor: Re: xilinx impact 9.2 problem
        123353: 07/08/24: Rutger Stoots: Re: xilinx impact 9.2 problem
            123363: 07/08/24: Jon Elson: Re: xilinx impact 9.2 problem
                123369: 07/08/25: Rutger Stoots: Re: xilinx impact 9.2 problem
                123384: 07/08/26: Nitro: Re: xilinx impact 9.2 problem
                123391: 07/08/27: Rutger Stoots: Re: xilinx impact 9.2 problem
123349: 07/08/24: Symon: Samtec PowerPoser power filtering solution.
    123350: 07/08/24: Gabor: Re: Samtec PowerPoser power filtering solution.
        123360: 07/08/24: Symon: Re: Samtec PowerPoser power filtering solution.
            123362: 07/08/24: Symon: Re: Samtec PowerPoser power filtering solution.
            123367: 07/08/24: PeteS: Re: Samtec PowerPoser power filtering solution.
123351: 07/08/24: Gabor: Re: Annoying
123354: 07/08/24: mahshid: Dynamic power estimation using Xpower
    123361: 07/08/24: Symon: Re: Dynamic power estimation using Xpower
    123368: 07/08/25: mahshid: Re: Dynamic power estimation using Xpower
123355: 07/08/24: Kevin: hwicap for EDK 9.1
123357: 07/08/24: Roman Zeilinger: Implementing MIPS Memory Hiarchy
    123358: 07/08/24: Jon Beniston: Re: Implementing MIPS Memory Hiarchy
        123359: 07/08/24: Roman Zeilinger: Re: Implementing MIPS Memory Hiarchy
    123364: 07/08/24: Jon Beniston: Re: Implementing MIPS Memory Hiarchy
123373: 07/08/25: tersono: A beginner asks questions about synthesis under Xilinx XST
    123376: 07/08/25: svenand: Re: A beginner asks questions about synthesis under Xilinx XST
        123379: 07/08/26: tersono: Re: A beginner asks questions about synthesis under Xilinx XST
123377: 07/08/25: Uncle Noah: Overriding a VHDL generic for command-line driven synthesis with ISE
123378: 07/08/26: Bart van Deenen: [xilinx ise simulation] how to keep all settings between runs
    123380: 07/08/26: Duth: Re: how to keep all settings between runs
        123387: 07/08/27: Bart van Deenen: Re: how to keep all settings between runs
    123541: 07/08/29: Duth: Re: how to keep all settings between runs
123381: 07/08/26: Bob Smith: Newbie with ISE 9_2_02i_lin gets error : Process "Translate" failed
    123393: 07/08/27: <manolete@discontrol.net>: Re: Newbie with ISE 9_2_02i_lin gets error : Process "Translate" failed
        123408: 07/08/27: Joseph Samson: Re: Newbie with ISE 9_2_02i_lin gets error : Process "Translate"
        123422: 07/08/28: Bob Smith: Re: Newbie with ISE 9_2_02i_lin gets error : Process "Translate"
    123677: 07/09/01: Bob Smith: Re: Newbie with ISE 9_2_02i_lin gets error : Process "Translate"
123382: 07/08/26: ajith.thamara@gmail.com: Partial reconfiguration using ICAP
    123458: 07/08/28: Sean Durkin: Re: Partial reconfiguration using ICAP
        123685: 07/09/01: Sean Durkin: Re: Partial reconfiguration using ICAP
    123566: 07/08/30: Neil Steiner: Re: Partial reconfiguration using ICAP
    123602: 07/08/30: ajith.thamara@gmail.com: Re: Partial reconfiguration using ICAP
123389: 07/08/27: Christian Kirschenlohr: Looking for VME-Bus Core
123390: 07/08/27: onenanometer@gmail.com: Interview Questions
    123508: 07/08/29: Nir Dahan: Re: Interview Questions
123394: 07/08/27: Zorjak: bidirectional pin help
    123396: 07/08/27: MM: Re: bidirectional pin help
        123418: 07/08/27: Jeff Cunningham: Re: bidirectional pin help
            123462: 07/08/28: Mike Treseler: Re: bidirectional pin help
            123520: 07/08/29: MM: Re: bidirectional pin help
                123532: 07/08/29: MM: Re: bidirectional pin help
                    123537: 07/08/29: MM: Re: bidirectional pin help
                        123550: 07/08/29: MM: Re: bidirectional pin help
                            123551: 07/08/29: MM: Re: bidirectional pin help
    123407: 07/08/27: Zorjak: Re: bidirectional pin help
    123423: 07/08/28: Zorjak: Re: bidirectional pin help
    123497: 07/08/29: Zorjak: Re: bidirectional pin help
    123528: 07/08/29: Zorjak: Re: bidirectional pin help
    123534: 07/08/29: Zorjak: Re: bidirectional pin help
    123542: 07/08/29: Zorjak: Re: bidirectional pin help
    123555: 07/08/30: Zorjak: Re: bidirectional pin help
123395: 07/08/27: Weng Tianxiang: Null statement in VHDL
    123397: 07/08/27: Mike Treseler: Re: Null statement in VHDL
        123400: 07/08/27: Mike Treseler: Re: Null statement in VHDL
        123409: 07/08/27: Alex Colvin: Re: Null statement in VHDL
        123425: 07/08/28: HT-Lab: Re: Null statement in VHDL
        123430: 07/08/28: Colin Paul Gloster: Re: Null statement in VHDL
        123449: 07/08/28: Colin Paul Gloster: Re: Null statement in VHDL
            123708: 07/09/02: Jonathan Bromley: Re: Null statement in VHDL
                123710: 07/09/02: KJ: Re: Null statement in VHDL
                    123729: 07/09/03: Jonathan Bromley: Re: Null statement in VHDL
                        123742: 07/09/03: KJ: Re: Null statement in VHDL
                        123756: 07/09/04: Jonathan Bromley: Re: Null statement in VHDL
        123463: 07/08/28: Jim Lewis: Re: Null statement in VHDL
        123754: 07/09/04: comp.arch.fpga: Re: Null statement in VHDL
        123816: 07/09/05: Andy: Re: Null statement in VHDL
    123399: 07/08/27: Weng Tianxiang: Re: Null statement in VHDL
    123402: 07/08/27: Mike Lundy: Re: Null statement in VHDL
        123820: 07/09/05: Andy: Re: Null statement in VHDL
    123406: 07/08/27: Weng Tianxiang: Re: Null statement in VHDL
    123411: 07/08/27: Andy: Re: Null statement in VHDL
    123413: 07/08/27: Andy: Re: Null statement in VHDL
    123415: 07/08/27: Mike Lundy: Re: Null statement in VHDL
    123424: 07/08/28: comp.arch.fpga: Re: Null statement in VHDL
    123429: 07/08/28: comp.arch.fpga: Re: Null statement in VHDL
    123450: 07/08/28: Tricky: Re: Null statement in VHDL
    123453: 07/08/28: comp.arch.fpga: Re: Null statement in VHDL
    123481: 07/08/28: Andy: Re: Null statement in VHDL
123398: 07/08/27: bart: ANNC: FPGA Noise Fundamentals Webcast
    123412: 07/08/27: <MikeShepherd564@btinternet.com>: Re: ANNC: FPGA Noise Fundamentals Webcast
    123436: 07/08/28: Gabor: Re: ANNC: FPGA Noise Fundamentals Webcast
123401: 07/08/27: Gavin Scott: Re: Annoying
123405: 07/08/27: <mittra@gmail.com>: tricking bitgen into creating rom-like behavior
    123410: 07/08/27: glen herrmannsfeldt: Re: tricking bitgen into creating rom-like behavior
        123421: 07/08/28: Sean Durkin: Re: tricking bitgen into creating rom-like behavior
    123414: 07/08/27: Andy: Re: tricking bitgen into creating rom-like behavior
    123438: 07/08/28: PFC: Re: tricking bitgen into creating rom-like behavior
123416: 07/08/27: fpgabuilder: PLL Power and m/n ratio
    123417: 07/08/27: austin: Re: PLL Power and m/n ratio
    123437: 07/08/28: Gabor: Re: PLL Power and m/n ratio
    123444: 07/08/28: Paul Leventis: Re: PLL Power and m/n ratio
    123521: 07/08/29: fpgabuilder: Re: PLL Power and m/n ratio
    123530: 07/08/29: Gabor: Re: PLL Power and m/n ratio
    123670: 07/09/01: fpgabuilder: Re: PLL Power and m/n ratio
123419: 07/08/28: Weng Tianxiang: New keyword 'orif' and its implications
    123431: 07/08/28: Symon: Re: New keyword 'orif' and its implications
        123464: 07/08/28: Symon: Re: New keyword 'orif' and its implications
            123471: 07/08/28: Jonathan Bromley: Re: New keyword 'orif' and its implications
    123433: 07/08/28: Jonathan Bromley: Re: New keyword 'orif' and its implications
    123434: 07/08/28: Marcus Harnisch: Re: New keyword 'orif' and its implications
        123596: 07/08/30: Mike Treseler: Re: New keyword 'orif' and its implications
        123601: 07/08/30: Jim Lewis: Re: New keyword 'orif' and its implications
        123672: 07/08/31: Jim Lewis: Re: New keyword 'orif' and its implications
            123850: 07/09/05: Jim Lewis: Re: New keyword 'orif' and its implications
            123851: 07/09/05: Jim Lewis: Re: New keyword 'orif' and its implications
            123871: 07/09/06: Brian Drummond: Re: New keyword 'orif' and its implications
                123941: 07/09/07: Brian Drummond: Re: New keyword 'orif' and its implications
    123455: 07/08/28: Mike Treseler: Re: New keyword 'orif' and its implications
    123460: 07/08/28: KJ: Re: New keyword 'orif' and its implications
        123525: 07/08/29: Mike Treseler: Re: New keyword 'orif' and its implications
    123461: 07/08/28: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123465: 07/08/28: Jim Lewis: Re: New keyword 'orif' and its implications
        123478: 07/08/28: Jim Lewis: Re: New keyword 'orif' and its implications
        123482: 07/08/28: Mike Treseler: Re: New keyword 'orif' and its implications
        123501: 07/08/29: Colin Paul Gloster: Re: New keyword 'orif' and its implications
            123561: 07/08/30: Colin Paul Gloster: Re: New keyword 'orif' and its implications
                123577: 07/08/30: Jim Lewis: Re: New keyword 'orif' and its implications
                    123622: 07/08/31: Colin Paul Gloster: Re: New keyword 'orif' and its implications
            123576: 07/08/30: Jim Lewis: Re: New keyword 'orif' and its implications
                123594: 07/08/30: Jim Lewis: Re: New keyword 'orif' and its implications
                123600: 07/08/30: Jim Lewis: Re: New keyword 'orif' and its implications
                123639: 07/08/31: Jim Lewis: Re: New keyword 'orif' and its implications
            123733: 07/09/03: Colin Paul Gloster: Re: New keyword 'orif' and its implications
                123750: 07/09/03: KJ: Re: New keyword 'orif' and its implications
    123468: 07/08/28: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123472: 07/08/28: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123476: 07/08/28: Andy: Re: New keyword 'orif' and its implications
    123477: 07/08/28: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123479: 07/08/28: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123484: 07/08/28: Andy: Re: New keyword 'orif' and its implications
    123503: 07/08/29: comp.arch.fpga: Re: New keyword 'orif' and its implications
    123523: 07/08/29: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123539: 07/08/29: Andy: Re: New keyword 'orif' and its implications
    123547: 07/08/29: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123574: 07/08/30: comp.arch.fpga: Re: New keyword 'orif' and its implications
    123590: 07/08/30: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123593: 07/08/30: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123597: 07/08/30: Andy: Re: New keyword 'orif' and its implications
    123606: 07/08/30: Andy: Re: New keyword 'orif' and its implications
    123609: 07/08/30: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123612: 07/08/30: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123630: 07/08/31: Andy: Re: New keyword 'orif' and its implications
    123634: 07/08/31: Andy: Re: New keyword 'orif' and its implications
    123641: 07/08/31: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123656: 07/08/31: Andy: Re: New keyword 'orif' and its implications
    123664: 07/08/31: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123666: 07/08/31: Weng Tianxiang: Re: New keyword 'orif' and its implications
        123880: 07/09/06: Weng Tianxiang: Re: New keyword 'orif' and its implications
        123884: 07/09/06: Weng Tianxiang: Re: New keyword 'orif' and its implications
        123886: 07/09/06: Weng Tianxiang: Re: New keyword 'orif' and its implications
        123891: 07/09/06: Andy: Re: New keyword 'orif' and its implications
    123674: 07/08/31: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123683: 07/09/01: comp.arch.fpga: Re: New keyword 'orif' and its implications
    123689: 07/09/01: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123694: 07/09/02: comp.arch.fpga: Re: New keyword 'orif' and its implications
    123695: 07/09/02: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123721: 07/09/02: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123723: 07/09/02: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123738: 07/09/03: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123739: 07/09/03: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123748: 07/09/03: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123762: 07/09/04: Andy: Re: New keyword 'orif' and its implications
    123763: 07/09/04: Andy: Re: New keyword 'orif' and its implications
    123764: 07/09/04: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123767: 07/09/04: Andy: Re: New keyword 'orif' and its implications
    123772: 07/09/04: Andy: Re: New keyword 'orif' and its implications
    123824: 07/09/05: Andy: Re: New keyword 'orif' and its implications
    123827: 07/09/05: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123828: 07/09/05: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123830: 07/09/05: Andy: Re: New keyword 'orif' and its implications
    123831: 07/09/05: Andy: Re: New keyword 'orif' and its implications
    123846: 07/09/05: Weng Tianxiang: Re: New keyword 'orif' and its implications
    123878: 07/09/06: Andy: Re: New keyword 'orif' and its implications
123420: 07/08/28: vasile: weird issue on Xilinx ML501/ML505 evkit designs
123426: 07/08/28: shadabambat1@gmail.com: XHWIF interface for Virtex II devices
123427: 07/08/28: <anilcelebi@gmail.com>: VHDL clocking scheme VS Verilog clocking scheme
    123428: 07/08/28: Jonathan Bromley: Re: VHDL clocking scheme VS Verilog clocking scheme
        123442: 07/08/28: Jonathan Bromley: Re: VHDL clocking scheme VS Verilog clocking scheme
    123439: 07/08/28: Gabor: Re: VHDL clocking scheme VS Verilog clocking scheme
123432: 07/08/28: Analog_Guy: Xilinx Virtex IOB Regiters and Noise???
    123440: 07/08/28: John_H: Re: Xilinx Virtex IOB Regiters and Noise???
    123441: 07/08/28: Gabor: Re: Xilinx Virtex IOB Regiters and Noise???
        123459: 07/08/28: John Retta: Re: Xilinx Virtex IOB Regiters and Noise???
    123447: 07/08/28: Analog_Guy: Re: Xilinx Virtex IOB Regiters and Noise???
123443: 07/08/28: maxascent: PCB Layers
    123445: 07/08/28: Gabor: Re: PCB Layers
        123485: 07/08/28: Ben Jackson: Re: PCB Layers
    123451: 07/08/28: vt2001cpe: Re: PCB Layers
    123456: 07/08/28: John Larkin: Re: PCB Layers
        123457: 07/08/28: maxascent: Re: PCB Layers
    123467: 07/08/28: Symon: Re: PCB Layers
    123469: 07/08/28: vsurducan@gmail.com: Re: PCB Layers
    123470: 07/08/28: vsurducan@gmail.com: Re: PCB Layers
    123480: 07/08/28: comp.arch.fpga: Re: PCB Layers
        123679: 07/09/01: Symon: Re: PCB Layers
            123681: 07/09/01: maxascent: Re: PCB Layers
                123697: 07/09/02: Symon: Re: PCB Layers
            123686: 07/09/01: KJ: Re: PCB Layers
                123699: 07/09/02: Symon: Re: PCB Layers
    123493: 07/08/29: vsurducan@gmail.com: Re: PCB Layers
123473: 07/08/28: Gabor: Re: PCB Layers
    123498: 07/08/29: Symon: Re: PCB Layers
    123499: 07/08/29: Symon: Re: PCB Layers
123474: 07/08/28: vasile: Re: PCB Layers
123483: 07/08/28: Simon: VGA controller in the EDK ?
    123486: 07/08/29: John Williams: Re: VGA controller in the EDK ?
        123488: 07/08/29: Mark McDougall: Re: VGA controller in the EDK ?
    123487: 07/08/29: Simon: Re: VGA controller in the EDK ?
    123491: 07/08/29: Simon: Re: VGA controller in the EDK ?
123489: 07/08/28: <JimboD2@gmail.com>: Problems with PLB_DDR2 core and soft reset
    123492: 07/08/29: vsurducan@gmail.com: Re: Problems with PLB_DDR2 core and soft reset
        123517: 07/08/29: Jeff Cunningham: Re: Problems with PLB_DDR2 core and soft reset
    123510: 07/08/29: <JimboD2@gmail.com>: Re: Problems with PLB_DDR2 core and soft reset
    123519: 07/08/29: <PrestonMc@gmail.com>: Re: Problems with PLB_DDR2 core and soft reset
123490: 07/08/29: Rodo: altera's USB byteblaster cable: anyone has the mindford one?
    123494: 07/08/29: Fredrik: Re: altera's USB byteblaster cable: anyone has the mindford one?
        123549: 07/08/30: Rodo: Re: altera's USB byteblaster cable: anyone has the mindford one?
123495: 07/08/29: Pablo: VHDL core to read/write to Bram_Block.
    123502: 07/08/29: Göran Bilski: Re: VHDL core to read/write to Bram_Block.
    123511: 07/08/29: <harshada.pendse@gmail.com>: Re: VHDL core to read/write to Bram_Block.
    123727: 07/09/03: Pablo: Re: VHDL core to read/write to Bram_Block.
123500: 07/08/29: <markus.jank@de.bosch.com>: Strange behaviour of a design
    123507: 07/08/29: KJ: Re: Strange behaviour of a design
    123509: 07/08/29: Gabor: Re: Strange behaviour of a design
    123524: 07/08/29: MM: Re: Strange behaviour of a design
    123553: 07/08/29: <markus.jank@de.bosch.com>: Re: Strange behaviour of a design
    123568: 07/08/30: Gabor: Re: Strange behaviour of a design
    123598: 07/08/30: <markus.jank@gmx.de>: Re: Strange behaviour of a design
    123690: 07/09/02: Kunal: Re: Strange behaviour of a design
    123691: 07/09/02: Kunal: Re: Strange behaviour of a design
    123802: 07/09/04: <markus.jank@gmx.de>: Re: Strange behaviour of a design
123504: 07/08/29: fl: Question about xflow?
    123540: 07/08/29: Duth: Re: Question about xflow?
123512: 07/08/29: selva kumar: intialize memory in fpga
    123515: 07/08/29: Symon: Re: intialize memory in fpga
    123516: 07/08/29: Erik Anderson: Re: intialize memory in fpga
    123518: 07/08/29: johnp: Re: intialize memory in fpga
123513: 07/08/29: selva kumar: memory in spartan 3 fpga
    123522: 07/08/29: Nico Coesel: Re: memory in spartan 3 fpga
    124723: 07/10/01: pete: Re: memory in spartan 3 fpga
123514: 07/08/29: Sylvain Munaut <SomeOne@SomeDomain.com>: OSERDES behavior
123526: 07/08/29: vsurducan@gmail.com: PCIe question
    123527: 07/08/29: Charles, NG: Re: PCIe question
        123546: 07/08/29: PeteS: Re: PCIe question
            123669: 07/08/31: PeteS: Re: PCIe question
                123673: 07/08/31: PeteS: Re: PCIe question
    123529: 07/08/29: Gabor: Re: PCIe question
        123544: 07/08/30: vasile: Re: PCIe question
    123545: 07/08/30: vasile: Re: PCIe question
    123652: 07/08/31: Gabor: Re: PCIe question
    123701: 07/09/02: John Adair: Re: PCIe question
123531: 07/08/29: =?iso-8859-1?B?RWRtb25kIENvdOk=?=: Registered output for Altera on-chip memory
    123586: 07/08/30: fpgabuilder: Re: Registered output for Altera on-chip memory
123533: 07/08/29: shadabambat1@gmail.com: Difference in the JTAG instructions between Virtex and Virtex II
123535: 07/08/29: EEngineer: Output signals not synchronized
    123538: 07/08/29: EEngineer: Re: Output signals not synchronized
        123543: 07/08/29: John_H: Re: Output signals not synchronized
    123570: 07/08/30: Gabor: Re: Output signals not synchronized
    123571: 07/08/30: <s.stanislava@gmail.com>: Re: Output signals not synchronized
    123572: 07/08/30: EEngineer: Re: Output signals not synchronized
    123578: 07/08/30: Gabor: Re: Output signals not synchronized
    123592: 07/08/30: EEngineer: Re: Output signals not synchronized
    123603: 07/08/30: Andy Peters: Re: Output signals not synchronized
    123613: 07/08/31: EEngineer: Re: Output signals not synchronized
123536: 07/08/29: asic1234@gmail.com: SDF File basics
    123618: 07/08/31: Jon Beniston: Re: SDF File basics
    123643: 07/08/31: asic1234@gmail.com: Re: SDF File basics
123548: 07/08/29: Ace: Where is Command Reg and Status Reg as mentioned in PCI system architecture (Mindshare) in generated pci32 core?
    123563: 07/08/30: Brian Drummond: Re: Where is Command Reg and Status Reg as mentioned in PCI system architecture (Mindshare) in generated pci32 core?
        123624: 07/08/31: Brian Drummond: Re: Where is Command Reg and Status Reg as mentioned in PCI system architecture (Mindshare) in generated pci32 core?
    123611: 07/08/30: Ace: Re: Where is Command Reg and Status Reg as mentioned in PCI system architecture (Mindshare) in generated pci32 core?
123552: 07/08/29: Piyush Kaul: Xilinx FPGA Based Board Problem
    123559: 07/08/30: Martin Thompson: Re: Xilinx FPGA Based Board Problem
    123633: 07/08/31: <SKatsyuba@gmail.com>: Re: Xilinx FPGA Based Board Problem
    123942: 07/09/07: Piyush Kaul: Re: Xilinx FPGA Based Board Problem
123556: 07/08/30: Guru: Spartan3E and DDR termination
    123567: 07/08/30: Gabor: Re: Spartan3E and DDR termination
    123581: 07/08/30: Gabor: Re: Spartan3E and DDR termination
    123615: 07/08/31: Bob: Re: Spartan3E and DDR termination
    123625: 07/08/31: Brian Drummond: Re: Spartan3E and DDR termination
        123782: 07/09/04: Ben Jackson: Re: Spartan3E and DDR termination
    123698: 07/09/02: Guru: Re: Spartan3E and DDR termination
    123773: 07/09/04: vasile: Re: Spartan3E and DDR termination
    123780: 07/09/04: Gabor: Re: Spartan3E and DDR termination
    123817: 07/09/05: vasile: Re: Spartan3E and DDR termination
123557: 07/08/30: fazulu deen: modelsim
    123558: 07/08/30: Jon Beniston: Re: modelsim
    123562: 07/08/30: fazulu deen: Re: modelsim
    123583: 07/08/30: fpgabuilder: Re: modelsim
    123587: 07/08/30: fazulu deen: Re: modelsim
    123614: 07/08/31: fpgabuilder: Re: modelsim
123564: 07/08/30: <dormanpeter1@gmail.com>: Spartan 3E starter kit (Rev.D) modification : 3E500 -> 3E1200
    123573: 07/08/30: emu: Re: Spartan 3E starter kit (Rev.D) modification : 3E500 -> 3E1200
    123580: 07/08/30: <dormanpeter1@gmail.com>: Re: Spartan 3E starter kit (Rev.D) modification : 3E500 -> 3E1200
    123700: 07/09/02: John Adair: Re: Spartan 3E starter kit (Rev.D) modification : 3E500 -> 3E1200
123569: 07/08/30: maxascent: PCB Impedance Control
    123575: 07/08/30: Symon: Re: PCB Impedance Control
        123604: 07/08/30: John_H: Re: PCB Impedance Control
            123619: 07/08/31: Symon: Re: PCB Impedance Control
                123626: 07/08/31: Brian Drummond: Re: PCB Impedance Control
                    123631: 07/08/31: Bob Perlman: Re: PCB Impedance Control
                        123637: 07/08/31: John_H: Re: PCB Impedance Control
                            123655: 07/08/31: John_H: Re: PCB Impedance Control
                                123675: 07/08/31: PeteS: Re: PCB Impedance Control
                            123671: 07/08/31: PeteS: Re: PCB Impedance Control
                        123667: 07/08/31: PeteS: Re: PCB Impedance Control
            123665: 07/08/31: PeteS: Re: PCB Impedance Control
        123610: 07/08/30: PeteS: Re: PCB Impedance Control
        123682: 07/09/01: John Larkin: Re: PCB Impedance Control
            123696: 07/09/02: Symon: Re: PCB Impedance Control
                123703: 07/09/02: Hal Murray: Re: PCB Impedance Control
                123705: 07/09/02: John Larkin: Re: PCB Impedance Control
                    123757: 07/09/04: Symon: Re: PCB Impedance Control
                        123765: 07/09/04: John Larkin: Re: PCB Impedance Control
                            123840: 07/09/05: glen herrmannsfeldt: Re: PCB Impedance Control
                                123842: 07/09/05: John Larkin: Re: PCB Impedance Control
                    123779: 07/09/04: glen herrmannsfeldt: Re: PCB Impedance Control
                        123789: 07/09/04: John Larkin: Re: PCB Impedance Control
                        123835: 07/09/05: Hal Murray: Re: PCB Impedance Control
                            123929: 07/09/06: glen herrmannsfeldt: Re: PCB Impedance Control
                        123843: 07/09/05: John Larkin: Re: PCB Impedance Control
                            123933: 07/09/06: glen herrmannsfeldt: Re: PCB Impedance Control
                        123844: 07/09/05: glen herrmannsfeldt: Re: PCB Impedance Control
                    123832: 07/09/05: John Larkin: Re: PCB Impedance Control
                        123918: 07/09/06: PeteS: Re: PCB Impedance Control
                    123833: 07/09/05: John_H: Re: PCB Impedance Control
                        123857: 07/09/06: Symon: Re: PCB Impedance Control
                    123839: 07/09/05: PeteS: Re: PCB Impedance Control
            123702: 07/09/02: Hal Murray: Re: PCB Impedance Control
                123704: 07/09/02: John Larkin: Re: PCB Impedance Control
            123801: 07/09/04: John Larkin: Re: PCB Impedance Control
                123807: 07/09/05: Symon: Re: PCB Impedance Control
                    123812: 07/09/05: John Larkin: Re: PCB Impedance Control
                        123860: 07/09/06: Symon: Re: PCB Impedance Control
                            123883: 07/09/06: John Larkin: Re: PCB Impedance Control
                    123845: 07/09/05: glen herrmannsfeldt: Re: PCB Impedance Control
            123841: 07/09/05: glen herrmannsfeldt: Re: PCB Impedance Control
                123858: 07/09/06: Symon: Re: PCB Impedance Control
                    123870: 07/09/06: John_H: Re: PCB Impedance Control
                        123877: 07/09/06: Symon: Re: PCB Impedance Control
                            123932: 07/09/06: glen herrmannsfeldt: Re: PCB Impedance Control
                        123890: 07/09/06: John Larkin: Re: PCB Impedance Control
                            123931: 07/09/06: glen herrmannsfeldt: Re: PCB Impedance Control
                    123905: 07/09/06: John_H: Re: PCB Impedance Control
                    123919: 07/09/06: PeteS: Re: PCB Impedance Control
                        123930: 07/09/06: glen herrmannsfeldt: Re: PCB Impedance Control
    123753: 07/09/03: <kayrock66@yahoo.com>: Re: PCB Impedance Control
        123766: 07/09/04: John Larkin: Re: PCB Impedance Control
123579: 07/08/30: Sebastian Goller: Reconfiguration of a XUP Board
    123582: 07/08/30: Gabor: Re: Reconfiguration of a XUP Board
123585: 07/08/30: Pasacco: Die size, pitch size?
    123591: 07/08/30: Uwe Bonnes: Re: Die size, pitch size?
        123620: 07/08/31: Symon: Re: Die size, pitch size?
            123662: 07/08/31: John_H: Re: Die size, pitch size?
            123663: 07/09/01: Jim Granville: Re: Die size, pitch size?
    123599: 07/08/30: Pasacco: Re: Die size, pitch size?
    123607: 07/08/30: Peter Alfke: Re: Die size, pitch size?
    123616: 07/08/31: Pasacco: Re: Die size, pitch size?
    123654: 07/08/31: Pasacco: Re: Die size, pitch size?
    123658: 07/08/31: Peter Alfke: Re: Die size, pitch size?
    123659: 07/08/31: Pasacco: Re: Die size, pitch size?
    123661: 07/08/31: Peter Alfke: Re: Die size, pitch size?
    123726: 07/09/03: <j.d.morrison@gmail.com>: Re: Die size, pitch size?
    123810: 07/09/05: Pasacco: Re: Die size, pitch size?
123595: 07/08/30: <siliconbluetechnology@yahoo.com>: An FPGA startup is seeking testcase from potential customers
    123608: 07/08/31: Jim Granville: Re: An FPGA startup is seeking testcase from potential customers
    123651: 07/08/31: <siliconbluetechnology@yahoo.com>: Re: An FPGA startup is seeking testcase from potential customers
    123668: 07/09/01: fpgabuilder: Re: An FPGA startup is seeking testcase from potential customers
    123724: 07/09/03: <j.d.morrison@gmail.com>: Re: An FPGA startup is seeking testcase from potential customers
123617: 07/08/31: Benni V.: Spartan 3E - Readback via JTAG
    123621: 07/08/31: Uwe Bonnes: Re: Spartan 3E - Readback via JTAG
        123730: 07/09/03: Uwe Bonnes: Re: Spartan 3E - Readback via JTAG
    123636: 07/08/31: Benni V.: Re: Spartan 3E - Readback via JTAG
123623: 07/08/31: Frai: Xilinx blockram FIFO async reset annoys me (and Modelsim)
123627: 07/08/31: Wei Wang: Is it possible to make bit files generated by Xilinx ISE readable?
    123629: 07/08/31: John_H: Re: Is it possible to make bit files generated by Xilinx ISE readable?
    123635: 07/08/31: MM: Re: Is it possible to make bit files generated by Xilinx ISE readable?
    123640: 07/08/31: Jim Wu: Re: Is it possible to make bit files generated by Xilinx ISE readable?
    123678: 07/08/31: glen herrmannsfeldt: Re: Is it possible to make bit files generated by Xilinx ISE readable?
123628: 07/08/31: Peter Mendham: Wifi with a Virtex 4
123632: 07/08/31: Simon: Memory bandwidth of the 3A kit
    123638: 07/08/31: Simon: Re: Memory bandwidth of the 3A kit
    123687: 07/09/01: Antti: Re: Memory bandwidth of the 3A kit
123642: 07/08/31: Amir: Simple Project involving microblaze
    123647: 07/08/31: young: Re: Simple Project involving microblaze
123644: 07/08/31: asimatta@hotmail.com: signal termination in spartan 3e starter kit
123645: 07/08/31: Brad Smallridge: Xilinx ML40x Mouse VHDL Wanted
    123676: 07/08/31: <ghelbig@lycos.com>: Re: Xilinx ML40x Mouse VHDL Wanted
123646: 07/08/31: asic1234@gmail.com: what does asynchronous loop mean?
    123649: 07/08/31: Hal Murray: Re: what does asynchronous loop mean?
123648: 07/08/31: young: BlockRAM connection error
    123837: 07/09/05: Paulo Dutra: Re: BlockRAM connection error
    123921: 07/09/07: young: Re: BlockRAM connection error
123650: 07/08/31: robin: Chip Designing made Easy
    123653: 07/08/31: John_H: Re: Chip Designing made Easy
    123688: 07/09/01: Antti: Re: Chip Designing made Easy
123660: 07/08/31: David Chen: How to add additional FSL interface to customized IP?
    123725: 07/09/03: Göran Bilski: Re: How to add additional FSL interface to customized IP?


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