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Some useful bits and pieces listed here http://www.enterpoint.co.uk/techitips/techitips_useful_things.html on our website. John Adair Enterpoint Ltd. www.enterpoint.co.uk On 6 Aug, 09:06, jitendra <jitendrakumarpoth...@gmail.com> wrote: > hi all, > i am new to this group and i am beginner in this FPGA field so i need > ur help to find some material regarding FPGA i hope u people can help > me out > thank uArticle: 122776
On Aug 4, 4:04 am, Eli Billauer <e...@billauer.co.il> wrote: > Hello, > > I would like to utilize a controller for a SINGLE data rate SDRAM > (Micron MT48LC16M16A2TG-75, to be specific). In the past I've used > Xilinx' MiG 1.4 to obtain a DDR2 controller, which I ended up pretty > happy with (after forgetting the via dolorosa to set it up...). Its > main benefit is a simple and convenient FIFO-based user interface. > > For some reason, I thought that MiG would create an SDR controller as > well (it's simpler, after all), but it turned out I'm very wrong: The > last piece of attention on Xilinx' behalf to SDR, which I've managed > to find, is xapp134. That paper, along with its HDL code, originates > in 1999, and is more or less the same ever since. The controller > offered is hence adapted to Virtex-I and Spartan-II, and is yucky is > several respects. > > Newer application notes (as well as MiG) relate to faster memory > classes (DDR, DDR2, QDR, you name it), with controllers eating up some > clock resources to solve timing problems. And all I wanted was a cheap > memory with reasonably simple access. > > Given the situation, I'm considering to create a DDR controller with > MiG for a memory with similar attributes (bus width, array size, etc) > and then hack it down to SDR. Since the command interface is the same, > that should leave me with changing the data flow, and make the burst > timing right. Not much fun, but hey, after debugging the MiG DDR > controller, I should survive this one as well. > > And here's the irony: I picked this SDRAM to make things simpler for > me. > > So before I start this little self torture, does anyone have a better > idea? I'm with Martin. Write your own SDRAM controller from scratch. It's really not difficult, and you can optimize it for your particular application. It shouldn't take more than a couple of days to write, simulate and verify it. -aArticle: 122777
I need to connect the Xilinx ML402 board to the 3.3V CMOS chip. I am concerned about the ESD that could burn the CMOS chip. I am concerned about the possibility of the ESD when CMOS is being connected or disconnected from the FPGA board's header, even though I would do it when both devices are turned off. I know that this depends on the chip itself, but I wonder if there are any general precautions that I could follow that would make this steps less hazardous? Is it more safe to set all the FPGA board's outputs to high impedance state once the task has been done before turning the board off? The complete loop: - FPGA creates control signals, including clock, that are sent through the board's header to the 3.3V CMOS chip. - CMOS chip generates some data on its outputs that are connected to the FPGA board's header. Thanks, -DanArticle: 122778
EEngineer wrote: > I need to connect the Xilinx ML402 board to the 3.3V CMOS chip. I am > concerned about the ESD that could burn the CMOS chip. After a quick look at the chematic the maximum supply voltage is 3.3v@3A. It would be worth checking what the maximum unloaded/no load voltage is. That will give a maximum possible voltage that this CMOS device will see if powered up. You should be putting the device in or out with the PCB powered down. You may want to discharge any supply decoupling capacitors with some cable. You are using a grounded wrist strap. Andy > > I am concerned about the possibility of the ESD when CMOS is being > connected or disconnected from the FPGA board's header, even though I > would do it when both devices are turned off. I know that this depends > on the chip itself, but I wonder if there are any general precautions > that I could follow that would make this steps less hazardous? Is it > more safe to set all the FPGA board's outputs to high impedance state > once the task has been done before turning the board off? > > The complete loop: > - FPGA creates control signals, including clock, that are sent through > the board's header to the 3.3V CMOS chip. > - CMOS chip generates some data on its outputs that are connected to > the FPGA board's header. > > Thanks, > -Dan >Article: 122779
Dan, Connecting, and disconnecting cables, or headers, of parts mounted on boards is not usually an ESD issue. ESD is thousands of volts, from static electricity accumulation (usually on your person). Usually holding each assembly in your hands is enough to insure the potential difference between them is small (your skin and body neutralizes any charge difference between the two while you hold them). This does mean that you use both hands, so the two assemblies are neutral to each other. Sounds like you are concerned about "hot plugging" or connecting and disconnecting live (or will be live soon) interfaces. So, which is it? Damage from very high static voltages? Or damage from voltages within the normal operating range of the device when inserted live into a system? As far as Xilinx FPGAs go, we publish our human body model ESD and machine model ESD specifications, and we also have no problem with live insertion (power on), as long as ground connects first, before an IO connects. The reason why we suggest that grounds mate first, is that the ground provides the return path for any transients, and the self-protecting IO structures are better at protecting themselves if they share a ground. Austin EEngineer wrote: > I need to connect the Xilinx ML402 board to the 3.3V CMOS chip. I am > concerned about the ESD that could burn the CMOS chip. > > I am concerned about the possibility of the ESD when CMOS is being > connected or disconnected from the FPGA board's header, even though I > would do it when both devices are turned off. I know that this depends > on the chip itself, but I wonder if there are any general precautions > that I could follow that would make this steps less hazardous? Is it > more safe to set all the FPGA board's outputs to high impedance state > once the task has been done before turning the board off? > > The complete loop: > - FPGA creates control signals, including clock, that are sent through > the board's header to the 3.3V CMOS chip. > - CMOS chip generates some data on its outputs that are connected to > the FPGA board's header. > > Thanks, > -Dan >Article: 122780
The error in ISE seemed to be also fixed by removing the "Perform timing driven packing and placement" option. My guess is that the special carry structures infered during synthesis came with special packing requirements (only for timing driven packing/placement) that were violated if resources couldn't be shared. I'm still awaiting further insight into this and my other problems. ---Matthew Hicks > I have a design that instantiates four copies of a module and I am > using Xilinx's AREA_GROUP constraint to partition each instantiation > into its own 1/8th sector of the FPGA. I ran across a few problems. > One, how do I convey these constraints to Synplify (v8.8) for my final > implementation run? I tried xc_area_group constraints on each > top-level instance name, but either my format is wrong or it just > doesn't feel the need to respect them, because they get placed in > rectangular fashion around the center of the FPGA. On a similar note, > would it be better to use RLOC constraints for what I am trying to do > instead? > > My main problem is in ISE 9.1.03 when attempting to Map the design. I > get > the error message below at phase 1.1. I also listed the contents of > my .ucf > file below. I don'y get this error when "Resource Sharing" is turned > on. > I still get the error though even when "Use RLOC" is off. Any > suggestions? > ERROR:Place:293 - The following 13 components are required to be > placed in a > specific relative placement form. The required relative coordinates in > the > RPM grid (that can be seen in the FPGA Editor) are shown in brackets > next to > the component names. Due to placement constraints it is impossible to > place > the components in the required form. > LUT FPU1/Madd_tmp_expAB_addsub0001_cy(1) (0, 0) > LUT FPU1/Madd_tmp_expAB_addsub0001_cy(1) (0, 0) > FF FPU1/Madd_tmp_expAB_addsub0001_cy(1) (0, 0) > LUT FPU1/Madd_tmp_expAB_addsub0001_cy(3) (0, 1) > LUT FPU1/Madd_tmp_expAB_addsub0001_cy(3) (0, 1) > LUT FPU1/Madd_tmp_expAB_addsub0001_cy(5) (0, 2) > LUT FPU1/Madd_tmp_expAB_addsub0001_cy(5) (0, 2) > LUT FPU1/Madd_tmp_expAB_addsub0001_cy(7) (0, 3) > LUT FPU1/Madd_tmp_expAB_addsub0001_cy(7) (0, 3) > LUT N14610 (0, 4) > LUT N14610 (0, 4) > LUT FPU1/Madd_tmp_expAB_addsub0001_cy(8) (0, 5) > FF FPU1/Madd_tmp_expAB_addsub0001_cy(8) (0, 5) > NET "clk" TNM_NET = "clk"; > TIMESPEC "TS_clk" = PERIOD "clk" 40 ns HIGH 50 %; > INST "FPU1/*" AREA_GROUP = FPU1Group; > AREA_GROUP "FPU1Group" RANGE = SLICE_X0Y0:SLICE_X51Y63; > AREA_GROUP "FPU1Group" RANGE = RAMB16_X0Y0:RAMB16_X1Y7; > AREA_GROUP "FPU1Group" GROUP = CLOSED; > AREA_GROUP "FPU1Group" PLACE = CLOSED; > AREA_GROUP "FPU1Group" COMPRESSION = 0; > INST "FPU2/*" AREA_GROUP = FPU2Group; > AREA_GROUP "FPU2Group" RANGE = SLICE_X0Y64:SLICE_X51Y127; > AREA_GROUP "FPU2Group" RANGE = RAMB16_X0Y8:RAMB16_X1Y15; > AREA_GROUP "FPU2Group" GROUP = CLOSED; > AREA_GROUP "FPU2Group" PLACE = CLOSED; > AREA_GROUP "FPU2Group" COMPRESSION = 0; > INST "FPU3/*" AREA_GROUP = FPU3Group; > AREA_GROUP "FPU3Group" RANGE = SLICE_X0Y128:SLICE_X51Y191; > AREA_GROUP "FPU3Group" RANGE = RAMB16_X0Y16:RAMB16_X1Y23; > AREA_GROUP "FPU3Group" GROUP = CLOSED; > AREA_GROUP "FPU3Group" PLACE = CLOSED; > AREA_GROUP "FPU3Group" COMPRESSION = 0; > INST "FPU4/*" AREA_GROUP = FPU4Group; > AREA_GROUP "FPU4Group" RANGE = SLICE_X0Y192:SLICE_X51Y255; > AREA_GROUP "FPU4Group" RANGE = RAMB16_X0Y24:RAMB16_X1Y31; > AREA_GROUP "FPU4Group" GROUP = CLOSED; > AREA_GROUP "FPU4Group" PLACE = CLOSED; > AREA_GROUP "FPU4Group" COMPRESSION = 0; > ---Matthew Hicks >Article: 122781
On 6 Aug, 08:13, "X.Y." <Xieyu1...@gmail.com> wrote:
> I use Cyclone II to implement image processing. There are a CMOS image
> sensor, a FPGA chip, and a SRAM on my board. I meet a new problem when
> I try to optimize my design. In my old instance, I use the same clock
> when image capture (storage), image display, and image processing.
> This clock, which is named "pclk", has a frequency of 24MHz. It is
> slow. The frequency of image capture and display cannot be changed
> because of the requirement of other device. So I want to increase the
> frequency of image processing. It involves SRAM reading, writing, and
> data processing. I use a PLL to acquire a clock of 72MHz. This is the
> problem. SRAM will also be read when image capture, and written when
> display. That means the clock, the address bus and data bus will be
> switched between the state of image capture/display and image process.
> Actually, I use two blocks: one for image capture/display and another
> for image process. And I use BUS MUX to switch address bus and data
> bus. Meanwhile, I use LPM MUX to switch the two clock of different
> frequency. Unfortunately, the instance does not meet timing. In Timing
> Analyzer Summary, it reports, Clock setup: 'pclk' has a slack of
> -4.152ns and Clock hold: 'pclk' has a slack of -4.216ns. What should I
> do to solve this problem?
>
> Best Regards,
> X.Y.
Assuming you are using the Classic Timing Analyzer, make sure you have
a CUT assignment between the two clock domains. In the QSF, you want
to see something like:
set_instance_assignment -from pclk -to <your pll clock name> -
name CUT ON
set_intance_assignment -from <your pll clock name> -to pclk -name
CUT ON
You can make these assignments using the Assignment Editor.
BTW, clock muxing is something the new TimeQuest Timing Analyzer does
very well. Here is an example of how to describe this in an SDC for
TimeQuest:
http://www.altera.com/support/examples/timequest/exm-tq-clock-mux.html
Hope this helps.
-David Karchmer
Altera
Article: 122782
On 8 7 , 1 08 , "John_H" <newsgr...@johnhandwork.com> wrote:
> "austin" <aus...@xilinx.com> wrote in message
>
> news:f97j08$gtp2@cnn.xilinx.com...
>
> > SATA,
>
> > Has been characterized and verified on Virtex 5 GTP transceivers.
>
> > We are preparing the report for publication.
>
> > Get with your FAE for more details,
>
> > Austin
>
> Way to go Xilinx! I also look forward to the report.
Antti,
I searched on the Silicon Image website, but I can not find the
soc as your said. Can you give me an link? Thanks.
Look forward to the report. And I don't know why the phy chip
can't be bought.
By the way, whether the function can be easily realized as
following:
PC(PCIe) <-----> FPGA board <--------> PCIe-SATA controller
<--------> SATA disk
Thanks a lot.
Article: 122783Zorjak <Zorjak@gmail.com> writes: > I know that in VHDL there is keyword "inout" when defining port, but I > don't know what detirminats that this kind defined port would be input > or output. If it's an in-out port, you have to have at least one driver (a signal assignment statement). When you want the port to be an input, assign the std_logic value 'Z' to it.Article: 122784
Hello, I try to communicate with a Digilent S3- Board via USB-Module 2 using linux (libusb). Has anybody successfully transmitted or received data this way (the win32 way works) ? best regards AndreasArticle: 122785
Eddie H wrote: > Any Ideas? Why use the GTP at all ? At 400 MBps, an ISERDES based solution should work I think. SylvainArticle: 122786
>> otherwise. I bet the noise on the supplies is a lot bigger problem than >> noise on a ground plane. (I bet they say to use LDO regs on the supplies, >> even though the B/W of such regs. are a best a few hundred kHz. A passive >> filter is much better!) >> >> HTH., Syms. Hi Symon, I am trying to design Pi filters(cap-ferrite bead-cap) for PLL analog power suplly pins(VCCA_PLL#) of a FPGA. But I do not know how to determines the bandwidth of these filters, especially the rated current value and the resistence of the Ferrite bead, cause i do not know the amplitude and the spectrum of the current feeds a VCCA_PLL#. As I know, Pi filter is widely used to isolate the power supply plane from noisy digital ICs or some noise sensitive analog circuits. http://www.fujitsu.com/downloads/MICRO/fme/displaycontrollers/bm-mb86292eb01-rev1-10.pdf (Fig2-1 "noise filter" may be implemented by Pi filter) But how to estimate the spectrum the input current of a IC? And what kind of ferrite bead should I select? Does the drop across the bead matter? Could you give me some advice? Leon,Article: 122787
On 7 Aug., 03:07, IDDLife <xing.starw...@gmail.com> wrote: > On 8 7 , 1 08 , "John_H" <newsgr...@johnhandwork.com> wrote: > > > "austin" <aus...@xilinx.com> wrote in message > > >news:f97j08$gtp2@cnn.xilinx.com... > > > > SATA, > > > > Has been characterized and verified on Virtex 5 GTP transceivers. > > > > We are preparing the report for publication. > > > > Get with your FAE for more details, > > > > Austin > > > Way to go Xilinx! I also look forward to the report. > > Antti, > > I searched on the Silicon Image website, but I can not find the > soc as your said. Can you give me an link? Thanks. > Look forward to the report. And I don't know why the phy chip > can't be bought. > > By the way, whether the function can be easily realized as > following: > > PC(PCIe) <-----> FPGA board <--------> PCIe-SATA controller > <--------> SATA disk > > Thanks a lot. look at "steelvine" products, they offer "drive lock" this I think is actually on the fly encryption SATA PHY - you can not buy. just belive me. you can try of course, but very very likely you will fail finding it the easist to get are SATA-PATA bridges they are also extremly cheap around 2 USD AnttiArticle: 122788
Thanks people. Thanks to all. You realy helped me. It is more than I expected. Thanks again ZoranArticle: 122789
On 8 7 , 4 12 , Antti <Antti.Luk...@googlemail.com> wrote: > On 7 Aug., 03:07, IDDLife <xing.starw...@gmail.com> wrote: > > > > > On 8 7 , 1 08 , "John_H" <newsgr...@johnhandwork.com> wrote: > > > > "austin" <aus...@xilinx.com> wrote in message > > > >news:f97j08$gtp2@cnn.xilinx.com... > > > > > SATA, > > > > > Has been characterized and verified on Virtex 5 GTP transceivers. > > > > > We are preparing the report for publication. > > > > > Get with your FAE for more details, > > > > > Austin > > > > Way to go Xilinx! I also look forward to the report. > > > Antti, > > > I searched on the Silicon Image website, but I can not find the > > soc as your said. Can you give me an link? Thanks. > > Look forward to the report. And I don't know why the phy chip > > can't be bought. > > > By the way, whether the function can be easily realized as > > following: > > > PC(PCIe) <-----> FPGA board <--------> PCIe-SATA controller > > <--------> SATA disk > > > Thanks a lot. > > look at "steelvine" products, they offer "drive lock" this I think is > actually on the fly encryption > > SATA PHY - you can not buy. just belive me. you can try of course, but > very very likely you will fail finding it > > the easist to get are SATA-PATA bridges they are also extremly cheap > around 2 USD > > Antti The "drive lock" actually is not the same function to encrypt the data stored in the disk. It just locks the disk. The ATA command set has the "LOCK" command to do that. I agree that the SATA phy chip is very difficult to buy. Can I realize the function using the following idea: PC(PCIe) <-----> FPGA board <--------> PCIe-SATA controller <--------> SATA disk thanks a lot.Article: 122790
Thank you for your answers. What I really wanted to verify, is that
there isn't an easy way which I've missed.
And writing a controller for a very specific purpose from scratch is
indeed not difficult, but writing one which makes a fairly good use of
the bandwidth for a reasonable, but unknown access pattern, well,
well...
So I'll stick to my previous plan to downgrade the MiG controller,
which has two great advantages: I know it, and I've seen it working.
>From what I've managed to understand, the only major difference is
startup sequence. I'll report back if I come across something worth
mentioning.
Thanks again,
Eli
Article: 122791> Thank you for your answers. What I really wanted to verify, is that > there isn't an easy way which I've missed. > > And writing a controller for a very specific purpose from scratch is > indeed not difficult, but writing one which makes a fairly good use of > the bandwidth for a reasonable, but unknown access pattern, well, > well... > > So I'll stick to my previous plan to downgrade the MiG controller, > which has two great advantages: I know it, and I've seen it working. >> From what I've managed to understand, the only major difference is > startup sequence. I'll report back if I come across something worth > mentioning. Could you use the mch_opb_sdram controller from Xilinx EDK in your application ?Article: 122792
"commone" <dechenxu@yahoo.com.cn> wrote in message news:Yo2dnQcPwrv6kiXbRVn_vgA@giganews.com... > > Hi Symon, > > I am trying to design Pi filters(cap-ferrite bead-cap) for PLL analog > power suplly pins(VCCA_PLL#) of a FPGA. But I do not know how to > determines the bandwidth of these filters, especially the rated current > value and the resistence of the Ferrite bead, cause i do not know the > amplitude and the spectrum of the current feeds a VCCA_PLL#. > > As I know, Pi filter is widely used to isolate the power supply plane from > noisy digital ICs or some noise sensitive analog circuits. > > http://www.fujitsu.com/downloads/MICRO/fme/displaycontrollers/bm-mb86292eb01-rev1-10.pdf > > > (Fig2-1 "noise filter" may be implemented by Pi filter) > > But how to estimate the spectrum the input current of a IC? And what kind > of ferrite bead should I select? Does the drop across the bead matter? > > Could you give me some advice? > > Leon, > Hi Leon, A normal design process would choose a bandwidth, and design to that. I suggest you do the same. Download LTspice from http://www.linear.com/designtools/software/ , find some spice models for ferrites and away you go. You may have a learning curve to work out how to use the tools properly, but it'll be useful for many years to come... HTH., Syms.Article: 122793
Hello. I have designed a small application on a Virtex4FX based on the Xilinx lwIP Echo Server example ( www.files.em.avnet.com/files/181/279/fx12_lc_temac_lwip_echo_server_edk9_1_01.zip ). I haven`t done any dramatic changes to the example, in general terms I modified the socket.c of the project to receive UDP packets on the TEMAC from a source IP, and retransmit them to a destination IP. After some time I managed to make everything work as I planned. But now I`m facing a problem that I don`t know how to solve. I can only transmit through the board data at a maximum rate of 1Mbps. Anything more than that is lost. eg. When i transmit at 1.4Mbps, 400Kbps of data is lost, etc. And when I try to transmit at data rates over 3Mbps, I get on Hyperterminal the error messege that the Rx Fifo is full. The data buffer I use for the data transmission, is declared as a normal Array[] variable. Is there an easy way to improve the performance of my application? Thank you in advance.Article: 122794
>"commone" <dechenxu@yahoo.com.cn> wrote in message >news:Yo2dnQcPwrv6kiXbRVn_vgA@giganews.com... >> >> Hi Symon, >> >> I am trying to design Pi filters(cap-ferrite bead-cap) for PLL analog >> power suplly pins(VCCA_PLL#) of a FPGA. But I do not know how to >> determines the bandwidth of these filters, especially the rated current >> value and the resistence of the Ferrite bead, cause i do not know the >> amplitude and the spectrum of the current feeds a VCCA_PLL#. >> >> As I know, Pi filter is widely used to isolate the power supply plane from >> noisy digital ICs or some noise sensitive analog circuits. >> >> http://www.fujitsu.com/downloads/MICRO/fme/displaycontrollers/bm-mb86292eb01-rev1-10.pdf >> >> >> (Fig2-1 "noise filter" may be implemented by Pi filter) >> >> But how to estimate the spectrum the input current of a IC? And what kind >> of ferrite bead should I select? Does the drop across the bead matter? >> >> Could you give me some advice? >> >> Leon, >> >Hi Leon, >A normal design process would choose a bandwidth, and design to that. I >suggest you do the same. Download LTspice from >http://www.linear.com/designtools/software/ , find some spice models for >ferrites and away you go. >You may have a learning curve to work out how to use the tools properly, but >it'll be useful for many years to come... >HTH., Syms. > > > Hi Symon, Check out this link: http://focus.ti.com/lit/ug/spru889/spru889.pdf The design example on page 51 tells me how to design a Pi filter for Fig4-14. But now I try to design a filter as fig4-16. Then what kind of bandwidth should I choose? Thanks Leon,Article: 122795
"commone" <dechenxu@yahoo.com.cn> wrote in message news:DvmdnUUttI-I-CXbRVn_vgA@giganews.com... > Hi Symon, > Check out this link: > http://focus.ti.com/lit/ug/spru889/spru889.pdf > > The design example on page 51 tells me how to design a Pi filter for > Fig4-14. But now I try to design a filter as fig4-16. Then what kind of > bandwidth should I choose? > > Thanks > Leon, > Hi Leon, That stuff in Fig4-14 looks dodgy at first glance, I wouldn't do that myself. Anyway, I digress. For a power supply you would ideally require a very low bandwidth. After all, passing DC is the requirement. You need to decide what noise on the power supply you want to keep from your IC power. Also, the filter will prevent noise from the IC switching its supply current from getting back to the main power supply. For example, if you have a switching power supply going at (say) 1MHz, you might want to filter that noise out. BTW., Ferrites are not always much use at lower frequencies, you might need a 'proper' power inductor. HTH., Syms.Article: 122796
> I can only transmit through the board data at a maximum rate of 1Mbps.= > Anything more than that is lost. You mean "to the board", not "through", yes ? > eg. When i transmit at 1.4Mbps, 400Kbps of data is lost, etc. > And when I try to transmit at data rates over 3Mbps, I get on > Hyperterminal the error messege that the Rx Fifo is full. Well, I have never used Virtex4, but I have used a FPGA board (Suzaku) = = with LAN91c111 MAC chip. This, running Microblaze/ucLinux, achieved an ethernet bandwidth of... = 2 = Mbps. Yes, that's a bit more than 200 kilobytes per second, ie. ridiculo= us. TCP handles retransmissions, so full FIFOs causing lost packets will sl= ow = down your throughput, but the packets will be retransmitted. If, however, you need more throughput, or use UDP, you have a problem. If you only need a few megabits/s with UDP, you still have a problem : = = the PC will sometimes pause for a few tens of milliseconds (disk access,= = whatever), and then send the backlog of packets at full wire speed, whic= h = will zap your RX buffers. So if you need UDP without packet loss, you need to be able to absorb t= he = full wire speed (100M or 1G depending on your application). If you need = = less than 100 Mbps throughput, it can be useful to configure the etherne= t = on 100 Mbits instead of 1 Gbits (but then the switch might zap the packe= ts = if you use a switch !) UDP has no transmission guarantee ; however if your receiving hardware = = can pull the packets from the FIFO faster than they come (ie. handles 10= 0 = Mbps without sweating), and your network has no funky topology like = inter-switch bottlenecks etc, you will find that you can run the thing f= or = 10 hours straight and not lose a single packet. Wired Ethernet is very = reliable. Your problem is that lwIP is a TCP stack designed for simple embedded = aplications, to add TCP-IP to a microcontroller, at low bandwidth, with = a = small code footprint. It is not at all designed for high throughput ! Embedded Linux has another problem : it has too many features, so a lot= = of CPU is used to process the received network data. This is not a probl= em = when you have a 3 GHz Core 2 CPU. However, on a 50 MHz Microblaze, that'= s = a different story. So, if you intend to use UDP for high throughput data transfer, you'll = = need to ditch lwIP and write your own very simple network stack. If your TEMAC supports scatter/gather DMA, set it up with a large RX ri= ng = buffer, preferably a few megabytes in SDRAM, so that it can receive many= = packets and write them to memory very fast. Then, to handle a received packet, write simple C code like this : - If packet is ARP query, answer query - If packet is UDP with destination =3D myself, parse packet - all other cases, drop packets This will take about 3 pages of C code, very simple, very efficient. If you can't use hardware for UDP checksums, ignore them on receive, se= t = them to 0 on sends. UDP checksums are useless on LAN anyway, since there= = is Ethernet CRC for data integrity check. Do not copy packet data at least 3 times like lwIP does ! Do everything= = in-place, recycle your buffers, etc. If you need to copy data, use a DMA core, but first ask yourself, do yo= u = really need this copy ? You could do some clever buffer recycling instea= d.Article: 122797
On Aug 7, 12:51 pm, PFC <li...@peufeu.com> wrote: > > Thank you for your answers. What I really wanted to verify, is that > > there isn't an easy way which I've missed. > > > And writing a controller for a very specific purpose from scratch is > > indeed not difficult, but writing one which makes a fairly good use of > > the bandwidth for a reasonable, but unknown access pattern, well, > > well... > > > So I'll stick to my previous plan to downgrade the MiG controller, > > which has two great advantages: I know it, and I've seen it working. > >> From what I've managed to understand, the only major difference is > > startup sequence. I'll report back if I come across something worth > > mentioning. > > Could you use the mch_opb_sdram controller from Xilinx EDK in your > application ? The mch_opb_sdram controller is the same shit. He would only get a bunch of stuff that he does not need and low bandwidth. GuruArticle: 122798
400Mbps is the power-up speed but eventually it needs to run at higher speed not supported by the Select I/O. Is it possible to feed the GTP output from V5 back to the V5 Select I/O differential input? The output will then go in the FPGA fabric and the FPGA will inturn genetrate the single ended 1.5V output. The advantage with this approach is that we are dealing with fixed known delays from power cycle to power cycle. Question is can the select I/O differential input accept the GTP output which is of CML type. I can not use the GTP receiver as it requires 8b/10b enabled and probably more work. Prefer to use the select I/O. EddieArticle: 122799
Thank you for your reply PFC. Really helpful information. I forgot to mention some information about my application, It's using UDP, with a Gigabit Ethernet controller and Xilinx's Microkernel (XMK). I knew that lwip and XMK were going to cause me delays, but I never expected to be such great! Unfortunately there is no time for me to redesign the application to achieve a good throughput, but I have learnt my lesson.
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