Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Jul 25, 4:11 am, n...@puntnl.niks (Nico Coesel) wrote: > Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid> wrote: > >Hi all, > > >For a new project we will need an FPGA and need to select one, so the > >question is: Altera or Xilinx? > > >The designs needs a serial bus with automatic module enumeration (2 - 12 > >changeable modules, not hotplug), access control (master slave probably), > >buffers at each module (< 1kB), fixed timing, 10 - 40 Mbs. The master > >module will need aditional buffering, ethernet and a processsor (probably > >next to the fpga, not inside, but who knows). Slaves may or may not > >require a (simple) processor. And in future there may be a need for > >digital signal filters in some new slaves, but that could also be > >implemented in a DSP. > > >My guess is that if it wasn't for the buffers, it could probably fit > >inside a CPLD. > > >Any insights in what is the best FPGA for this (and other) application? > >What is the major difference, are the differences, between Altera and > >Xilinx? > > I'm under the impression that Altera parts are much easier to obtain > in small quantities. Most 'hobbiest' projects seem to use Altera > parts. Every time I buy Xilinx parts, I'll have to meet minimum order > values so sometimes I must buy more devices than I actually need. > > Also if you really want to push an FPGA to its limits (space/speed) it > is almost impossible to write FPGA independant code. So whatever you > choose, you'll probably get stuck to it because changing vendors will > require re-learning the quirks, tricks and basic fpga elements. > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U opwww.adresboekje.nl I've bought small quantities of Xilinx parts from DigiKey. -Dave PollumArticle: 122301
> <snip> > > Do you use bypass capacitors from power to ground? I do have one 0.1 uF multi layered ceramic (dipped) on the power/gnd pins on the right facet.Article: 122302
I made another test today, I put the MDIO_0_T signal on a testpoint available on my board. It goes high only during the turn-around bit! I guess it should be high during the read phase also. I have opened a webcase, wait and see ...Article: 122303
> > I hate to ask the obvious - but have you simulated the design at this > clock rate? I haven't used the xc95xx stuff but certainly when I use a > Spartan, simulation is the key to making a deisgn that does what I > want it - and if it works, it narrows any problems to the hardware. > Is this modelsim?Article: 122304
Brian, I am also recently (last two weeks) disappointed in the Xilinx website availability. There have been some breakdowns with our provider, and we are also transitioning to a whole new web site content management system. A bit like replacing the engine on an airplane while flying. I have to use it as well! In fact, to get answers, I file a webcase. It is faster than any other method (unless I know exactly who has the answer, in which case I may call them, or email them. But with ~ 3,000 employees, that is pretty hard to do). I apologize in advance for any difficulties, but please continue to check back: it will be back, and be back better than before. AustinArticle: 122305
All, The V5 FX family is open for early access, and yes, it has a PowerPC(tm) processor. I am sure that you have also read Antti's post, so he has already "spilled the beans" about which version it is. Xilinx decided to see which IP provider had the best 'deal' for the core, so it is licensed from a third party (who licenses from IBM). The advantage to Xilinx is that at 65nm we have the RTL code (the 405 was full custom from IBM in both 130 and 90nm). Having the RTL allows us to do much more than we have done in the past. It allows our PowerPC team to craft a much better solution for our customers. The silicon for the FX is back, and in house, so we are very very busy with Verification and Characterization (V&C). Contact your FAE, disti, or rep, for details. Right now we have many units in ovens at 100C (and freezers at -40C) running Quake, Linux, etc. to shake out all the bugs. Some of the nice new features are: integrated APU, 5-way crosspoint buss switch with scatter-gather DMA controllers, 64K data and instruction caches with parity (for soft error flush, and re-fetch)... AustinArticle: 122306
On 7 25 , 6 30 , Peter Alfke <pe...@xilinx.com> wrote: > Just another case of several nice people trying to answer an > incomplete and confusing question. > We recently have had too many of this type. > Peter Alfke > > On Jul 24, 2:20 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > > > Then he would only need to add at 15.3 MHz which should be pretty easy to do. > > > ---Matthew Hicks > > > > On Jul 24, 1:32 pm, Peter Alfke <pe...@xilinx.com> wrote: > > > >> We still do not know the width of the adder. > > >> If it's a bit-serial 3-input adder, that takes only 4 LUTs plus two > > >> flip-flops, and the combinatorial chain is only through two LUTs, so > > >> it should easily meet the speed requirements. > > >> Peter Alfke, Xilinx Applications > > >> On Jul 24, 7:18 am, skyworld <chenyong20...@gmail.com> wrote: > > > >>> On 7 24 , 9 48 , John_H <newsgr...@johnhandwork.com> wrote: > > > >>>> skyworld wrote: > > > >>>>> Hi, > > > >>>>> I have to design with 3 input adder, i.e. D = A + B + C, in > > >>>>> Spartan 3E. The addition has to be finished in one 153.6MHz clock. > > >>>>> When I do PAR, I met timing violations. Can anybody give me some > > >>>>> advices on how to implement this design? (I can't upgrade to other > > >>>>> device because of cost). Thanks very much. > > > >>>>> best regards > > > >>>>> skyworld > > > >>>> How large are the vectors you're adding? > > > >>>> Have you looked at the timing analysis of your path to sanity-check > > >>>> the timing violations? If you have long routing delays, that can > > >>>> be accommodated with relative placements to keep the > > >>>> register-to-adder and adder-to-adder routing delays down. Getting > > >>>> on and off the carry chain may limit you at this speed. > > > >>>> You may have to ask yourself if your requirement is *really* three > > >>>> adds in one cycle. What do you do with the data after the clock? > > >>>> Comparing to a constant, for instance, would allow you to take the > > >>>> difference of the constant with A in the first cycle and compare to > > >>>> a B+C result rather than a direct comparison to A+B+C. If the > > >>>> logic generating any two vectors is simple enough, the values could > > >>>> be generated and the difference taken before the first register. > > > >>>> I do know that a divider that needed to completely daisy-chain four > > >>>> 14-bit add/subtract stages per cycle was only happy at 66 MHz with > > >>>> some RLOC constraints. Your situation is a little better since > > >>>> you're not MSB carry-out to LSB, but not much. The time to get on > > >>>> and off that carry chain may swamp your results. > > > >>>> - John_H > > > >>> Hi John, > > > >>> in fact this design is for sigme-delta transmission modulator. I > > >>> need a filter to transform 10 bit parallel input data (15.36MHz) to > > >>> one bit output stream (153.6MHz). The filter are composed by 3 stage > > >>> adders. Each adder has three inputs, i.e., what I have mentioned D = > > >>> A + B + C. Every adder has to finish A + B + C within one 153.6MHz > > >>> clock so that 153.6Mbps data stream works well. I have tried to use > > >>> pipeline adder, but for this structure failed. So I am searching a > > >>> way for "fast adder algorithm", or "fast three input adder > > >>> algorithm", which could be implemented in Spartan 3E and runs fast > > >>> enough. Thanks very much. > > > >>> skyworld > > > > In the OP's second post he did say: "I need a filter to transform 10 > > > bit parallel input data (15.36MHz) to one bit output stream > > > (153.6MHz)." So I assumed that he meant 10-bits parallel data is > > > input, then multipled and added, and then the ten-bit result is > > > shifted out 1-bit at a time. > > > -Dave Pollum Hi Gentlemen, Sorry to give you with an imcomplete question. well, the design could be described as: always @ (posedge clk) begin a1 <= a1 + in11 + in21; a2 <= a2 + in21 + in22; a3 <= a3 + in31 + in32; end all these adders are 32 bit wider, and the in21/in22/in23 are output of mux, the control signal of the mux is determined by a3. are these information enouge to the question? thanks.Article: 122307
I've done "Simulate Behavioural Model" from the ISE, it worked.Article: 122308
BTW I had to reduce the divider counter to 1 bit, otherwise there are 4 million simulation steps per second timer clock.Article: 122309
> I don't quite understand Verilog, but I don't see that the output of
> your 22-bit counter has any affect on your 5-bit counter. Shouldn't
> you have something like:
> if cdiv = 1
> aa <= aa + 1;
Sorry, posted wrong code, here is the correct code
`timescale 1ns / 1ps
module counter (
input wire c0,
input wire c1,
output reg [5:0] aa,
output wire cdiv
);
reg [21:0] nn;
assign cdiv= nn[21];
always @(posedge c0)
nn=nn+1;
always @(posedge c1)
aa <= aa + 1;
endmodule
Article: 122310On Jul 12, 7:20 pm, Mark McDougall <ma...@vl.com.au> wrote: > spaceg...@gmail.com wrote: > > I deasserted a the majority of the configuration signals > > since asserting would cause interrupts, error reports, etc. Uploading > > the design as-is does not work, so clearly I am missing something. > > I don't have any experience withPCIecores, but for PCI the core needs to > be able to handle configuration cycles (at least) in order for the BIOS to > probe the device. So basically most of the functionality required for > transaction processing must be in place in even aminimaldesign. > > If I were you I'd instantiate a fully functional/connected core and work > backwards from there... > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266 Thanks. I took your suggestion and created a full design using Xilinx's example design and ISE. After I got that working I just removed the pieces that I didn't need. The funny thing is that I got pretty much the same design as I had originally with the exception a buffer attached to sys_reset_n and the following for clock management settings. defparam sys_clk_mgt.SYNCLK1OUTEN = "ENABLE"; defparam sys_clk_mgt.SYNCLK2OUTEN = "DISABLE"; Well....lesson learned. Thanks again.Article: 122311
"skyworld" <chenyong20000@gmail.com> wrote in message news:1185378848.473707.135320@e16g2000pri.googlegroups.com... > > Hi Gentlemen, > > Sorry to give you with an imcomplete question. > > well, the design could be described as: > > always @ (posedge clk) > begin > a1 <= a1 + in11 + in21; > a2 <= a2 + in21 + in22; > a3 <= a3 + in31 + in32; > end > > all these adders are 32 bit wider, and the in21/in22/in23 are output > of mux, the control signal of the mux is determined by a3. > > are these information enouge to the question? thanks. skyworld, I thought this was a 10-bit modulator, so why 32 bits? You cannot get two 32-bit adders at 156 MHz in your device for a speed grade you didn't mention. Can you generate adders in a previous step to provide in11+in21 (should this be in11+in12?), in21+in22, and in31+in32? You can add another step to the pipeline and perform the 2-input additions in separate cycles. If you ABSOLUTELY cannot accept the added 6 ns latency, tell us how the inNN vectors are generate. Perhaps there's a way to get the in21+in22 style result in the previous cycle where the inNN registers are generated. Sometimes simple logic can be pulled into an adder. Also, what do you do with the a1, a2, and a3 values? You may similarly be able to push the accumulator into the next cycle and use the result combinatorially if your post-add logic is simple. When you can't reach speed, either redistribute the code or rethink your system needs to allow more pipelining. - John_HArticle: 122312
> Sorry, posted wrong code, here is the correct code > > `timescale 1ns / 1ps > > module counter ( > input wire c0, > input wire c1, > output reg [5:0] aa, > output wire cdiv > ); > > reg [21:0] nn; > assign cdiv=3D nn[21]; > > always @(posedge c0) > nn=3Dnn+1; Shouldn't this be a "<=3D" ? > always @(posedge c1) > aa <=3D aa + 1; > > endmodule Well, you have various options : - your verilog code is wrong (ie it compiles but it doesn't do what you= = think) : check your compilation warnings. - you have a gremlin (signal integrity problem, ground bounce...) then = = please upload a schematic, layout, or digicam shot of your stuff on some= = image sharing site and put the link here.Article: 122313
Vincent, I suspect that there is an installation issue or environment variable problem. J.33 is an internal build code that translates to the 9.1i build (no service packs). For a 9.2.01i build, the internal build code should be J.37. Is it possible that you have one install on top of another? -David "dude" <califrancais@gmail.com> wrote in message news:1185267993.051778.63860@k79g2000hse.googlegroups.com... > hello, > > we are trying to compile a v5 sx95t running 9.2 on linux red hat 9, > but we are unable to pass the map step > (ngdbuild went fine) > > any clue ? > > cheers > Vincent > > Release 9.2.01i - Map J.33 > Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. > Using target part "5vsx95tff1136-1". > FATAL_ERROR:Portability:PortDynamicLib.c:358:1.27 - dll open of > library > </common/soft/xilinx9.2i_lnx/virtex5/bin/lin/libMapRain.so> failed > due to > /common/soft/xilinx9.2i_lnx/virtex5/bin/lin/libMapRain.so: > undefined symbol: > > _ZN17pktba_TaskManager9openPCubeEP13XCad_CadModelP7Xdm_TxnRPK10Xdm_DesignR9pk > sba_Log. Process will terminate. For more information on this > error, please > consult the Answers Database or open a WebCase with this project > attached at > http://www.xilinx.com/support. > make[1]: *** [module_top_map.ncd] Error 91 >Article: 122314
On 25 Jul., 17:10, austin <aus...@xilinx.com> wrote: > All, > > The V5 FX family is open for early access, and yes, it has a PowerPC(tm) > processor. > > I am sure that you have also read Antti's post, so he has already > "spilled the beans" about which version it is. > > Xilinx decided to see which IP provider had the best 'deal' for the > core, so it is licensed from a third party (who licenses from IBM). > > The advantage to Xilinx is that at 65nm we have the RTL code (the 405 > was full custom from IBM in both 130 and 90nm). Having the RTL allows > us to do much more than we have done in the past. It allows our PowerPC > team to craft a much better solution for our customers. > > The silicon for the FX is back, and in house, so we are very very busy > with Verification and Characterization (V&C). Contact your FAE, disti, > or rep, for details. Right now we have many units in ovens at 100C (and > freezers at -40C) running Quake, Linux, etc. to shake out all the bugs. > > Some of the nice new features are: integrated APU, 5-way crosspoint buss > switch with scatter-gather DMA controllers, 64K data and instruction > caches with parity (for soft error flush, and re-fetch)... > > Austin Austin the "440" was spilled by an Xilinx employee in August 2006... ;) AnttiArticle: 122315
Another problem (less serious), while programming the device, if I leave the oscillator connected the programmer fails, whereas if I revice the oscillator it works. (funny?) Another clue, I use the power supply from my usb port as I haven't got a dedicated 5V supply, measuring the voltage near the device reads 4.75v and current through device is 70mA without oscillator and 85mA with oscillator. "PFC" <lists@peufeu.com> wrote in message news:op.tv04bwlmcigqcu@apollo13... > Sorry, posted wrong code, here is the correct code > > `timescale 1ns / 1ps > > module counter ( > input wire c0, > input wire c1, > output reg [5:0] aa, > output wire cdiv > ); > > reg [21:0] nn; > assign cdiv= nn[21]; > > always @(posedge c0) > nn=nn+1; Shouldn't this be a "<=" ? > always @(posedge c1) > aa <= aa + 1; > > endmodule Well, you have various options : - your verilog code is wrong (ie it compiles but it doesn't do what you think) : check your compilation warnings. - you have a gremlin (signal integrity problem, ground bounce...) then please upload a schematic, layout, or digicam shot of your stuff on some image sharing site and put the link here.Article: 122316
Antti, Very hard for me to keep track of "leaks"... Austin Antti wrote: > On 25 Jul., 17:10, austin <aus...@xilinx.com> wrote: >> All, >> >> The V5 FX family is open for early access, and yes, it has a PowerPC(tm) >> processor. >> >> I am sure that you have also read Antti's post, so he has already >> "spilled the beans" about which version it is. >> >> Xilinx decided to see which IP provider had the best 'deal' for the >> core, so it is licensed from a third party (who licenses from IBM). >> >> The advantage to Xilinx is that at 65nm we have the RTL code (the 405 >> was full custom from IBM in both 130 and 90nm). Having the RTL allows >> us to do much more than we have done in the past. It allows our PowerPC >> team to craft a much better solution for our customers. >> >> The silicon for the FX is back, and in house, so we are very very busy >> with Verification and Characterization (V&C). Contact your FAE, disti, >> or rep, for details. Right now we have many units in ovens at 100C (and >> freezers at -40C) running Quake, Linux, etc. to shake out all the bugs. >> >> Some of the nice new features are: integrated APU, 5-way crosspoint buss >> switch with scatter-gather DMA controllers, 64K data and instruction >> caches with parity (for soft error flush, and re-fetch)... >> >> Austin > > Austin the "440" was spilled by an Xilinx employee in August > 2006... ;) > > Antti > > > > >Article: 122317
Using PCI shouldn't be a problem but if your board is effectively the processor master then you need to configure the other card using the IDSEL lines and configuration cycles. It is possible your FPGA card does bot support driving the IDSEL lines but some simple mods can usually sort that out. Clocks and bus grant/request lines can also be an issue. Otherwise your PCI core may limit your ability to act as master depending on how ir is implemented. Our core implements these additional features as a tag on and we can configure the target function from the internal OPB bus allowing the target function capability of the FPGA board. John Adair Enterpoint Ltd. www.enterpoint.co.uk On 25 Jul, 12:38, awa <ameliaw.az...@gmail.com> wrote: > Hi, > > I was wondering if anyone has ever use FPGA to communicate with > another board that use PC/104 plus bus as the interface? To give a > better view, I have one firewire board that uses a PCI-to-1394 host > chip and another board that has an FPGA on it. I would like to control > the firewire by using the FPGA. Does anyone has any suggestion on how > to do this? > > I've tried using Xilinx PCi IPCore but did not work. I was wondering > if I might need to use OPB bridge instead. I am open to any > suggestion. > > Cheers!Article: 122318
On 25 Lug, 11:12, jetm...@hotmail.com wrote: > Andrea05 ha escrito: > > > Is it possible in to define something like Xint32 but for 64bit? > > I successfully use the following in EDK for PPC405: > > typedef unsignedlonglongulong64; > typedef signedlonglongslong64; > > Regards, > Marc Thank you guys, the solution is the one suggested by Marc. Also using Microblaze processor is it possible to define a long long variable (which is the uint64_t type suggested by Eric). I don't know how slow is to use this kind of type but it defenitevely works! Thanks again, AndreaArticle: 122319
Eric The shop will show these modules when the new batch comes in shortly and we have stock built and tested. The first batch were sold out before we could put it up on the shop. The shop website is undergoing a major overhaul currently and a few things will be tidyed up. The sister product Drigmorn1 will also appear shortly after that with a slightly different pin arrangement. As always our engineering sub-site (maintained by the engineers and not sales) will always show products first due to the speed which we can place information on that section without rebuilding databases and so on. The shop does tend to lag a bit so please do ask if in doubt. For those buying our offices and labs have not been flooded although many places too far away have been. We have had problems getting the team into the office due to a lack of driveable roads but that is currently improving substantially. Couriers are also getting back to normal and providing we don't get much more rain I think we will be running nearly normally by early next week. John Adair Enterpoint Ltd. www.enterpoint.co.uk On 24 Jul, 23:23, Eric Smith <e...@brouhaha.com> wrote: > Symon wrote: > > There's a bloke (John Adair) that posts on here whose company sells stuff > > like that. > >http://www.enterpoint.co.uk/component_replacements/craignell.html > > Looks like it may be suitable. It's disconcerting that the "Shop" link > goes to a web store that doesn't appear to actually offer the product. > I'll send them email.Article: 122320
On 25 Jul., 19:51, austin <aus...@xilinx.com> wrote: > Antti, > > Very hard for me to keep track of "leaks"... > > Austin > > > > Antti wrote: > > On 25 Jul., 17:10, austin <aus...@xilinx.com> wrote: > >> All, > > >> The V5 FX family is open for early access, and yes, it has a PowerPC(tm) > >> processor. > > >> I am sure that you have also read Antti's post, so he has already > >> "spilled the beans" about which version it is. > > >> Xilinx decided to see which IP provider had the best 'deal' for the > >> core, so it is licensed from a third party (who licenses from IBM). > > >> The advantage to Xilinx is that at 65nm we have the RTL code (the 405 > >> was full custom from IBM in both 130 and 90nm). Having the RTL allows > >> us to do much more than we have done in the past. It allows our PowerPC > >> team to craft a much better solution for our customers. > > >> The silicon for the FX is back, and in house, so we are very very busy > >> with Verification and Characterization (V&C). Contact your FAE, disti, > >> or rep, for details. Right now we have many units in ovens at 100C (and > >> freezers at -40C) running Quake, Linux, etc. to shake out all the bugs. > > >> Some of the nice new features are: integrated APU, 5-way crosspoint buss > >> switch with scatter-gather DMA controllers, 64K data and instruction > >> caches with parity (for soft error flush, and re-fetch)... > > >> Austin > > > Austin the "440" was spilled by an Xilinx employee in August > > 2006... ;) > > > Antti- Zitierten Text ausblenden - > > - Zitierten Text anzeigen - ;) eh I just did not want the credits... aArticle: 122321
On Jul 24, 6:02 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > "Gabor" <ga...@alacron.com> wrote in message > > news:1185308366.265115.156820@m3g2000hsh.googlegroups.com... > > > > > On Jul 24, 9:39 am, John_H <newsgr...@johnhandwork.com> wrote: > >> devices wrote: > >> > "Jim Granville" <no.s...@designtools.maps.co.nz> wrote in message > >> >news:46a51c8d$1@clear.net.nz... > > >> >> Serial EE proms, have chosen a polling system for their 'wait' > >> >> requirements. > > >> >> -jg > > >> > Yeah, i notice the Ack polling in Microchip's seeproms. > > >> > By the way, are royalties still due to Philips? Or have the copyrights > >> > expired. Just curious, i read something about it time ago. > > >> > bye, Jim > > >> If you limit yourself to 400 kHz and 10 bit addressing, no royalties. > >> Our company contacted the Philips legal folks a couple years ago to > >> clear it up for ourselves. > > > Do you mean no more than 400 KHz and no more than 10 bits? Or > > should there be royalties for 100 KHz and 7 bit addressing? > > The last time I talked with Philips they said it was okay to > > use I2C if there were Philips chips on the bus. In our case > > this is generally true. > > There are I2C implementations that exceed 400 kHz (1.6 MHz?) and/or have > greater than 10-bit addressing. It's these items which are still covered by > Philips patents. 100 kHz and 7 bit is fine according to what we got > directly from the patent holders. O.K. I went to NXP.com and found a link to this page: http://www.semiconductors.philips.com/buses/i2c/licensing/index.html which pretty much says they're not charging royalties for licenses although it doesn't go so far as to say you don't need a license... There's no mention of high-speed I2C licensing. Is this under a different patent holder (i.e. not Philips)?Article: 122322
John Adair <g1@enterpoint.co.uk> wrote: >Eric >The shop will show these modules when the new batch comes in shortly >and we have stock built and tested. The first batch were sold out >before we could put it up on the shop. The shop website is undergoing >a major overhaul currently and a few things will be tidyed up. Could you not just list everything, and simple put a note "out of stock" instead ..?, otherwise one is lead to think that you simple just don't have it at all.Article: 122323
Dear Group, I am using xilinx ise8.2i , xc9536, and I have some questions One of the documentation files leds.pdf exaplains how much current will be available when the anode is connected to 5V and the cathode to the device. However, my situation is reverse, I want to connect the cathode to 0V and the anode to the device. Why is this not mentioned? In document qst.pdf there is a simple simulation of a counter in page 17. Does this apply only to the vhdl counter, or also to the verilog counter, because there is also a wizard for "verilog test fixture" . I tried to follow the instructions for the "test bench waveform" wizard and the clock picture was completely black??? Finally, chose the "verilog text fixture" and got the following initial begin // Initialize Inputs c0 = 0; c1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end What is this global reset, is it something which only belongs in simulation, or should I have something physical on my development board?Article: 122324
Stef <stef33d@yahooi-n-v-a-l-i-d.com.invalid> wrote: >Hi all, >For a new project we will need an FPGA and need to select one, so the >question is: Altera or Xilinx? Xilinx (and Actel?) have free linux version of their programming tool. Which Altera doesn't.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z