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Bob, Good point: depending on his requirements, he may have to BOTH send a high quality, low jitter clock to all FPGAs, AND forward clocks from each FPGA to other ones for source synchronous transfer operation on his communications between devices. AustinArticle: 121751
NGDBUILD done. Process "Translate" completed successfully Now I have this error during mapping : ERROR:LIT:297 - BUFG or BUFGCTRL are the only valid components that can drive REFCLK pin of IDELAYCTRL symbol mem_interface_top_inst1/mem_interface_top_idelay_ctrl0/idelayctrl0.Article: 121752
Jan, Seems there are other announcements in this area, too: http://www.eetimes.com/rss/showArticle.jhtml?articleID=201000153&cid=RSSfeed_eetimes_newsRSS I would absolutely just love it if open source IP for FPGAs could be a vibrant and healthy business! But it seems that there is enough difference between the open software world, and the open hardware world to make it not to be. So, the question is: what is needed to make the model work? AustinArticle: 121753
On a sunny day (Thu, 12 Jul 2007 10:48:18 -0700) it happened austin <austin@xilinx.com> wrote in <f75ph2$fld2@cnn.xilinx.com>: >Jan, > >Seems there are other announcements in this area, too: > >http://www.eetimes.com/rss/showArticle.jhtml?articleID=201000153&cid=RSSfeed_eetimes_newsRSS > >I would absolutely just love it if open source IP for FPGAs could be a >vibrant and healthy business! But it seems that there is enough >difference between the open software world, and the open hardware world >to make it not to be. > >So, the question is: what is needed to make the model work? FPGA's in DIL 48 pin packages available in local and online shops at low prices.Article: 121754
On Jul 11, 5:46 pm, Totally_Lost <air_b...@yahoo.com> wrote: > On Jul 11, 5:41 pm, Jim Granville <no.s...@designtools.maps.co.nz> > wrote: > > > The specific example here was a 3rd party tool flow issue, and quite > > a long time ago. As a 3rd party issue it is not entirely Xilinx's fault. > > It even seemed there was a design solution, just no longer free. > > The specific issue was ISE and it's synthesis tool, and that Xilinx > terminated a 3rd party agreement and went inhouse with XST, failing to > provide continutity of synthesis ability for existing registered users > of ISE because they didn't want to spend the money to include XC4K > support in XST. > > That was a breach of contract for registered ISE users like myself at > the time, as when I asked for a new license, they were unable to > deliver an alternate synthesis for the product I purchased when they > terminated the 3rd party contract. > > It's in this specific context that Austin's statements are a clear > missrepresentation. That XC4K business decison by Xilinx cost me > dearly, almost loosing my home, and business. So when he slams their > competitors and states Xilinx has always taken the mornal high ground > here, and never caused their customers concern about product > support .... let's just agree, that is a lie. > > The point is, that Xilinx could have included XC4K support in XST, and > by choosing not do, caused thousands of Xilinx users (including many > students with XC4K student boards and educational ISE licenses) an > clear economic loss from the decision removing VHDL/Verilog license > availablity or replacement with XST. > > So, this is not spin (AKA a politically or socially correct lie) ... > this is gross missrepresentation by Austin, specifically to place > Xilinx competitors at a disadvantage, and misslead new Xilinx > customers about their past. I'm confused... I distinctly remember many emails from Xilinx about the end of FPGA Express support, and several options for for the future. A perception I had (from those emails) was that it was a rather nasty divorce. I'm willing to believe that Xilinx did all they could to support their customers; I got a good deal of help from their support staff preparing for the future. I chose to sand-bag a copy of ISE-4.2 just in case I ever had to fix any of my Spartan-I or 4K designs. Last time I checked, it worked just fine; the FPGA-Express license hadn't expired, nor had ISE stopped working. In a way, they did me a favor by dropping support for those devices. I'm real happy to never do a Spartan-I design ever, ever again. G.Article: 121755
In comp.arch Maurice Branson <traubenuss@arcor.de> wrote: > Hello, > > designing a motherboard featuring a Virtex-4 FX140 FPGA with 24 integrated > RocketIOs (Gigabit SerDes IOs) I am now facing the problem of how to get the > signals off the board in a most space-saving and elegant way? > > All 24 differential signals will be connected to some DACs outside the > motherboard to convert the signals into the analog signal domain. > > In the definition of the interface I have nearly all effective degrees of > freedom. I once learned that coaxial connections are the most appropriate > way to do so in terms of signal integrity, but with 24 differential signals > and bidirectional connections that would mean at least 96 SMA connectors > (that takes very large board space and implies some skew problems due to the > differences in the line lengths). > > I once used the Tyco ZDOK system (plug + receptacle) for board-to-board > connections with up to 80 parallel signals but unfortunately the > performance was not satisfactory, so I won't be using them again. Are there > any other interface systems for the above described purpose or ways to build > a highly-parallel highspeed connection between two boards? > > I appreciate every kind of suggestion and help. Thanks a lot in advance. > > Regards, Maurice What's the required signaling rate to the DAQs? > > -- Be Happy. Don't Worry about the difference between lose and loose..Article: 121756
Hello, I am implementing a PCIe design for the HiTechGlobal HTG-V4-PCIe60 (Virtex 4 FX60 and FX100) board and having a little difficulty. What I'm trying to do is create a minimalistic base design that will eventually be used to build larger applications. The basic idea is to get the host system to see the card on the PCIe bus via a probe. I do not want to handle transactions or any other functions unless it is necessary for the board to be seen by the host. Drivers (kernel modules) for the card is planned to be done later as well. I am using the Xilinx pci_express_v3_4 8-lane endpoint core, which comes with an example design and scripts to implement it. After modifying to the UCF, the example design work with no problem but I would like implement my own design using ISE. In an ISE project I have included the pci_express_v3_4.ngc file and created a top level module that instantiates the core (instantiation code provided by Xilinx). The top module includes all PCIe interface signals for the 8- lane core, transaction signals (rxn and txn), and configuration signals that are illustrated in the Xilinx LogiCORE PCI Express v3.4 Users Guide. I deasserted a the majority of the configuration signals since asserting would cause interrupts, error reports, etc. Uploading the design as-is does not work, so clearly I am missing something. Unfortunately I haven't been able to find a Xilinx document that details exactly what is needed to get the PCIe core to work. What signals must be present and what values must they hold? Does there have to be a transaction handler present even though there are no transactions to be handled? Must the core's input signals be assigned a value or could we justs let ISE set a default? What values do I need to set the configuration signals at startup? What I'm looking for is the bare minimum. Some document (or someone) that outlines the procedure (and "must haves") for a minimalistic ISE design using the endpoint core. Does such a document exists? Like I said before, I just want the host system to see the board on the bus. Transactions and all other functionality will be handled later. Does anyone know what I need to do or have some useful techniques (ideas, documents, links, etc.) than could help me?Article: 121757
On Jul 12, 11:56 am, "Geronimo Stempovski" <geronimo.stempov...@arcor.de> wrote: > Hi folks, > > I am planning to design a PCB featuring three Virtex-4 FX60 FPGAs and some > periphery. The three FPGAs are needed due to the data processing complexity > and the amount of high-speed IOs (MGTs). What I am most concerned about > right now is to find an appropriate clocking solution. > > In my opinion, there are mainly three alternatives to design the clocking > scheme: > > a) connection of the clock in a star-like topology, feeding each of the > three FPGAs with the same clock signal (which has to be possibly duplicated > by a clock buffer to generate three out of one clock reference signal, > thereby introducing additional jitter) > > b) clock in daisy-chain, feeding each of the three FPGAs with the identical > clock signal which is routed from one device to another (in terms of jitter > this is also not an optimal solution) > > c) each FPGA device is supplied with its own clock (which than can be > optimally routed to the device in short distances), but synchronization is a > major issue then > > Does anyone have sufficient experience in designing clock trees and is > willing to share his experience, comments, hints and suggestions with me? > > Thanks in advance > > Gero Don't want to be too salesy - but why not take a look at Lattice Clock Manager devices - very high performance, very low jitter, and per pin voltage, termination, and skew control - just the ticket for FPGAs without PLLs ;-) http://www.latticesemi.com/products/ispclock/index.cfm?source=topnav&jsessionid=ba30b6308a23$24$03$3 (of course, our ECP2M FPGA family might also be of interest ;-) ) hope the design goes well - Mike Thomas lattice SFAE NY/NJArticle: 121758
Mike Treseler wrote: > > I believe that digital design students > would be better off not having a board at all > until they are fully competent with hdl language, > simulation and synthesis. > > To learn those basics, all I need is an editor, > simulator and RTL viewer. I can only partly agree with that. Yes, the students are novices, and what they get the boads to do will be very simple, but the Boards/Hardware give an important psychology connection to the real world. A digital design student graduating never having seen a device, or data sheet, is not a good idea. I'd rate the microcontroller sector, ahead of the FPGA on in this aspect - there are some truly impressive 'USB Stick' eval boards at low prices out there. -jgArticle: 121759
Is there a way to convert a schematic file (.sch) into a functional verilog module (.v/.vf) from the command line? I want to do this so I can compile the resulting verilog file with modelsim for simulation. I know how to do this from the ISE GUI, but it would be much easier if I could do it from the command line. Please bear in mind that I am using Xilinx ISE 9.1i or ModelSim XE III/ Starter 6.2c when posing your answers. I appreciate any help you can provide. Kind Regards, Craig. P.S. Out of curiosity, is there a way to simulate a project with mixed verilog and schematic files in ModelSim from the command line?Article: 121760
I am using V5 GTP. As per my understanding, the GTP output should swing between 1.2V and 700mV and common mode voltage of about 950mV. But when I look at this using oscilloscope, I see that the GTP output swings between 625mV and 75mV with common mode voltage at about 350mV. I am not sure why I am not seeing the common mode voltage of 950mV - as per the V5 specification. Ideally I am looking for common voltage in betwen 400mV to 790mV. If you have an idea on acheiveing this then please let me know. EddieArticle: 121761
Craig, Depending on what tools you used to capture the schematic, and what models your flow supports, asking for a "verilog netlist" is a feature of some tools. The resulting verilog netlist will be at the transistor and wire level, or gate level (which in the hierarchy is made up of gates and wires), and will basically allow you to functionally simulate the schematic, less any timing, or 'analog' behavior (after all, you only have 1's, 0's, 'don't cares', tri-states, and unknowns). This is commonly done for ASIC/ASSP design: one may synthesize higher level RTL (like verilog and VHDL descriptions that have no specific technology or functional modules like 'multiply this by that') into lower level schematics of transistors (from standard cell library gates). The resulting circuit netlist (like a spice netlist) will allow one to perform many good (analog) simulations, but will either take too long, or blow up, if there are close to a billion devices in the chip. The next choice is to simulate the verilog netlist of the wires and transistors, which will run much much faster, but will be unable to tell you anything about time, voltage, or current. Since you posted on c.a.f. I am going to presume your HDL was synthesized for a FPGA, and then it was placed, and routed in the FPGA. You may also have a schematic of how the HDL blocks are connected together. The resultant netlist is in some format (for Xilinx: XDL) which may then be simulated quickly for the functional behavior. In an FPGA, the translation all the way down to transistors is not provided, like it would be in the ASIC/ASSP flow.... Make sense? AustinArticle: 121762
Rob wrote: > Jim, > > Yes, Antti is correct. Altera moved MaxIII behiind CycloneIII and > StratixIII. So I guess the key question is "How far behind ?" I see CycloneIII has March data, and StratixIII has May data, and we are now into July.... ? -jgArticle: 121763
http://direct.xilinx.com/bvdocs/userguides/ug196.pdf page 112 page 202 MGTAVTTX = ? on your board? Like many things, the GTP is programmable, and there are external supplies to set the common mode voltages to be whatever you would like them to be (in order to meet all the possible standards more easily). Austin Eddie H wrote: > I am using V5 GTP. As per my understanding, the GTP output should swing between 1.2V and 700mV and common mode voltage of about 950mV. > > But when I look at this using oscilloscope, I see that the GTP output swings between 625mV and 75mV with common mode voltage at about 350mV. > > I am not sure why I am not seeing the common mode voltage of 950mV - as per the V5 specification. > > Ideally I am looking for common voltage in betwen 400mV to 790mV. If you have an idea on acheiveing this then please let me know. > > EddieArticle: 121764
Do you have the transmit impedance getting calibrated properly per chapter 10 (page 201) of UG196? http://www.xilinx.com/bvdocs/userguides/ug196.pdf <Eddie H> wrote in message news:eea7f3e.-1@webx.sUN8CHnE... >I am using V5 GTP. As per my understanding, the GTP output should swing >between 1.2V and 700mV and common mode voltage of about 950mV. > > But when I look at this using oscilloscope, I see that the GTP output > swings between 625mV and 75mV with common mode voltage at about 350mV. > > I am not sure why I am not seeing the common mode voltage of 950mV - as > per the V5 specification. > > Ideally I am looking for common voltage in betwen 400mV to 790mV. If you > have an idea on acheiveing this then please let me know. > > EddieArticle: 121765
Nico Coesel wrote: > austin <austin@xilinx.com> wrote: > > >>Nico, >> >>I don't make things up. I just read about it in eetimes. >> >>opencores is up for sale, and there is no one who cares to "take it." >> >>What does that say? > > > That nobody is interested in the brand 'Opencores'. But according to > the magazine articles you refer to, they attract a lot of engineers > working with programmable logic and ASIC. SO the content of the > website is attractive enough. It would be a great buy for an FPGA > vendor to push their own products. Certainly it would look like a good fit for Lattice to host this. Then they can develop an eco system around their own OpenCores, whilst allowing others space to live as well. I'd imagine the upper echelons of Xilinx would gag on their own legal-red-tape, even thinking about this idea ;) Companies _can_ have too many lawyers (but never too many engineers :) -jgArticle: 121766
Jim Granville wrote:
> Mike Treseler wrote:
>>
>> I believe that digital design students
>> would be better off not having a board at all
>> until they are fully competent with hdl language,
>> simulation and synthesis.
>>
>> To learn those basics, all I need is an editor,
>> simulator and RTL viewer.
>
> I can only partly agree with that.
>
> Yes, the students are novices, and what they get the
> boards to do will be very simple, but the Boards/Hardware
> give an important psychology connection to the real world.
I hear what you're saying. A scope trace
is slightly more real than a sim waveform.
But from the novice postings here,
I have to conclude that the psychology connection
is sometimes a magic recipe rather than an understanding
of what's really going on to make that LED flash.
> A digital design student graduating never having seen a
> device, or data sheet, is not a good idea.
I agree. A capstone or thesis project should involve
serious work with real hardware. However, the instructor
should provide hardware demonstrations during lectures as well
-- as in physics 101.
-- Mike Treseler
Article: 121767Austin, How accurate is the timing for post place and route simulations using the Xilinx libraries? ---Matthew Hicks > Craig, > > Depending on what tools you used to capture the schematic, and what > models your flow supports, asking for a "verilog netlist" is a feature > of some tools. > > The resulting verilog netlist will be at the transistor and wire > level, or gate level (which in the hierarchy is made up of gates and > wires), and will basically allow you to functionally simulate the > schematic, less any timing, or 'analog' behavior (after all, you only > have 1's, 0's, 'don't cares', tri-states, and unknowns). > > This is commonly done for ASIC/ASSP design: one may synthesize higher > level RTL (like verilog and VHDL descriptions that have no specific > technology or functional modules like 'multiply this by that') into > lower level schematics of transistors (from standard cell library > gates). > > The resulting circuit netlist (like a spice netlist) will allow one to > perform many good (analog) simulations, but will either take too long, > or blow up, if there are close to a billion devices in the chip. The > next choice is to simulate the verilog netlist of the wires and > transistors, which will run much much faster, but will be unable to > tell you anything about time, voltage, or current. > > Since you posted on c.a.f. I am going to presume your HDL was > synthesized for a FPGA, and then it was placed, and routed in the > FPGA. > > You may also have a schematic of how the HDL blocks are connected > together. The resultant netlist is in some format (for Xilinx: XDL) > which may then be simulated quickly for the functional behavior. > > In an FPGA, the translation all the way down to transistors is not > provided, like it would be in the ASIC/ASSP flow.... > > Make sense? > > Austin >Article: 121768
Jim, It isn't the lawyers that would have a problem with this: it is the regular rank and file engineers. We understand that most of what is there is (sorry) very poor quality, and that would reflect badly on Xilinx. Very badly indeed. No company would put there name on such a mess: it is too much of a liability. Would you tell your boss that all your IP came from such a source? And expect to stay employed? Think of it: do you ever get an email that says "I used that code, understood it completely without even reading anything, and it worked, and I am sooo happy." Yes, sure. Rather, you get (tens of) thousands of complaints....just read the newsgroup! Problems that are non-problems, problems that are easily solved by reading the data sheet, problems solved by a few simple experiments, it matters not: most people see a problem, and call up the help desk. If you are their biggest supplier, you get blamed for everything else (and we do often solve problems that do not even belong to us). "Your chip is breaking my power supply" (* a real complaint!). We analyzed and fixed their power supply for them. Don't get me wrong: I love getting tens of thousands of web cases. It allows us to measure how we improve, and measure how satisfied our customer's are. With 350,000 seats of software and tens of thousands of engineers designing every hour of every day, the web cases are a "heatbeat" and tell us immediately how well we are doing what we promised to do. And this is for products, code, manuals, and services where we spend a great deal of time on, and pay a lot of attention to quality. I was told many years ago by the "Bell System" that one half of all returned boards had no problems (the problem was in the imagination of the technician). This holds as true today as it did then: most (more than 1/2) of all reported problems are not really a problem (in a well run organization with a great product). Yes, all reported issues are taken seriously, and followed through on. Every time. That is how you get better. Imagine what would happen with a cornucopia of stuff of totally unknown quality, and inadequate documentation! In other words, real garbage? Lawyers? That is the least of our concerns: how about staying in business? You can't impress anyone (for long) with having more garbage than your competitor. AustinArticle: 121769
As a follow-up, I found a document wp237, from Xilinx, that explains the details of the offset in and offset out constraints fairly well. In addition to the aformentioned methods, I also found out that in Synplify, you can specify that all IO registers be packed into the IOB (syn_useioff) which won't allow retiming outside of the border registers. This way I can let the tool retime the internal stages and don't have to worry about my borders being violated. ---Matthew Hicks > Thanks, I'll work on applying those constraints tomorrow. For some > reason, I thought those constraints were for informational purposes > and not something I could use to handcuff the tools. > > I viewed the informational (sales) items on retiming and they said it > doesn't affect the functionality of the design, so I figured a little > extra otimazation never hurt. I just didn't think to look at the > other timing parameters beside Fmax. Now I know. > > ---Matthew Hicks > >> "Matthew Hicks" <mdhicks2@uiuc.edu> wrote in message >> news:b66e6524a10f8c9905f5bb67596@news.ks.uiuc.edu... >> >>> I am using Synplicity Synplify Premiere 8.8 and I ran into the >>> problem that it keeps retiming my designs such that a great deal of >>> the logic is placed before the input registers and/or after the >>> output registers. I was clued into this when I went finish >>> implementing the design in ISE and the timing report listed a delay >>> for the input to clock or clock to output (or both) that was longer >>> than the reported minimum period for the design. While looking at >>> timing this close is new to me, I'm guessing the largest of these >>> three values is the fastest that I can clock my design at, barring >>> any multicycle or false paths. Is there any way to constrain >>> Synplify so it won't retime logic outside of the designs main input >>> and output registers? >>> >>> ---Matthew Hicks >>> >> Specify your input and output delay constraints. >> >> While I prefer the "OFFSET IN BEFORE" and "OFFSET OUT AFTER" >> constraints used by Xilinx, the Synplify constraints are the "OFFSET >> IN AFTER" and "OFFSET OUT BEFORE" style constraints popularized by >> Synopsys which specify the cycle time from the common clock in the >> external chip to your FPGA and from the FPGA to the external chip, >> virtual-clock to virtual-clock. >> >> I get around the problem by not using retiming. >>Article: 121770
Matthew, We stand by the speeds files. In other words, if the actual part is slower, on any path or feature, it may be returned (via the RMA process), and we issue a new one that meets the specifications. I have taken part in many such cases, and on only two occasions, we had made a mistake in the speeds file, and we had to offer a faster speed grade part to the customer, or work with them to improve their timing to get around the failing path. It is so extremely painful to have to issue a new (slower) speeds file for our customers; we only do that when we have no other alternative whatsoever (and you can believe we get hammered internally for having the wrong number in the speeds file). The same is true for IBIS models, packaging files, etc. AustinArticle: 121771
MAX3 will not be this year. Altera will be doing MAX2Z (Zero Power) this year. The release of C3 depends on package. I'm to understand that some C3 devices will be in production 3Q of this year, some more 4Q of this year, and I think the full line is supposed to be in prodcution by 1Q of '08. I happen to be targeting a C3 device for a prodcut that Altera tells me will be ready 3Q of this year: EP3C10F256 I don't have any information on S3. "Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message news:4696a0a9$1@clear.net.nz... > Rob wrote: > >> Jim, >> >> Yes, Antti is correct. Altera moved MaxIII behiind CycloneIII and >> StratixIII. > > So I guess the key question is "How far behind ?" > I see CycloneIII has March data, and StratixIII has May data, > and we are now into July.... ? > > -jg > >Article: 121772
Sorry I'm trying to be very practical here. I just want to know what command line tools I can use to create a verilog file from a schematic file. How do I do that from the command line using either ISE 9.1i or ModelSim? I'd appreciate it if you could give me an example? Lets say my schematic is named: circuit.sch I'd like to create a verilog file (netlist) that is equivilent to it, say: circuit.v I'm guessing at the command line it would be something like: xst -sch circuit.sch > circuit.v I have read through all the user manuals, developer manuals, etc... I can't not figure out how to do this outside of the GUI interface. Thanks again for any help you can provide. Thanks, Craig.Article: 121773
spacegato@gmail.com wrote: > I deasserted a the majority of the configuration signals > since asserting would cause interrupts, error reports, etc. Uploading > the design as-is does not work, so clearly I am missing something. I don't have any experience with PCIe cores, but for PCI the core needs to be able to handle configuration cycles (at least) in order for the BIOS to probe the device. So basically most of the functionality required for transaction processing must be in place in even a minimal design. If I were you I'd instantiate a fully functional/connected core and work backwards from there... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 121774
I'll take this as a 'no' then ? :) The topic is not about buying the cores, but about providing a hosting/forum shell, where such cores can "percolate away", and I'm sure a company with the right culture could make this work. I did not expect Xilinx to embrace the idea, but it does seem a better fit for Lattice. -jg austin wrote: > Jim, > > It isn't the lawyers that would have a problem with this: it is the > regular rank and file engineers. We understand that most of what is > there is (sorry) very poor quality, and that would reflect badly on > Xilinx. Very badly indeed. > > No company would put there name on such a mess: it is too much of a > liability. Would you tell your boss that all your IP came from such a > source? And expect to stay employed? > > Think of it: do you ever get an email that says "I used that code, > understood it completely without even reading anything, and it worked, > and I am sooo happy." > > Yes, sure. > > Rather, you get (tens of) thousands of complaints....just read the > newsgroup! Problems that are non-problems, problems that are easily > solved by reading the data sheet, problems solved by a few simple > experiments, it matters not: most people see a problem, and call up the > help desk. If you are their biggest supplier, you get blamed for > everything else (and we do often solve problems that do not even belong > to us). > > "Your chip is breaking my power supply" (* a real complaint!). We > analyzed and fixed their power supply for them. > > Don't get me wrong: I love getting tens of thousands of web cases. It > allows us to measure how we improve, and measure how satisfied our > customer's are. With 350,000 seats of software and tens of thousands of > engineers designing every hour of every day, the web cases are a > "heatbeat" and tell us immediately how well we are doing what we > promised to do. > > And this is for products, code, manuals, and services where we spend a > great deal of time on, and pay a lot of attention to quality. > > I was told many years ago by the "Bell System" that one half of all > returned boards had no problems (the problem was in the imagination of > the technician). This holds as true today as it did then: most (more > than 1/2) of all reported problems are not really a problem (in a well > run organization with a great product). Yes, all reported issues are > taken seriously, and followed through on. Every time. That is how you > get better. > > Imagine what would happen with a cornucopia of stuff of totally unknown > quality, and inadequate documentation! In other words, real garbage? > > Lawyers? That is the least of our concerns: how about staying in business? > > You can't impress anyone (for long) with having more garbage than your > competitor. > > Austin
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