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Hi, gouaich wrote: > You all probably know that embedded systems are more and more > considered as hot topics to be though at universities. I will be in > charge of managing a complete course for graduate students on embedded > system with a focus on software engineering and operating systems for > embedded platforms. > > Since having only a theoretical course is quite a boring activity : ) > I am looking for the best platform students can experiment and play > with (doing labs, projects and so on) For hardware you really can't beat the Xilinx/Digilent S3E-500 boards for price (USD$150 retail) and capability. 3-bit VGA out (can be hacked up to more bits), LCD char display, LEDs, switches, ADC/DAC, ethernet, and lots of memory. You may have a case to make to the Xilinx University Program for a donation - go to www.xilinx.com/univ This board will do both elementry digital logic teachuing as well as CPU / system-on-chip, embedded OS projects. > Obviously, free and open source platforms are privileged since this is > an education purpose in a university that cannot afford paying money > for licences; or even managing a complex relation with an industrial > partner with some 'discounts' on licences. I'm biased, but in terms of OS, you can run Linux (2.4 and 2.6) on it with a freely available HW/SW development environment (http://developer.petalogix.com). There is an active community and mailing list. The only thing I don't like about these boards is the USB programming model, if you are using Linux as your host development environment, the USB driver is a bit flakey. Once you get it setup it's ok, but there can be some frustration early on. Look to the archives of this NG for ways people have got around that with open source USB drivers. Regards, JohnArticle: 122026
On Jul 17, 4:21 am, Antti <Antti.Luk...@googlemail.com> wrote: > Hi > > I just burnt my fingers trying to lift off the Xilinx Spartan 3A > Starterkit > the all corner with power supplies is extremly hot - I wonder if that > is > normal or not. > > I already own 3 FPGA boards designed by Digilent with burned in Power > supplies > so I am little worried that I may get a 4th one into my collection of > "dead digilent garbage" :( > > The board was powered maybe 3 minutes and FPGA was configured with > original bitstream > for the dataflash programming, and yes incoming power is 5V not 9 > > Any ideas? Should I be worry? The power supply IC are so tiny that it > is defenetly not possible > to mount any heat sink on them :( FWIW, my Spartan-3E 1600 kit from Digilent had a burning hot power regulator (just short of smoking). Digilent swapped the board for one that didn't do that, but was otherwise identical. I suspect there might be something wrong with yours. TommyArticle: 122027
>> >> I know if you have used the chip scope core inserter you can import >> the project file (*.cdc) into chipscope analyser and the signal names >> will be imported into the analyser. I have not used the chip scope >> core generator in a long time but I beleive there is a similar option >> to "generate bus / signal name example File (*.cdc) " which you can >> modify to include the signal names as connected and then import it in >> the a similar way. >> >> Hope this helps >> >> Adam >> > > Thanks for replying Adam. I use chipscope directly within XPS, i.e. I > just add the PLB IBA and ICON the design like any other IP core. I set > the chipscope parameters, wire up blocks, then build it and download the > bitstream all within XPS. Then I start the chipscope analyzer from > outside of XPS and it finds the core and seems to work, except for no > meaningful waveform names. I tried running the standalone versions of > chipscope generator and inserter, but it's not clear how to get that > into my xps framework. Since they supply the chipscope IP cores within > XPS there must be a way to use them in that context? > > -Jeff Even when you use XPS, it generates a CDC file that you should import from within analyzer. This cdc file will be in: $(PRJ)/implementation/chipscope_plb_iba.../*.cdc -SivaArticle: 122028
Peter Wallace wrote: > No matter what options I use, the bus hold circuits are enabled on the > inputs of a XC9572XL (same problem with 95144XL) in a design of ours. I've tried > ISE6.3 and WEBPack 9.1, no difference. > > The reason I want high impedance inputs is that they are used with a high > value series resistor (and clamp diodes) as part of a power MOSFET > out-of-saturation short circuit protection. > > If anyone has experience with this or especially how to solve it I would > be very grateful... > > Peter Wallace I seem to remember you have to open the advanced options **after** compiling in the fitter tool where you get the option to set the default pin state; unfortunately, I seem to recall you can't set it to Hi-Z or input (F***ing stupid). I don't have the tool open now, but I had the same problem a while ago. Once you compile, the options magically appear - amazing, even if you can't make it do what you want. Cheers PeteSArticle: 122029
I want to program an FPGA to generate two-dimensional, 10-bit video white noise. Any suggestions? I'm not sure if an independent LFSR per bit would work. If so, would I want different lengths per bit, or would I just initialize the different bits at different times? Thanks. PeteArticle: 122030
I spend most of my day trying to minimize dark noise and you're looking to add white noise. Sorry for the useless post, but this struck me as funny. Out of curiosity, what is the application? "Pete Fraser" <pfraser@covad.net> wrote in message news:139qo03ef5pigbb@news.supernews.com... >I want to program an FPGA to generate two-dimensional, > 10-bit video white noise. Any suggestions? I'm not sure if an > independent LFSR per bit would work. If so, would I want > different lengths per bit, or would I just initialize the different > bits at different times? > > Thanks. > > Pete >Article: 122031
John_H wrote: >>> My ohmmeter walked away at work, besides - I'd need an ohmmeter to >>> check my ohmmeter. Don't they have high impedance outputs even >>> when the resistance measurement goes to the 0-20 ohm range? I wrote: >> No. John_H wrote: > So every time I check for a connection (sub-ohm) you think I'm > shorting the battery? No. There's a lot of room between "shorting the battery" and "high impedance". I suppose it comes down to "high impedance" not having a clear quantitative definition.Article: 122032
On Jul 16, 4:51 pm, "KJ" <kkjenni...@sbcglobal.net> wrote: > "Andy Peters" <goo...@latke.net> wrote in message > > news:1184622931.288181.283710@x35g2000prf.googlegroups.com...> On Jul 16, 2:37 pm, Jim Granville <no.s...@designtools.maps.co.nz> > > wrote: > >> steve.l...@xilinx.com wrote: > >> > The ISE Classics release is not a one year license (it's perpetual). > >> > Also, I think we sent out a letter to customers telling them they could > >> > continue to use their current 4K/Spartan licenses forever. > > >> > Yes, rehosting the flex license was an issue. We tried, but were > >> > unsuccessful, to negotiate that with Synopsys. > > >> In the instance mentioned of a new hard drive, surely one can > >> simply edit the HD ID, to match what the license expects ? > > > Doesn't work. I've tried. > > You wouldn't find anybody licensing their software keyed to such an easily > editable thing if you could change so readily. > > KJ Hi, I have successfully transfered a Synopsys HD-locked license to a replacement drive by changing the drive ID. You need to get -both- copies of the DriveID, but (as I said earlier) a 2-minute google will find you a program that does it all for you. G.Article: 122033
"Pete Fraser" <pfraser@covad.net> writes:
> I want to program an FPGA to generate two-dimensional,
> 10-bit video white noise. Any suggestions? I'm not sure if an
> independent LFSR per bit would work. If so, would I want
> different lengths per bit,
If they're running on the same clock, you are likely to see an
obvious pattern to the bits, especially if they are the same length
LFSRs.
If you are using an FPGA that has hardware multipliers (as most do
nowdays), I'd suggest using a linear congruential generator:
http://en.wikipedia.org/wiki/Linear_congruential_generator
What you want to avoid is a modulus that isn't a power of two. The
first set of coefficients listed in the "Example LCGs" section uses
a modulus of 2^32. It generates a 32-bit pseudo-random number for
each multiply, so you could get three 10-bit video samples per
iteration.
In typical Xilinx FPGAs, you get 18-bit signed multipliers, so
you would build a 32-bit unsigned multiplier from four of those and
some adders. Maybe the tools can infer that from a Verilog or VHDL
multiplication operator, or maybe you can use Coregen.
If your data rate requirement isn't too high, you can implement
the 32-bit multiplier using a single hardware multiplier cycled
four times.
It is possible that an LCG will still result in too much pattern
for your application. If so, it is possible to implement the
Mersenne Twister in hardware. While it is not suitable as a
source of pseudorandom sequences for cryptography, it has a long
enough period (approx. 10^600) that it should be suitable as a general
noise source.
Eric
Article: 122034On Tue, 17 Jul 2007 12:25:05 -0500, Jon Elson <elson@pico-systems.com> wrote: <snipped> > I'm using Xilinx ise 4.2i, which is one of the last versions that supported the 5 V chips. <snipped> >Jon Jon; Last year I was using ISE 7.1 (SP4) for doing XC95108 and XC95216 (XC95288?) CPLD designs. BTW, ISE v6.3 was reasonably sized; the code bloat started with v7.1. ISE v8 and up are so huge they will only fit on DVDs. -Dave PollumArticle: 122035
x@x.com wrote: > On Tue, 17 Jul 2007 12:25:05 -0500, Jon Elson <elson@pico-systems.com> > wrote: > <snipped> > >>I'm using Xilinx ise 4.2i, which is one of the last versions that supported the 5 V chips. > > <snipped> > >>Jon > > > Jon; > Last year I was using ISE 7.1 (SP4) for doing XC95108 and XC95216 > (XC95288?) CPLD designs. BTW, ISE v6.3 was reasonably sized; the code > bloat started with v7.1. ISE v8 and up are so huge they will only fit > on DVDs. Hmm, maybe I believed Xilinx's own material, which I think in ise 5.2 or whatever said it would be the last release to support the 5 V chips. Very interesting to hear that 7.1 handles them also. What about 5 V Spartan? I do more of that then 9500 parts. JonArticle: 122036
On 2007-07-17, PFC <lists@peufeu.com> wrote: > > Actually, I possibly skrewed up ;) in my datasheet reading... > XPS can load a parallel flash if your design contains an opb_emc memory > controller though. Yes, if you make a design with some RAM and a parallel flash, the Xilinx tools will build an application to run on this design (I'm thinking PPC here, but maybe it also does this if you include microblaze?) that will program the flash memory. It's pretty slow, though. As soon as we had our own stuff booting and talking on the network we switched to programming that way. > So for safety I put a JTAG Platform Flash to configure the FPGA. SPI > flash will just store software (or maybe even not be populated). If it makes you feel better, the hardware guys at work put platform flash down on the first few revs of a much more complex board than yours (ultimately booted by a CPLD sequencing the parallel flash) just to be sure the FPGA would configurable right away... (btw, I just got my pcbs today and assembled my FLEX board and everything works! yay!) -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 122037
Andy Botterill wrote: > If you can measure Idd in the positive supply line you could try the > following. > > Turn all 7 outputs high. Measure Idd. > Turn one output low. Measure Idd. > > Increase the number of outputs low until all are off. Measure Idd each > time. > > The changes of Idd should be comparable to the output IOH. > With no load on the outputs, this shouldn't make any difference. > Drive all inputs high. Measure Idd. Why should changing an input from high to low change the Idd, when there is nothing connected to the output pin? > > Turn each output off and note the change in Idd. Unless you have low > value pullups/pulldowns you may have to measure all high then all low. > > The will give you an indication of the input current taken by all of > your input cells. Does it compare with your datasheet? > With nothing connected to any input, there should be no input current. > Ideally you can do this without changing the output state. Your design > may not ket you do this. > > Take you original Idd and subtract the output current and input current. > This gives you the active supply current+plus any static pin clashes. > > It's worth running a dvm over pins which you think are inactive just to > make sure that they are floating. They are all grounded by the default "ground all unused pads" option, which Xilinx recommended. Anyway, I did some more current measurements : erased 23 mA simple config 39 mA complex config 75 mA The "simple config" is a design that patches a bug in an ASIC, it has 8 D flip-flops and 6 gates, so it uses only a small number of product terms and MCs in the 9536. That current draw is still WAY over what is predicted by Xilinx's formula, which is now clearly wrong in my opinion. This problem has gone from a "help me fix my mistake" situation to a "help me convince Xilinx to publish a better procedure for power estimation". I'm not asking for even a 10% accuracy, but up to 200% error is not acceptable! JonArticle: 122038
On 2007-07-17, Jeff Cunningham <jcc@sover.net> wrote: > adam.taylor@selex-sas.com wrote: >> I know if you have used the chip scope core inserter you can import >> the project file (*.cdc) into chipscope analyser and the signal names > > Thanks for replying Adam. I use chipscope directly within XPS, i.e. I > just add the PLB IBA and ICON the design like any other IP core. His answer still applies. File | Import, find your cdc file, select the right ILA (beware the ila selection is reset after you select the file), hit ok. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 122039
Eric Smith wrote: > If they're running on the same clock, you are likely to see an > obvious pattern to the bits, especially if they are the same length > LFSRs. What if their periods are all relatively prime? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 122040
Jon Elson wrote:
>
> Anyway, I did some more current measurements :
> erased 23 mA
> simple config 39 mA
> complex config 75 mA
>
> The "simple config" is a design that patches a bug in an ASIC, it has 8
> D flip-flops and 6 gates, so it uses only a small number of product
> terms and MCs in the 9536. That current draw is still WAY over what is
> predicted by Xilinx's formula, which is now clearly wrong in my
> opinion.
In an ideal world, the Fitter would read a simple model file,
and calculate the Power figures for you.....
> This problem has gone from a "help me fix my mistake"
> situation to a "help me convince Xilinx to publish a better procedure
> for power estimation". I'm not asking for even a 10% accuracy, but up
> to 200% error is not acceptable!
I notice that the 9536XL power eqn adds Product Term values, and
they have
ICC(mA) = MCHS(0.175*PTHS + 0.345) +
MCLP(0.052*PTLP+ 0.272) +
0.04 * MCTOG(MCHS +MCLP)* f
So I'd ask Xilinx what those coefficents are for the XC9536.
this formula does show config can have a BIG effect on the Icc.
or, you could use you numbers above, to get something like
MCLP(0.48*PTLP+ 0.640) for the older part.
-jg
Article: 122041Jon Elson wrote: > > Anyway, I did some more current measurements : > erased 23 mA > simple config 39 mA > complex config 75 mA Another simple check you could do, is flip the macrocells to HIGH power, and check the Icc does actually increase - just to verify that setting is taking effect. -jgArticle: 122042
Hi, I am wondering what kind of issues I should look for when designing in DDR SDRAM for extended temperatures. For e.g. does temp. compensated refresh cycles extend to ambient temperatures of -40 to +85 deg C and over? Any other interesting things that could happen? Thanks and best regards, -sanjayArticle: 122043
I've figured out how to compile the RTL in Xilinx ISE Webpack9.2i and Altera Quurtus II 7.1. (It just took a few simple RTL-edits.) But what about the JTAG-debug unit? It seems to use the Lattice's JTAG-block. Can I just replace this with a generic JTAG TAP-controller, and then use a Xilinx-hosted Mico32 with a Lattice download-cable?Article: 122044
Jim Granville wrote: > Jon Elson wrote: > >> >> Anyway, I did some more current measurements : >> erased 23 mA >> simple config 39 mA >> complex config 75 mA > > > Another simple check you could do, is flip the macrocells to > HIGH power, and check the Icc does actually increase - just > to verify that setting is taking effect. Oh, yeah! It really increases, to about 130+ mA! I didn't let ir run for more than a few seconds at that level, as the little chip gets REALLY hot, well over 50 C at the package exterior. This test was done when there was significantly less logic in the design, so it would likely be worse now. JonArticle: 122045
when I synthesize the FPGA (ProASIC PLUS) in Synplify of Libero I have got a lot of warnings: "Unbound component (DFF or AND2...) mapped to black box". It seems that don't recognize the basic components, =BFdo I need any library? thanksArticle: 122046
"Pete Fraser" <pfraser@covad.net> wrote in message news:139qo03ef5pigbb@news.supernews.com... >I want to program an FPGA to generate two-dimensional, > 10-bit video white noise. Any suggestions? I'm not sure if an > independent LFSR per bit would work. If so, would I want > different lengths per bit, or would I just initialize the different > bits at different times? > > Thanks. > > Pete Use a 64 bit PRNG and randomly pick out the bits. I have used this in the past on a video generator using 12 bit video with great success with absolutely no visible repeat patterning. http://img.villagephotos.com/p/2007-7/1268869/prng64.jpg IckyArticle: 122047
"Icky Thwacket" <it@it.it> wrote in message news:469dc3ea$0$1609$ed2619ec@ptn-nntp-reader02.plus.net... > > "Pete Fraser" <pfraser@covad.net> wrote in message > news:139qo03ef5pigbb@news.supernews.com... >>I want to program an FPGA to generate two-dimensional, >> 10-bit video white noise. Any suggestions? I'm not sure if an >> independent LFSR per bit would work. If so, would I want >> different lengths per bit, or would I just initialize the different >> bits at different times? >> >> Thanks. >> >> Pete > > > Use a 64 bit PRNG and randomly pick out the bits. I have used this in the > past on a video generator using 12 bit video with great success with > absolutely no visible repeat patterning. > > http://img.villagephotos.com/p/2007-7/1268869/prng64.jpg > > Icky OOOps - sorry its actually a 32 bit PRNG with a 32 bit extension used for increased bit spacing for better randomization when generating a multibit video level.Article: 122048
"Eric Smith" <eric@brouhaha.com> wrote in message news:qh8x9efr5b.fsf@ruckus.brouhaha.com... > "Pete Fraser" <pfraser@covad.net> writes: >> I want to program an FPGA to generate two-dimensional, >> 10-bit video white noise. Any suggestions? I'm not sure if an >> independent LFSR per bit would work. If so, would I want >> different lengths per bit, ..snip > > It is possible that an LCG will still result in too much pattern > for your application. If so, it is possible to implement the > Mersenne Twister in hardware. I have one on my website if you need an example, http://www.ht-lab.com/freecores/mt32/mersenne.html Hans www.ht-lab.com While it is not suitable as a > source of pseudorandom sequences for cryptography, it has a long > enough period (approx. 10^600) that it should be suitable as a general > noise source. > > EricArticle: 122049
On 07/17/2007 01:21 PM, Antti wrote: > Hi > I just burnt my fingers trying to lift off the Xilinx Spartan 3A > Starterkit > the all corner with power supplies is extremly hot - I wonder if that > is > normal or not. > ... Maybe is not so normal... I've a spartan-3 starter kit and a spartan-3e 1600 board both from digilent and quite all IC on them cannot burn Your finger... Just on the spartan-3e 1600 board the ethernet phy IC is a little bit hotter than other IC but absolutly touchable with fingers Sandro
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